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/optee_os/core/include/mm/
H A Dtee_pager.h1 /* SPDX-License-Identifier: BSD-2-Clause */
3 * Copyright (c) 2016-2021, Linaro Limited
19 * tee_pager_early_init() - Perform early initialization of pager
26 * tee_pager_get_table_info() - Fills in table info for address mapped in
27 * translation table managed by the pager.
31 * Returns true if address is in the pager translation tables else false
36 * tee_pager_phys_to_virt() - Translate physical address to virtual address
37 * looking in the pager page tables
46 * tee_pager_set_alias_area() - Initialize pager alias area
48 * pager are aliased
[all …]
/optee_os/core/mm/
H A Dpgt_cache.c1 // SPDX-License-Identifier: BSD-2-Clause
21 * With pager enabled we allocate page table from the pager.
24 * using the interface provided by the pager.
28 * a page is completely unused it's returned to the pager.
30 * With pager disabled we have a static allocation of page tables instead.
34 * threads. In case a thread can't allocate the needed number of pager
73 assert(pgt && pgt->parent); in free_pgt()
74 parent = pgt->parent; in free_pgt()
75 assert(parent->num_used <= PGT_PARENT_TBL_COUNT && in free_pgt()
76 parent->num_used > 0); in free_pgt()
[all …]
H A Dcore_mmu.c1 // SPDX-License-Identifier: BSD-2-Clause
3 * Copyright (c) 2016-2025 Linaro Limited
97 static const char *tz_sdp_match = "linaro,secure-heap";
125 struct tee_mmap_region *old = mem_map->map; in heap_realloc_memory_map()
126 size_t old_sz = sizeof(*old) * mem_map->alloc_count; in heap_realloc_memory_map()
133 mem_map->map = m; in heap_realloc_memory_map()
134 mem_map->alloc_count++; in heap_realloc_memory_map()
140 struct tee_mmap_region *old = mem_map->map; in boot_mem_realloc_memory_map()
141 size_t old_sz = sizeof(*old) * mem_map->alloc_count; in boot_mem_realloc_memory_map()
146 mem_map->map = m; in boot_mem_realloc_memory_map()
[all …]
/optee_os/core/arch/riscv/include/mm/
H A Dgeneric_ram_layout.h1 /* SPDX-License-Identifier: BSD-2-Clause */
26 * Optional directives when pager is enabled:
42 * TEE_SHMEM_START Non-secure static shared memory physical base address
43 * TEE_SHMEM_SIZE Non-secure static shared memory byte size
47 * TDSRAM_BASE On-chip secure RAM base address, required by pager.
48 * TDSRAM_SIZE On-chip secure RAM byte size, required by pager.
62 * ----------------------------------------------------------------------------
65 * +----------------------------------+ <-- CFG_TDDRAM_START
67 * +----------------------------------+
69 * +----------------------------------+
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/optee_os/core/arch/arm/include/mm/
H A Dgeneric_ram_layout.h1 /* SPDX-License-Identifier: BSD-2-Clause */
25 * Optional directives when pager is enabled:
41 * TEE_SHMEM_START Non-secure static shared memory physical base address
42 * TEE_SHMEM_SIZE Non-secure static shared memory byte size
46 * TZSRAM_BASE On-chip secure RAM base address, required by pager.
47 * TZSRAM_SIZE On-chip secure RAM byte size, required by pager.
61 * ----------------------------------------------------------------------------
64 * +----------------------------------+ <-- CFG_TZDRAM_START
66 * +----------------------------------+
68 * +----------------------------------+
[all …]
/optee_os/core/arch/arm/plat-nuvoton/
H A Dconf.mk4 include core/arch/arm/cpu/cortex-armv8-0.mk
38 $(call force,CFG_WITH_PAGER,n,Pager is not supported for NPCM845x)
/optee_os/core/include/kernel/
H A Duser_mode_ctx_struct.h1 /* SPDX-License-Identifier: BSD-2-Clause */
3 * Copyright (c) 2019-2021, Linaro Limited
4 * Copyright (c) 2020-2023, Arm Limited
15 * struct user_mode_ctx - user mode context
17 * @regions: Memory regions registered by pager
28 * @is_32bit: True if 32-bit TS, false if 64-bit TS
H A Dlinker.h1 /* SPDX-License-Identifier: BSD-2-Clause */
29 #define VCORE_UNPG_RX_SZ ((size_t)(__vcore_unpg_rx_end - \
32 #define VCORE_UNPG_RO_SZ ((size_t)(__vcore_unpg_ro_end - \
35 #define VCORE_UNPG_RW_SZ ((size_t)(__vcore_unpg_rw_end - \
38 #define VCORE_NEX_RW_SZ ((size_t)(__vcore_nex_rw_end - \
41 #define VCORE_INIT_RX_SZ ((size_t)(__vcore_init_rx_end - \
44 #define VCORE_INIT_RO_SZ ((size_t)(__vcore_init_ro_end - \
51 #define VCORE_FREE_SZ ((size_t)(__vcore_free_end - \
55 /* No VCORE_FREE range in pager configuration since it uses all memory */
/optee_os/core/arch/arm/plat-rpi3/
H A Dplatform_config.h1 /* SPDX-License-Identifier: BSD-2-Clause */
39 #error "Pager not supported for ARM64"
59 * 0x0840_0000 [ARM Trusted Firmware ] -
60 * 0x0840_0000 [TZDRAM_BASE, BL32_LOAD_ADDR] -
64 * 0x0000_0000 [DRAM0_BASE] -
/optee_os/core/arch/arm/plat-mediatek/
H A Dplatform_config.h1 /* SPDX-License-Identifier: BSD-2-Clause */
16 #error "Pager not supported for ARM64"
/optee_os/core/arch/arm/plat-stm32mp1/
H A Dmain.c1 // SPDX-License-Identifier: BSD-2-Clause
3 * Copyright (c) 2017-2025, STMicroelectronics
4 * Copyright (c) 2016-2018, Linaro Limited
63 IMSG("Platform stm32mp1: flavor %s - DT %s", in platform_banner()
201 * This concerns OP-TEE pager for STM32MP1 to use secure internal
207 * +--------------+ <-- SYSRAM_BASE
211 * +--------------+ <-- SRAM1_BASE (= SYSRAM_BASE + SYSRAM_SIZE)
212 | | full range assigned to non-secure world or
213 * | SRAM1 128kB | to secure world, or to- Cortex-M4 exclusive access
214 * +--------------+ <-- SRAM2_BASE (= SRAM1_BASE + SRAM1_SIZE)
[all …]
H A Dstm32_util.h1 /* SPDX-License-Identifier: BSD-3-Clause */
3 * Copyright (c) 2018-2022, STMicroelectronics
31 * @opp_id: OPP support identifier read from DT property opp-hw-support
95 * @pa if it does not relate to an SRAMx non-aliased memory address.
99 /* Return whether or not the physical address range intersec pager secure RAM */
/optee_os/core/arch/arm/plat-sprd/
H A Dplatform_config.h1 /* SPDX-License-Identifier: BSD-2-Clause */
37 #error "Pager not supported for ARM64"
55 #define TZDRAM_SIZE (0x02000000 - TEE_SHMEM_SIZE)
75 * +------------------+
77 * + TZDRAM +---------+
79 * +--------+---------+
85 #define TA_RAM_SIZE ROUNDDOWN((TZDRAM_SIZE - TEE_RAM_VA_SIZE), \
/optee_os/core/arch/arm/plat-zynqmp/
H A Dplatform_config.h1 /* SPDX-License-Identifier: BSD-2-Clause */
39 #error "Pager not supported for zynqmp"
/optee_os/lib/libutee/include/
H A Dpta_stats.h1 /* SPDX-License-Identifier: BSD-2-Clause */
17 * STATS_CMD_PAGER_STATS - Get statistics on pager
29 * STATS_CMD_ALLOC_STATS - Get statistics on core heap allocations
58 * STATS_CMD_MEMLEAK_STATS - Print memory leakage info to console
63 * STATS_CMD_TA_STATS - Get information on TA instances
77 * STATS_CMD_GET_TIME - Get both REE time and TEE time
79 * [out] value[0].a REE time as seen by OP-TEE in seconds
80 * [out] value[0].b REE time as seen by OP-TEE, milliseconds part
87 * STATS_CMD_PRINT_DRIVER_INFO - Print device drivers information to console
/optee_os/core/arch/arm/kernel/
H A Dboot.c1 // SPDX-License-Identifier: BSD-2-Clause
3 * Copyright (c) 2015-2023, Linaro Limited
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
59 * they are received in a single register when OP-TEE is initially entered.
60 * This limits 32-bit systems to only use make use of the lower 32 bits
63 * 64-bit systems on the other hand can use full 64-bit physical pointers.
102 /* May be overridden in plat-$(PLATFORM)/main.c */
108 /* May be overridden in plat-$(PLATFORM)/main.c */
113 /* May be overridden in plat-$(PLATFORM)/main.c */
118 /* May be overridden in plat-$(PLATFORM)/main.c */
[all …]
H A Dentry_a64.S1 /* SPDX-License-Identifier: BSD-2-Clause */
3 * Copyright (c) 2015-2025, Linaro Limited
4 * Copyright (c) 2021-2023, Arm Limited
12 #include <generated/asm-defines.h>
26 * stack_tmp + (cpu_id + 1) * stack_tmp_stride - STACK_TMP_GUARD
39 /* x0 = stack_tmp - STACK_TMP_GUARD */
192 * [Pager code, rodata and data] : In correct location
195 * initializing pager, first uint32_t tells the length of the data
210 ldp x3, x4, [x1, #-16]!
211 stp x3, x4, [x0, #-16]!
[all …]
H A Dentry_a32.S1 /* SPDX-License-Identifier: BSD-2-Clause */
3 * Copyright (c) 2014-2025, Linaro Limited
4 * Copyright (c) 2021-2023, Arm Limited
10 #include <generated/asm-defines.h>
42 push { r4-r6, lr }
62 1: pop { r4-r6, pc }
139 * Setup required by current implementation of the OP-TEE core:
140 * - Disable data and instruction cache.
141 * - MMU is expected off and exceptions trapped in ARM mode.
142 * - Enable or disable alignment checks upon platform configuration.
[all …]
H A Dlink.mk1 link-out-dir = $(out-dir)/core
3 link-script-dummy = $(arch-dir)/kernel/link_dummy.ld
4 link-script = $(if $(wildcard $(platform-dir)/kern.ld.S), \
5 $(platform-dir)/kern.ld.S, \
6 $(arch-dir)/kernel/kern.ld.S)
7 link-script-pp = $(link-out-dir)/kern.ld
8 link-script-dep = $(link-out-dir)/.kern.ld.d
12 link-ldflags-common += $(call ld-option,--no-warn-rwx-segments)
14 link-ldflags-common += $(call ld-option,--no-warn-execstack)
17 link-ldflags = $(LDFLAGS)
[all …]
/optee_os/core/arch/arm/plat-sam/
H A Dplatform_config.h1 /* SPDX-License-Identifier: BSD-2-Clause */
42 #error "Pager not supported for platform sama5d2"
87 * - 16kb way size (bit19:17=3b001)
/optee_os/core/arch/arm/plat-marvell/
H A Dplatform_config.h1 /* SPDX-License-Identifier: BSD-2-Clause */
40 #error "Pager not supported yet"
/optee_os/core/kernel/
H A Dthread.c1 // SPDX-License-Identifier: BSD-2-Clause
3 * Copyright (c) 2016-2022, Linaro Limited
5 * Copyright (c) 2020-2021, Arm Limited
64 #define GET_STACK_BOTTOM(stack, n) ((vaddr_t)&(stack)[n] + sizeof(stack[n]) - \
77 ((vaddr_t)&stack_thread[n] + sizeof(stack_thread[n]) - \
87 * each locally enable the pager (the mmu). Hence kept in pager sections.
104 return end_va - l + STACK_CANARY_SIZE; in stack_end_va_to_top_hard()
120 return (uint32_t *)(stack_end_va_to_top_hard(stack_size, end_va) - in stack_end_va_to_start_canary()
127 return (uint32_t *)(end_va + STACK_CANARY_SIZE / 2 - sizeof(uint32_t)); in stack_end_va_to_end_canary()
335 int ct = l->curr_thread; in get_stackcheck_recursion_flag()
[all …]
/optee_os/lib/libutils/ext/
H A Dmempool.c1 // SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2018-2019, Linaro Limited
29 * - the total size (in bytes) of the pool
30 * - the offset of the last item allocated in the pool (struct
31 * mempool_item). This offset is -1 is nothing is allocated yet.
34 * - the size of the item
35 * - the offsets, in the pool, of the previous and next items
40 * - the heap is never used.
41 * - there is no assumption on the size of the allocated memory buffers. Only
43 * - a constant time allocation and free as there is no list scan
[all …]
/optee_os/.github/workflows/
H A Dci.yml6 group: ci-${{ github.ref }} # unique per branch
7 cancel-in-progress: true # cancel previous runs on the same branch
11 runs-on: ubuntu-latest
14 - name: Checkout
17 fetch-depth: 0 # full history so checkpatch can check commit IDs in commit messages
18 - name: Update Git config
19 run: git config --globa
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/optee_os/core/include/drivers/
H A Dstpmic1.h1 /* SPDX-License-Identifier: BSD-3-Clause */
3 * Copyright (c) 2016-2018, STMicroelectronics - All Rights Reserved
195 * without needing pager support.
198 * low power and unpaged sequences: boot-on (bo) configuration and

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