1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (C) 2017 Timesys Corporation. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef PLATFORM_CONFIG_H 30 #define PLATFORM_CONFIG_H 31 32 #include <mm/generic_ram_layout.h> 33 #if defined(PLATFORM_FLAVOR_sama7g54_ek) 34 #include <sama7g5.h> 35 #else 36 #include <sama5d2.h> 37 #endif 38 39 #define STACK_ALIGNMENT 64 40 41 #ifdef CFG_WITH_PAGER 42 #error "Pager not supported for platform sama5d2" 43 #endif 44 #ifdef CFG_WITH_LPAE 45 #error "LPAE not supported" 46 #endif 47 48 #if defined(PLATFORM_FLAVOR_sama7g54_ek) 49 #define CONSOLE_UART_BASE (FLEXCOM3_BASE_ADDRESS + 0x200) 50 #define SFR_BASE SFR_BASE_ADDRESS 51 #define AT91C_BASE_TC0 TC0_BASE_ADDRESS 52 #define AT91C_ID_TC0 ID_TC0_CHANNEL0 53 #define AT91C_ID_TC1 ID_TC1_CHANNEL0 54 #define AT91C_ID_SYS ID_RSTC 55 #define AT91C_ID_PIOA ID_PIOA 56 #define AT91C_ID_PIOB ID_PIOB 57 #define AT91C_ID_PIOC ID_PIOC 58 #define AT91C_ID_PIOD ID_PIOD 59 #define AT91C_ID_WDT ID_DWDT_SW 60 #define AT91C_ID_TRNG ID_TRNG 61 #define AT91C_ID_SECUMOD ID_SECUMOD 62 #define AT91C_ID_SFR ID_SFR 63 #define AT91C_ID_SFRBU ID_SFRBU 64 #else 65 #if defined(PLATFORM_FLAVOR_sama5d27_wlsom1_ek) 66 #define CONSOLE_UART_BASE AT91C_BASE_UART0 67 #else 68 #define CONSOLE_UART_BASE AT91C_BASE_UART1 69 #endif 70 71 #define PL310_BASE (AT91C_BASE_L2CC) 72 #define SFR_BASE (AT91C_BASE_SFR) 73 #endif 74 75 /* 76 * PL310 Auxiliary Control Register 77 * 78 * I/Dcache prefetch enabled (bit29:28=2b11) 79 * NS can access interrupts (bit27=1) 80 * NS can lockdown cache lines (bit26=1) 81 * Round robin replacement policy (bit25=1) 82 * Force write allocated (default) 83 * Treats shared accesses (bit22=0, bit13=0) 84 * Parity disabled (bit21=0) 85 * Event monitor disabled (bit20=0) 86 * Platform flavor specific way config: 87 * - 16kb way size (bit19:17=3b001) 88 * Store buffer device limitation disabled (bit11=0) 89 * Cacheable accesses have high prio (bit10=0) 90 */ 91 #define PL310_AUX_CTRL_INIT 0x3E020000 92 93 /* 94 * PL310 Prefetch Control Register 95 * 96 * Double linefill enabled (bit30=1) 97 * I/D prefetch enabled (bit29:28=2b11) 98 * Prefetch drop enabled (bit24=1) 99 * Incr double linefill enable (bit23=1) 100 * Prefetch offset = 1 (bit4:0) 101 */ 102 #define PL310_PREFETCH_CTRL_INIT 0x71800001 103 104 /* 105 * PL310 Power Register 106 * 107 * Dynamic clock gating enabled 108 * Standby mode enabled 109 */ 110 #define PL310_POWER_CTRL_INIT 0x00000003 111 112 #endif /*PLATFORM_CONFIG_H*/ 113