| #
4a0e0f39 |
| 11-Sep-2023 |
Tony Han <tony.han@microchip.com> |
plat-sam: add the header file for sama7g5
Include <sama7g5.h> in platform_config.h and add definitions to adapt names already used by sama5d2.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked
plat-sam: add the header file for sama7g5
Include <sama7g5.h> in platform_config.h and add definitions to adapt names already used by sama5d2.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| #
a4186cf5 |
| 06-Jan-2023 |
Clément Léger <clement.leger@bootlin.com> |
plat-sam: add support for sama5d27-wlsom1-ek board
Add support for PLATFORM_FLAVOR=sama5d27_wlsom1_ek and use the correct debug console (UART0) for that platform.
Signed-off-by: Clément Léger <clem
plat-sam: add support for sama5d27-wlsom1-ek board
Add support for PLATFORM_FLAVOR=sama5d27_wlsom1_ek and use the correct debug console (UART0) for that platform.
Signed-off-by: Clément Léger <clement.leger@bootlin.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| #
d9070df1 |
| 30-Jul-2021 |
Clément Léger <clement.leger@bootlin.com> |
plat-sam: include sama5d2.h file necessary for some values
Defines that are in platform_config.h uses values from sama5d2.h file. Include it to avoid dependency problems.
Acked-by: Etienne Carriere
plat-sam: include sama5d2.h file necessary for some values
Defines that are in platform_config.h uses values from sama5d2.h file. Include it to avoid dependency problems.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| #
3a0a0b24 |
| 07-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
plat-sam: move pl310 related code to its own file
Cleanup main.c by moving pl310 code to sam_pl310.c file.
Signed-off-by: Clément Léger <clement.leger@bootlin.com> Acked-by: Jerome Forissier <jerom
plat-sam: move pl310 related code to its own file
Cleanup main.c by moving pl310 code to sam_pl310.c file.
Signed-off-by: Clément Léger <clement.leger@bootlin.com> Acked-by: Jerome Forissier <jerome@forissier.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| #
7acb65cf |
| 03-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
plat-sam: switch to generic_ram_layout.h
Remove existing defines from platform_config.h to use generic ram layout instead.
Signed-off-by: Clément Léger <clement.leger@bootlin.com> Acked-by: Jerome
plat-sam: switch to generic_ram_layout.h
Remove existing defines from platform_config.h to use generic ram layout instead.
Signed-off-by: Clément Léger <clement.leger@bootlin.com> Acked-by: Jerome Forissier <jerome@forissier.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| #
a5e82dc7 |
| 11-Feb-2019 |
Jerome Forissier <jerome.forissier@linaro.org> |
core_mmu: do not restrict device memory mapping to PGDIR_SIZE granularity
Device memory registered via register_phys_mem() is currently rounded up/down to CORE_MMU_PGDIR_SIZE (1 MiB, or 2 MiB for LP
core_mmu: do not restrict device memory mapping to PGDIR_SIZE granularity
Device memory registered via register_phys_mem() is currently rounded up/down to CORE_MMU_PGDIR_SIZE (1 MiB, or 2 MiB for LPAE). This is not needed and possibly incorrect for SoCs that define I/O memory maps with regions aligned on a small page (4 KiB), because using a larger granularity could result in overlaps between secure and non-secure mappings. This could cause issues depending on the type of memory firewall used by the SoC and its configuration. In any case, memory types other than MEM_AREA_IO_{SEC,NSEC} *can* be mapped with small page granularity using register_phys_mem(), so the situation is a bit inconsistent.
This commit removes the rounding by default and provides a new macro: register_phys_mem_pgdir(). Platforms that still need to use PGDIR_SIZE granularity (typically because it consumes less page table space) need to replace register_phys_mem() by register_phys_mem_pgdir().
In order to avoid any functional change in platform code, all calls to register_phys_mem() with device memory are replaced with register_phys_mem_pgdir(). In addition, CORE_MMU_DEVICE_SIZE is removed and replaced with CORE_MMU_PGDIR_SIZE since there is no unique mapping size for device memory anymore.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reported-by: Zeng Tao <prime.zeng@hisilicon.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| #
29e7629e |
| 03-May-2018 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: move CFG_TEE_CORE_NB_CORE to conf.mk for various platforms
Update platforms d02, rcar, sam, hikey, mediatek, poplar, rpi3, sprd, zynqmp and marvell.
These platforms no more defines CFG_ confi
core: move CFG_TEE_CORE_NB_CORE to conf.mk for various platforms
Update platforms d02, rcar, sam, hikey, mediatek, poplar, rpi3, sprd, zynqmp and marvell.
These platforms no more defines CFG_ configuration directives as NB_CORE was the last remaining one.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Joakim Bech <joakim.bech@linaro.org>
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| #
f6bbec8e |
| 24-Apr-2018 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: remove CFG_ prefix from CFG_TEE_LOAD_ADDR
TEE_LOAD_ADDR is now local to source files. It is set to CFG_TEE_LOAD_ADDR value if defined only for the platforms that previously allowed build to ov
core: remove CFG_ prefix from CFG_TEE_LOAD_ADDR
TEE_LOAD_ADDR is now local to source files. It is set to CFG_TEE_LOAD_ADDR value if defined only for the platforms that previously allowed build to override the value. Few platform did hardcod CFG_TEE_LOAD_ADDR, this change preserve these configurations.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| #
6f4e40ab |
| 25-Apr-2018 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: remove CFG_ prefix from CFG_SHMEM_START/_SIZE
Almost platform currently define these directives from within the source code, through platform_config.h. These values do not need to be configura
core: remove CFG_ prefix from CFG_SHMEM_START/_SIZE
Almost platform currently define these directives from within the source code, through platform_config.h. These values do not need to be configuration directive with the CFG_ prefix.
This change renames the CFG_SHMEM_xxx into TEE_SHMEM_xxx so that they do not mess with the platform configuration directives. Yet, the old CFG_SHMEM_START/SIZE directives can still be used by platform_config.h to set TEE_SHMEM_START/SIZE if the platform supports it (i.e plat-stm).
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| #
247bea90 |
| 25-Apr-2018 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: remove CFG_ prefix from TA_RAM_START/TA_RAM_SIZE
Almost platform currently define these directives from within the source code, through platform_config.h. These values do not need to be config
core: remove CFG_ prefix from TA_RAM_START/TA_RAM_SIZE
Almost platform currently define these directives from within the source code, through platform_config.h. These values do not need to be configuration directive with the CFG_ prefix.
This change renames these macros so that they do not mess with the platform configuration directives.
Old macro label New macro label CFG_TA_RAM_START TA_RAM_START CFG_TA_RAM_SIZE TA_RAM_SIZE
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| #
446cc62a |
| 25-Apr-2018 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: remove CFG_ prefix from TEE_RAM_START/VA_SIZE/PH_SIZE
Almost platform currently define these directives from within the source code, through platform_config.h. These values do not need to be c
core: remove CFG_ prefix from TEE_RAM_START/VA_SIZE/PH_SIZE
Almost platform currently define these directives from within the source code, through platform_config.h. These values do not need to be configuration directive with the CFG_ prefix.
This change renames these macros so that they do not mess with the platform configuration directives.
Old macro label New macro label CFG_TEE_RAM_START TEE_RAM_START CFG_TEE_RAM_VA_SIZE TEE_RAM_VA_SIZE CFG_TEE_RAM_PH_SIZE TEE_RAM_PH_SIZE
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| #
1bb92983 |
| 15-Dec-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
Add SPDX license identifiers
Adds one SPDX-License-Identifier line [1] to each source files that contains license text.
Generated by [2]: spdxify.py --add-spdx optee_os/
The scancode tool [3] wa
Add SPDX license identifiers
Adds one SPDX-License-Identifier line [1] to each source files that contains license text.
Generated by [2]: spdxify.py --add-spdx optee_os/
The scancode tool [3] was used to double check the license matching code in the Python script. All the licenses detected by scancode are either detected by spdxify.py, or have no SPDX identifier, or are false matches.
Link: [1] https://spdx.org/licenses/ Link: [2] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py Link: [3] https://github.com/nexB/scancode-toolkit Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Joakim Bech <joakim.bech@linaro.org>
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| #
e20d1bce |
| 15-May-2017 |
Akshay Bhat <akshay.bhat@timesys.com> |
plat-sam: Add support for Atmel-Microchip SAMA5D2-XULT board
Add basic support to get op-tee to run on SAMA5D2-XULT board.
The SoC is based on single core ARM Cortex-A5 and supports: ARM TrustZone
plat-sam: Add support for Atmel-Microchip SAMA5D2-XULT board
Add basic support to get op-tee to run on SAMA5D2-XULT board.
The SoC is based on single core ARM Cortex-A5 and supports: ARM TrustZone with support for configuring memory/peripherals as secure Secure RTC Secure boot On-the-fly encryption/decryption of DDR bus Tamper protection
Link: http://www.atmel.com/Images/Atmel-11267-32-bit-Cortex-A5-Microcontroller-SAMA5D2_Datasheet.pdf Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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