| /rk3399_ARM-atf/lib/el3_runtime/aarch64/ |
| H A D | context_mgmt.c | 124 el3_state_t *state; in setup_secure_context() local
165 el3_state_t *state; in setup_realm_context() local
236 el3_state_t *state; in setup_ns_context() local
409 el3_state_t *state; in setup_context_common() local
2061 el3_state_t *state; in cm_set_elr_el3() local
2079 el3_state_t *state; in cm_set_elr_spsr_el3() local
2100 el3_state_t *state; in cm_write_scr_el3_bit() local
2130 const el3_state_t *state; in cm_get_scr_el3() local
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| /rk3399_ARM-atf/plat/imx/imx8qm/ |
| H A D | imx8qm_psci.c | 22 #define CORE_PWR_STATE(state) \ argument
24 #define CLUSTER_PWR_STATE(state) \ argument
26 #define SYSTEM_PWR_STATE(state) \ argument
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| /rk3399_ARM-atf/plat/hisilicon/hikey/ |
| H A D | hikey_pm.c | 23 #define CORE_PWR_STATE(state) \ argument
25 #define CLUSTER_PWR_STATE(state) \ argument
27 #define SYSTEM_PWR_STATE(state) \ argument
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| /rk3399_ARM-atf/plat/imx/imx93/ |
| H A D | imx93_psci.c | 19 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0]) argument
20 #define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1]) argument
21 #define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) argument
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| /rk3399_ARM-atf/plat/mediatek/mt8183/ |
| H A D | plat_pm.c | 81 #define MTK_CORE_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL0] argument
82 #define MTK_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL1] argument
83 #define MTK_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) ? \ argument
326 static void plat_mtk_power_domain_off(const psci_power_state_t *state) in plat_mtk_power_domain_off()
345 static void plat_mtk_power_domain_on_finish(const psci_power_state_t *state) in plat_mtk_power_domain_on_finish()
361 static void plat_mtk_power_domain_suspend(const psci_power_state_t *state) in plat_mtk_power_domain_suspend()
402 static void plat_mtk_power_domain_suspend_finish(const psci_power_state_t *state) in plat_mtk_power_domain_suspend_finish()
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| /rk3399_ARM-atf/plat/ti/k3/common/ |
| H A D | k3_psci.c | 20 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0]) argument
21 #define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1]) argument
22 #define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) argument
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| /rk3399_ARM-atf/plat/allwinner/common/ |
| H A D | sunxi_scpi_pm.c | 43 #define CPU_PWR_STATE(state) \ argument
45 #define CLUSTER_PWR_STATE(state) \ argument
47 #define SYSTEM_PWR_STATE(state) \ argument
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| /rk3399_ARM-atf/lib/extensions/fgt/ |
| H A D | fgt2.c | 15 el3_state_t *state; in fgt2_enable() local
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| /rk3399_ARM-atf/lib/extensions/brbe/ |
| H A D | brbe.c | 14 el3_state_t *state = get_el3state_ctx(ctx); in brbe_enable() local
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| /rk3399_ARM-atf/lib/extensions/debug/ |
| H A D | debugv8p9.c | 14 el3_state_t *state = get_el3state_ctx(ctx); in debugv8p9_extended_bp_wp_enable() local
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| /rk3399_ARM-atf/plat/brcm/board/stingray/src/ |
| H A D | brcm_pm_ops.c | 29 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0]) argument
30 #define CLUSTER_PWR_STATE(state) \ argument
32 #define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL2]) argument
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| /rk3399_ARM-atf/plat/hisilicon/hikey960/ |
| H A D | hikey960_pm.c | 26 #define CORE_PWR_STATE(state) \ argument
28 #define CLUSTER_PWR_STATE(state) \ argument
30 #define SYSTEM_PWR_STATE(state) \ argument
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| /rk3399_ARM-atf/plat/nxp/common/psci/ |
| H A D | plat_psci.c | 169 static void _pwr_suspend(const psci_power_state_t *state) in _pwr_suspend()
241 static void _pwr_suspend_finish(const psci_power_state_t *state) in _pwr_suspend_finish()
339 psci_power_state_t *state) in _pwr_state_validate()
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| /rk3399_ARM-atf/drivers/io/ |
| H A D | io_fip.c | 169 fip_dev_state_t *state; in free_dev_info() local
194 fip_dev_state_t *state; in fip_dev_open() local
223 fip_dev_state_t *state; in fip_dev_init() local
472 fip_dev_state_t *state; in fip_dev_get_plat_toc_flag() local
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| /rk3399_ARM-atf/services/spd/opteed/ |
| H A D | opteed_private.h | 27 #define get_optee_pstate(state) (((state) >> OPTEE_PSTATE_SHIFT) & \ argument
29 #define clr_optee_pstate(state) (state &= ~(OPTEE_PSTATE_MASK \ argument
129 uint32_t state; member
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| /rk3399_ARM-atf/lib/extensions/trf/aarch64/ |
| H A D | trf.c | 14 el3_state_t *state = get_el3state_ctx(ctx); in trf_enable() local
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| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/mce/ |
| H A D | ari.c | 137 int32_t ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time) in ari_enter_cstate()
218 uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state) in ari_read_cstate_stats()
241 int32_t ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats) in ari_write_cstate_stats()
277 int32_t ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) in ari_is_ccx_allowed()
298 int32_t ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) in ari_is_sc7_allowed()
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| /rk3399_ARM-atf/plat/imx/imx8ulp/ |
| H A D | imx8ulp_psci.c | 33 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0]) argument
34 #define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1]) argument
35 #define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) argument
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| /rk3399_ARM-atf/plat/st/stm32mp1/ |
| H A D | stm32mp1_shared_resources.c | 82 static const char __unused *shres2str_state(unsigned int state) in shres2str_state()
137 static void register_periph(enum stm32mp_shres id, unsigned int state) in register_periph()
235 static void register_periph_iomem(uintptr_t base, unsigned int state) in register_periph_iomem()
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| /rk3399_ARM-atf/plat/qti/msm8916/ |
| H A D | msm8916_pm.c | 35 #define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1]) argument
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| /rk3399_ARM-atf/lib/extensions/pmuv3/aarch64/ |
| H A D | pmuv3.c | 48 el3_state_t *state = get_el3state_ctx(ctx); in pmuv3_enable() local
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| /rk3399_ARM-atf/drivers/arm/sfcp/sfcp_core/ |
| H A D | sfcp_encryption_stub.c | 37 enum sfcp_trusted_subnet_state_t *state) in sfcp_trusted_subnet_get_state()
47 enum sfcp_trusted_subnet_state_t state) in sfcp_trusted_subnet_set_state()
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| H A D | sfcp_random.c | 14 uint64_t state[2]; member
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| /rk3399_ARM-atf/plat/rockchip/common/ |
| H A D | plat_pm.c | 21 #define RK_CORE_PWR_STATE(state) \ argument
23 #define RK_CLUSTER_PWR_STATE(state) \ argument
25 #define RK_SYSTEM_PWR_STATE(state) \ argument
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| /rk3399_ARM-atf/plat/socionext/synquacer/include/ |
| H A D | platform_def.h | 24 #define SQ_CORE_PWR_STATE(state) (state)->pwr_domain_state[SQ_PWR_LVL0] argument
25 #define SQ_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[SQ_PWR_LVL1] argument
26 #define SQ_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > SQ_PWR_LVL1) ?\ argument
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