Home
last modified time | relevance | path

Searched defs:n (Results 1 – 25 of 399) sorted by relevance

12345678910>>...16

/rk3399_rockchip-uboot/include/linux/
H A Dlog2.h27 int __ilog2_u32(u32 n) in __ilog2_u32()
35 int __ilog2_u64(u64 n) in __ilog2_u64()
50 bool is_power_of_2(unsigned long n) in is_power_of_2()
60 unsigned long __roundup_pow_of_two(unsigned long n) in __roundup_pow_of_two()
70 unsigned long __rounddown_pow_of_two(unsigned long n) in __rounddown_pow_of_two()
85 #define ilog2(n) \ argument
165 #define roundup_pow_of_two(n) \ argument
182 #define rounddown_pow_of_two(n) \ argument
190 int __order_base_2(unsigned long n) in __order_base_2()
208 #define order_base_2(n) \ argument
H A Dioport.h139 #define request_region(start,n,name) __request_region(&ioport_resource, (start), (n), (name), 0) argument
140 #define __request_mem_region(start,n,name, excl) __request_region(&iomem_resource, (start), (n), (n… argument
141 #define request_mem_region(start,n,name) __request_region(&iomem_resource, (start), (n), (name), 0) argument
142 #define request_mem_region_exclusive(start,n,name) \ argument
152 #define release_region(start,n) __release_region(&ioport_resource, (start), (n)) argument
153 #define check_mem_region(start,n) __check_region(&iomem_resource, (start), (n)) argument
154 #define release_mem_region(start,n) __release_region(&iomem_resource, (start), (n)) argument
161 resource_size_t n) in check_region()
168 #define devm_request_region(dev,start,n,name) \ argument
170 #define devm_request_mem_region(dev,start,n,name) \ argument
[all …]
H A Dbuild_bug.h7 #define __BUILD_BUG_ON_NOT_POWER_OF_2(n) (0) argument
8 #define BUILD_BUG_ON_NOT_POWER_OF_2(n) (0) argument
18 #define __BUILD_BUG_ON_NOT_POWER_OF_2(n) \ argument
20 #define BUILD_BUG_ON_NOT_POWER_OF_2(n) \ argument
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/
H A Dp2wi.h25 #define __P2WI_CC_CLK(n) (((n) & 0xff) << 0) argument
27 #define __P2WI_CC_CLK_DIV(n) (((n) >> 1) - 1) argument
28 #define P2WI_CC_CLK_DIV(n) \ argument
30 #define P2WI_CC_SDA_OUT_DELAY(n) (((n) & 0x7) << 8) argument
40 #define __P2WI_STAT_TRANS_ERR(n) (((n) & 0xff) << 8) argument
67 #define P2WI_DATADDR_BYTE_1(n) (((n) & 0xff) << 0) argument
69 #define P2WI_DATADDR_BYTE_2(n) (((n) & 0xff) << 8) argument
71 #define P2WI_DATADDR_BYTE_3(n) (((n) & 0xff) << 16) argument
73 #define P2WI_DATADDR_BYTE_4(n) (((n) & 0xff) << 24) argument
75 #define P2WI_DATADDR_BYTE_5(n) (((n) & 0xff) << 0) argument
[all …]
H A Dprcm.h16 #define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4) argument
18 #define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1) argument
19 #define PRCM_CPUS_CFG_PRE_DIV(n) \ argument
21 #define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8) argument
23 #define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1) argument
24 #define PRCM_CPUS_CFG_POST_DIV(n) \ argument
26 #define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16) argument
41 #define __PRCM_APB0_RATIO(n) (((n) & 0x3) << 0) argument
43 #define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1) argument
44 #define PRCM_APB0_RATIO_DIV(n) \ argument
[all …]
H A Ddram_sun4i.h108 #define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1) argument
112 #define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3) argument
120 #define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6) argument
125 #define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10) argument
128 #define DRAM_DCR_MODE(n) (((n) & 0x3) << 13) argument
137 #define DRAM_DRR_TRFC(n) ((n) & 0xff) argument
138 #define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8) argument
139 #define DRAM_DRR_BURST(n) ((((n) - 1) & 0xf) << 24) argument
141 #define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0) argument
143 #define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2) argument
[all …]
H A Dlcdc.h79 #define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) argument
81 #define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0) argument
83 #define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0) argument
84 #define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16) argument
85 #define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0) argument
86 #define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16) argument
92 #define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26) argument
95 #define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) argument
98 #define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0) argument
99 #define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16) argument
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-lpc32xx/
H A Dtimer.h29 #define TIMER_IR_CR(n) (1 << ((n) + 4)) argument
30 #define TIMER_IR_MR(n) (1 << (n)) argument
38 #define TIMER_MCR_STOP(n) (1 << (3 * (n) + 2)) argument
39 #define TIMER_MCR_RESET(n) (1 << (3 * (n) + 1)) argument
40 #define TIMER_MCR_INTERRUPT(n) (1 << (3 * (n))) argument
43 #define TIMER_CCR_INTERRUPT(n) (1 << (3 * (n) + 2)) argument
44 #define TIMER_CCR_FALLING_EDGE(n) (1 << (3 * (n) + 1)) argument
45 #define TIMER_CCR_RISING_EDGE(n) (1 << (3 * (n))) argument
48 #define TIMER_EMR_EMC_TOGGLE(n) (0x3 << (2 * (n) + 4)) argument
49 #define TIMER_EMR_EMC_SET(n) (0x2 << (2 * (n) + 4)) argument
[all …]
H A Duart.h56 #define HSUART_CTRL_HSU_OFFSET(n) ((n) << 9) argument
91 #define UART_CLKMODE_STATX(n) (1 << ((n) + 16)) argument
93 #define UART_CLKMODE_MASK(n) (0x3 << (2 * (n) - 2)) argument
94 #define UART_CLKMODE_AUTO(n) (0x2 << (2 * (n) - 2)) argument
95 #define UART_CLKMODE_ON(n) (0x1 << (2 * (n) - 2)) argument
96 #define UART_CLKMODE_OFF(n) (0x0 << (2 * (n) - 2)) argument
99 #define UART_LOOPBACK(n) (1 << ((n) - 1)) argument
/rk3399_rockchip-uboot/drivers/phy/
H A Dphy-rockchip-typec.c42 #define TX_TXCC_MGNFS_MULT_000(n) ((0x4050 | ((n) << 9)) << 2) argument
43 #define XCVR_DIAG_PLLDRC_CTRL(n) ((0x40e0 | ((n) << 9)) << 2) argument
44 #define XCVR_DIAG_BIDI_CTRL(n) ((0x40e8 | ((n) << 9)) << 2) argument
45 #define XCVR_DIAG_LANE_FCM_EN_MGN(n) ((0x40f2 | ((n) << 9)) << 2) argument
46 #define TX_PSC_A0(n) ((0x4100 | ((n) << 9)) << 2) argument
47 #define TX_PSC_A1(n) ((0x4101 | ((n) << 9)) << 2) argument
48 #define TX_PSC_A2(n) ((0x4102 | ((n) << 9)) << 2) argument
49 #define TX_PSC_A3(n) ((0x4103 | ((n) << 9)) << 2) argument
50 #define TX_RCVDET_CTRL(n) ((0x4120 | ((n) << 9)) << 2) argument
51 #define TX_RCVDET_EN_TMR(n) ((0x4122 | ((n) << 9)) << 2) argument
[all …]
/rk3399_rockchip-uboot/drivers/gpio/
H A Dmxs_gpio.c18 #define PINCTRL_DOUT(n) (0x0500 + ((n) * 0x10)) argument
19 #define PINCTRL_DIN(n) (0x0600 + ((n) * 0x10)) argument
20 #define PINCTRL_DOE(n) (0x0700 + ((n) * 0x10)) argument
21 #define PINCTRL_PIN2IRQ(n) (0x0800 + ((n) * 0x10)) argument
22 #define PINCTRL_IRQEN(n) (0x0900 + ((n) * 0x10)) argument
23 #define PINCTRL_IRQSTAT(n) (0x0c00 + ((n) * 0x10)) argument
26 #define PINCTRL_DOUT(n) (0x0700 + ((n) * 0x10)) argument
27 #define PINCTRL_DIN(n) (0x0900 + ((n) * 0x10)) argument
28 #define PINCTRL_DOE(n) (0x0b00 + ((n) * 0x10)) argument
29 #define PINCTRL_PIN2IRQ(n) (0x1000 + ((n) * 0x10)) argument
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_common.h30 #define UART_INFO_ID(n) (((n) >> 28) & 0xf) argument
31 #define UART_INFO_IOMUX(n) (((n) >> 24) & 0xf) argument
32 #define UART_INFO_BAUD(n) ((n) & 0xffffff) argument
35 #define STANDBY_IDLE(n) ((n) & 0xffff) argument
37 #define SR_INFO(n) (((n) >> 16) & 0xffff) argument
38 #define PD_INFO(n) ((n) & 0xffff) argument
40 #define FIRST_SCAN_CH(n) (((n) >> 28) & 0xf) argument
41 #define CHANNEL_MASK(n) (((n) >> 24) & 0xf) argument
42 #define STRIDE_TYPE(n) (((n) >> 16) & 0xff) argument
44 #define DDR_2T_INFO(n) ((n) & 1) argument
[all …]
H A Dsdram_px30.h19 #define PMUGRF_OS_REG(n) (PMUGRF_OS_REG0 + (n) * 4) argument
22 #define DDR_GRF_CON(n) (0 + (n) * 4) argument
24 #define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) argument
42 #define PB(n) ((0x1 << (15 + 16)) | ((n) << 15)) argument
43 #define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12)) argument
44 #define FBDIV(n) ((0xFFF << 16) | (n)) argument
47 #define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15)) argument
48 #define RST(n) ((0x1 << (14 + 16)) | ((n) << 14)) argument
49 #define PD(n) ((0x1 << (13 + 16)) | ((n) << 13)) argument
50 #define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12)) argument
[all …]
H A Dsdram_rk3328.h34 #define DDR_GRF_CON(n) (0 + (n) * 4) argument
36 #define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) argument
39 #define ddrphy_psrstn_req(n) (((0x1 << 15) << 16) | ((n) << 15)) argument
40 #define ddrphy_srstn_req(n) (((0x1 << 14) << 16) | ((n) << 14)) argument
41 #define ddrctrl_psrstn_req(n) (((0x1 << 13) << 16) | ((n) << 13)) argument
42 #define ddrctrl_srstn_req(n) (((0x1 << 12) << 16) | ((n) << 12)) argument
43 #define ddrmsch_srstn_req(n) (((0x1 << 11) << 16) | ((n) << 11)) argument
44 #define msch_srstn_req(n) (((0x1 << 9) << 16) | ((n) << 9)) argument
45 #define dfimon_srstn_req(n) (((0x1 << 8) << 16) | ((n) << 8)) argument
46 #define grf_ddr_srstn_req(n) (((0x1 << 7) << 16) | ((n) << 7)) argument
[all …]
/rk3399_rockchip-uboot/drivers/usb/dwc3/
H A Dgadget.h31 #define DWC3_DEPCFG_INT_NUM(n) ((n) << 0) argument
37 #define DWC3_DEPCFG_BINTERVAL_M1(n) ((n) << 16) argument
39 #define DWC3_DEPCFG_EP_NUMBER(n) ((n) << 25) argument
44 #define DWC3_DEPCFG_EP_TYPE(n) ((n) << 1) argument
45 #define DWC3_DEPCFG_MAX_PACKET_SIZE(n) ((n) << 3) argument
46 #define DWC3_DEPCFG_FIFO_NUMBER(n) ((n) << 17) argument
47 #define DWC3_DEPCFG_BURST_SIZE(n) ((n) << 22) argument
48 #define DWC3_DEPCFG_DATA_SEQ_NUM(n) ((n) << 26) argument
57 #define DWC3_DEPXFERCFG_NUM_XFER_RES(n) ((n) & 0xffff) argument
H A Dcore.h102 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) argument
103 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) argument
105 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) argument
107 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) argument
109 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) argument
110 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) argument
112 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) argument
113 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) argument
114 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) argument
115 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) argument
[all …]
/rk3399_rockchip-uboot/cmd/
H A Dblk_common.c69 ulong n; in blk_common_cmd() local
84 ulong n; in blk_common_cmd() local
98 ulong n; in blk_common_cmd() local
111 ulong n; in blk_common_cmd() local
/rk3399_rockchip-uboot/arch/arm/mach-snapdragon/
H A Dclock-apq8016.c32 #define SDCC_BCR(n) ((n * 0x1000) + 0x41000) argument
34 #define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004) argument
36 #define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008) argument
38 #define SDCC_M(n) ((n * 0x1000) + 0x4100C) argument
40 #define SDCC_N(n) ((n * 0x1000) + 0x41010) argument
42 #define SDCC_D(n) ((n * 0x1000) + 0x41014) argument
44 #define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018) argument
45 #define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C) argument
123 int div, int m, int n, int source) in clk_rcg_set_rate_mnd()
/rk3399_rockchip-uboot/include/
H A Ddiv64.h28 # define do_div(n,base) ({ \ argument
54 #define __div64_const32(n, ___b) \ argument
160 static inline uint64_t __arch_xprod_64(const uint64_t m, uint64_t n, bool bias) in __arch_xprod_64()
204 # define do_div(n,base) ({ \ argument
H A Dfsl_ifc.h73 #define IFC_AMASK(n) (IFC_AMASK_MASK << \ argument
115 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) argument
139 #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) argument
168 #define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) argument
176 #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) argument
180 #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) argument
199 #define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT) argument
201 #define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT) argument
203 #define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT) argument
205 #define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT) argument
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/ti-common/
H A Ddavinci_nand.h77 #define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2)) argument
79 #define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4) argument
80 #define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2))) argument
88 #define DAVINCI_ABCR_WSETUP(n) (n << 26) argument
89 #define DAVINCI_ABCR_WSTROBE(n) (n << 20) argument
90 #define DAVINCI_ABCR_WHOLD(n) (n << 17) argument
91 #define DAVINCI_ABCR_RSETUP(n) (n << 13) argument
92 #define DAVINCI_ABCR_RSTROBE(n) (n << 7) argument
93 #define DAVINCI_ABCR_RHOLD(n) (n << 4) argument
94 #define DAVINCI_ABCR_TA(n) (n << 2) argument
/rk3399_rockchip-uboot/include/power/
H A Das3722.h14 #define AS3722_SD_VOLTAGE(n) (0x00 + (n)) argument
15 #define AS3722_LDO_VOLTAGE(n) (0x10 + (n)) argument
21 #define AS3722_GPIO_CONTROL(n) (0x08 + (n)) argument
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-meson/
H A Dgxbb.h18 #define _GXBB_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n)) argument
19 #define GXBB_GPIO_EN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0) argument
20 #define GXBB_GPIO_IN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1) argument
21 #define GXBB_GPIO_OUT(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2) argument
/rk3399_rockchip-uboot/fs/ubifs/
H A Dtnc.c181 struct ubifs_old_idx *old_idx, *n; in destroy_old_idx() local
215 const int n = zn->child_cnt; in copy_znode() local
585 struct ubifs_znode *znode, int n) in get_znode()
606 static int tnc_next(struct ubifs_info *c, struct ubifs_znode **zn, int *n) in tnc_next()
651 static int tnc_prev(struct ubifs_info *c, struct ubifs_znode **zn, int *n) in tnc_prev()
704 struct ubifs_znode **zn, int *n, in resolve_collision()
893 struct ubifs_znode **zn, int *n, in fallible_resolve_collision()
1037 struct ubifs_znode **zn, int *n, in resolve_collision_directly()
1111 int n; in dirty_cow_bottom_up() local
1172 struct ubifs_znode **zn, int *n) in ubifs_lookup_level0()
[all …]
/rk3399_rockchip-uboot/lib/avb/libavb/
H A Davb_sysdeps_posix.c39 int avb_memcmp(const void* src1, const void* src2, size_t n) { in avb_memcmp()
43 void* avb_memcpy(void* dest, const void* src, size_t n) { in avb_memcpy()
47 void* avb_memset(void* dest, const int c, size_t n) { in avb_memset()
55 int avb_strncmp(const char* s1, const char* s2, size_t n) { in avb_strncmp()

12345678910>>...16