1*bfcef28aSBeniamino Galvani /* 2*bfcef28aSBeniamino Galvani * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com> 3*bfcef28aSBeniamino Galvani * 4*bfcef28aSBeniamino Galvani * SPDX-License-Identifier: GPL-2.0+ 5*bfcef28aSBeniamino Galvani */ 6*bfcef28aSBeniamino Galvani 7*bfcef28aSBeniamino Galvani #ifndef __GXBB_H__ 8*bfcef28aSBeniamino Galvani #define __GXBB_H__ 9*bfcef28aSBeniamino Galvani 10*bfcef28aSBeniamino Galvani #define GXBB_PERIPHS_BASE 0xc8834400 11*bfcef28aSBeniamino Galvani #define GXBB_HIU_BASE 0xc883c000 12*bfcef28aSBeniamino Galvani #define GXBB_ETH_BASE 0xc9410000 13*bfcef28aSBeniamino Galvani 14*bfcef28aSBeniamino Galvani /* Peripherals registers */ 15*bfcef28aSBeniamino Galvani #define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2)) 16*bfcef28aSBeniamino Galvani 17*bfcef28aSBeniamino Galvani /* GPIO registers 0 to 6 */ 18*bfcef28aSBeniamino Galvani #define _GXBB_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n)) 19*bfcef28aSBeniamino Galvani #define GXBB_GPIO_EN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0) 20*bfcef28aSBeniamino Galvani #define GXBB_GPIO_IN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1) 21*bfcef28aSBeniamino Galvani #define GXBB_GPIO_OUT(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2) 22*bfcef28aSBeniamino Galvani 23*bfcef28aSBeniamino Galvani #define GXBB_ETH_REG_0 GXBB_PERIPHS_ADDR(0x50) 24*bfcef28aSBeniamino Galvani #define GXBB_ETH_REG_1 GXBB_PERIPHS_ADDR(0x51) 25*bfcef28aSBeniamino Galvani 26*bfcef28aSBeniamino Galvani #define GXBB_ETH_REG_0_PHY_INTF BIT(0) 27*bfcef28aSBeniamino Galvani #define GXBB_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) 28*bfcef28aSBeniamino Galvani #define GXBB_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) 29*bfcef28aSBeniamino Galvani #define GXBB_ETH_REG_0_PHY_CLK_EN BIT(10) 30*bfcef28aSBeniamino Galvani #define GXBB_ETH_REG_0_CLK_EN BIT(12) 31*bfcef28aSBeniamino Galvani 32*bfcef28aSBeniamino Galvani /* HIU registers */ 33*bfcef28aSBeniamino Galvani #define GXBB_HIU_ADDR(off) (GXBB_HIU_BASE + ((off) << 2)) 34*bfcef28aSBeniamino Galvani 35*bfcef28aSBeniamino Galvani #define GXBB_MEM_PD_REG_0 GXBB_HIU_ADDR(0x40) 36*bfcef28aSBeniamino Galvani 37*bfcef28aSBeniamino Galvani /* Ethernet memory power domain */ 38*bfcef28aSBeniamino Galvani #define GXBB_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) 39*bfcef28aSBeniamino Galvani 40*bfcef28aSBeniamino Galvani /* Clock gates */ 41*bfcef28aSBeniamino Galvani #define GXBB_GCLK_MPEG_0 GXBB_HIU_ADDR(0x50) 42*bfcef28aSBeniamino Galvani #define GXBB_GCLK_MPEG_1 GXBB_HIU_ADDR(0x51) 43*bfcef28aSBeniamino Galvani #define GXBB_GCLK_MPEG_2 GXBB_HIU_ADDR(0x52) 44*bfcef28aSBeniamino Galvani #define GXBB_GCLK_MPEG_OTHER GXBB_HIU_ADDR(0x53) 45*bfcef28aSBeniamino Galvani #define GXBB_GCLK_MPEG_AO GXBB_HIU_ADDR(0x54) 46*bfcef28aSBeniamino Galvani 47*bfcef28aSBeniamino Galvani #define GXBB_GCLK_MPEG_1_ETH BIT(3) 48*bfcef28aSBeniamino Galvani 49*bfcef28aSBeniamino Galvani #endif /* __GXBB_H__ */ 50