| /rk3399_rockchip-uboot/arch/arm/mach-socfpga/ |
| H A D | clock_manager_arria10.c | 837 unsigned int clk_src, divisor, nocclk, src_hz; in cm_get_noc_clk_hz() local
912 u32 clk_src, mainmpuclk_reg; in cm_get_mpu_clk_hz() local
953 u32 clk_src = 0; in cm_get_per_vco_clk_hz() local
996 u32 clk_src = readl(&clock_manager_base->main_pll.vco0); in cm_get_main_vco_clk_hz() local
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| /rk3399_rockchip-uboot/board/freescale/s32v234evb/ |
| H A D | clock.c | 20 u32 clk_src; in select_pll_source_clk() local
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| /rk3399_rockchip-uboot/drivers/spi/ |
| H A D | mxc_spi.c | 96 u32 clk_src; in spi_cfg_mxc() local
133 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); in spi_cfg_mxc() local
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| /rk3399_rockchip-uboot/drivers/mmc/ |
| H A D | meson_gx_mmc.c | 36 unsigned int clk, clk_src, clk_div; in meson_mmc_config_clock() local
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| /rk3399_rockchip-uboot/drivers/phy/marvell/ |
| H A D | comphy.h | 88 bool clk_src; member
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| H A D | comphy_cp110.c | 87 static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src, in comphy_pcie_power_up()
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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3588.c | 1387 u32 reg, clk_src, uart_src, div; in rk3588_uart_set_rate() local
1497 u32 clk_src, div; in rk3588_pciephy_set_rate() local
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| H A D | clk_rk3576.c | 1704 u32 reg, clk_src, p_rate; in rk3576_uart_frac_set_rate() local
1839 u32 reg, clk_src = 0, div = 0; in rk3576_uart_set_rate() local
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| H A D | clk_px30.c | 429 u32 clk_src = GPLL_HZ / 2; in px30_i2s_get_clk() local
455 u32 clk_src; in px30_i2s_set_clk() local
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| H A D | clk_rv1106.c | 862 u32 reg, clk_src, uart_src, div; in rv1106_uart_set_rate() local
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| H A D | clk_rk3568.c | 2283 u32 reg, clk_src, uart_src, div; in rk3568_uart_set_rate() local
2429 u32 reg, con, clk_src, i2s_src, div; in rk3568_i2s3_set_rate() local
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| H A D | clk_rk3562.c | 525 u32 reg, clk_src, uart_src, div; in rk3562_uart_set_rate() local
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| /rk3399_rockchip-uboot/arch/arm/mach-imx/mx5/ |
| H A D | clock.c | 797 u32 clk_src; in config_ddr_clk() local
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