1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * 4 * (C) Copyright 2010 5 * Petr Stetiar <ynezz@true.cz> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 * 9 * Contains stolen code from ddcprobe project which is: 10 * Copyright (C) Nalin Dahyabhai <bigfun@pobox.com> 11 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 12 */ 13 14 #include <common.h> 15 #include <compiler.h> 16 #include <div64.h> 17 #include <drm_modes.h> 18 #include <edid.h> 19 #include <errno.h> 20 #include <fdtdec.h> 21 #include <hexdump.h> 22 #include <malloc.h> 23 #include <linux/compat.h> 24 #include <linux/ctype.h> 25 #include <linux/fb.h> 26 #include <linux/hdmi.h> 27 #include <linux/string.h> 28 29 #define EDID_EST_TIMINGS 16 30 #define EDID_STD_TIMINGS 8 31 #define EDID_DETAILED_TIMINGS 4 32 #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) 33 #define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) & (BITS_PER_LONG - 1))) 34 #define BITMAP_LAST_WORD_MASK(nbits) (~0UL >> (-(nbits) & (BITS_PER_LONG - 1))) 35 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 36 #define version_greater(edid, maj, min) \ 37 (((edid)->version > (maj)) || \ 38 ((edid)->version == (maj) && (edid)->revision > (min))) 39 40 /* 41 * EDID blocks out in the wild have a variety of bugs, try to collect 42 * them here (note that userspace may work around broken monitors first, 43 * but fixes should make their way here so that the kernel "just works" 44 * on as many displays as possible). 45 */ 46 47 /* First detailed mode wrong, use largest 60Hz mode */ 48 #define EDID_QUIRK_PREFER_LARGE_60 BIT(0) 49 /* Reported 135MHz pixel clock is too high, needs adjustment */ 50 #define EDID_QUIRK_135_CLOCK_TOO_HIGH BIT(1) 51 /* Prefer the largest mode at 75 Hz */ 52 #define EDID_QUIRK_PREFER_LARGE_75 BIT(2) 53 /* Detail timing is in cm not mm */ 54 #define EDID_QUIRK_DETAILED_IN_CM BIT(3) 55 /* Detailed timing descriptors have bogus size values, so just take the 56 * maximum size and use that. 57 */ 58 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE BIT(4) 59 /* Monitor forgot to set the first detailed is preferred bit. */ 60 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED BIT(5) 61 /* use +hsync +vsync for detailed mode */ 62 #define EDID_QUIRK_DETAILED_SYNC_PP BIT(6) 63 /* Force reduced-blanking timings for detailed modes */ 64 #define EDID_QUIRK_FORCE_REDUCED_BLANKING BIT(7) 65 /* Force 8bpc */ 66 #define EDID_QUIRK_FORCE_8BPC BIT(8) 67 /* Force 12bpc */ 68 #define EDID_QUIRK_FORCE_12BPC BIT(9) 69 /* Force 6bpc */ 70 #define EDID_QUIRK_FORCE_6BPC BIT(10) 71 /* Force 10bpc */ 72 #define EDID_QUIRK_FORCE_10BPC BIT(11) 73 74 struct detailed_mode_closure { 75 struct edid *edid; 76 struct hdmi_edid_data *data; 77 bool preferred; 78 u32 quirks; 79 int modes; 80 }; 81 82 #define LEVEL_DMT 0 83 #define LEVEL_GTF 1 84 #define LEVEL_GTF2 2 85 #define LEVEL_CVT 3 86 87 static struct edid_quirk { 88 char vendor[4]; 89 int product_id; 90 u32 quirks; 91 } edid_quirk_list[] = { 92 /* Acer AL1706 */ 93 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 94 /* Acer F51 */ 95 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 96 /* Unknown Acer */ 97 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 98 99 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 100 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 101 102 /* Belinea 10 15 55 */ 103 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 104 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 105 106 /* Envision Peripherals, Inc. EN-7100e */ 107 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 108 /* Envision EN2028 */ 109 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 110 111 /* Funai Electronics PM36B */ 112 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 113 EDID_QUIRK_DETAILED_IN_CM }, 114 115 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 116 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 117 118 /* LG Philips LCD LP154W01-A5 */ 119 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 120 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 121 122 /* Philips 107p5 CRT */ 123 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 124 125 /* Proview AY765C */ 126 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 127 128 /* Samsung SyncMaster 205BW. Note: irony */ 129 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 130 /* Samsung SyncMaster 22[5-6]BW */ 131 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 132 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 133 134 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 135 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 136 137 /* ViewSonic VA2026w */ 138 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 139 140 /* Medion MD 30217 PG */ 141 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 142 143 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 144 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 145 146 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 147 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 148 }; 149 150 /* 151 * Probably taken from CEA-861 spec. 152 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 153 * 154 * Index using the VIC. 155 */ 156 static const struct drm_display_mode edid_cea_modes[] = { 157 /* 0 - dummy, VICs start at 1 */ 158 { }, 159 /* 1 - 640x480@60Hz */ 160 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 161 752, 800, 480, 490, 492, 525, 0, 162 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 163 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 164 /* 2 - 720x480@60Hz */ 165 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 166 798, 858, 480, 489, 495, 525, 0, 167 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 168 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 169 /* 3 - 720x480@60Hz */ 170 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 171 798, 858, 480, 489, 495, 525, 0, 172 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 173 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 174 /* 4 - 1280x720@60Hz */ 175 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 176 1430, 1650, 720, 725, 730, 750, 0, 177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 178 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 179 /* 5 - 1920x1080i@60Hz */ 180 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 181 2052, 2200, 1080, 1084, 1094, 1125, 0, 182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 183 DRM_MODE_FLAG_INTERLACE), 184 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 185 /* 6 - 720(1440)x480i@60Hz */ 186 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 187 801, 858, 480, 488, 494, 525, 0, 188 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 189 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 190 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 191 /* 7 - 720(1440)x480i@60Hz */ 192 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 193 801, 858, 480, 488, 494, 525, 0, 194 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 195 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 196 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 197 /* 8 - 720(1440)x240@60Hz */ 198 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 199 801, 858, 240, 244, 247, 262, 0, 200 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 201 DRM_MODE_FLAG_DBLCLK), 202 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 203 /* 9 - 720(1440)x240@60Hz */ 204 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 205 801, 858, 240, 244, 247, 262, 0, 206 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 207 DRM_MODE_FLAG_DBLCLK), 208 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 209 /* 10 - 2880x480i@60Hz */ 210 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 211 3204, 3432, 480, 488, 494, 525, 0, 212 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 213 DRM_MODE_FLAG_INTERLACE), 214 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 215 /* 11 - 2880x480i@60Hz */ 216 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 217 3204, 3432, 480, 488, 494, 525, 0, 218 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 219 DRM_MODE_FLAG_INTERLACE), 220 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 221 /* 12 - 2880x240@60Hz */ 222 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 223 3204, 3432, 240, 244, 247, 262, 0, 224 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 225 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 226 /* 13 - 2880x240@60Hz */ 227 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 228 3204, 3432, 240, 244, 247, 262, 0, 229 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 230 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 231 /* 14 - 1440x480@60Hz */ 232 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 233 1596, 1716, 480, 489, 495, 525, 0, 234 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 235 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 236 /* 15 - 1440x480@60Hz */ 237 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 238 1596, 1716, 480, 489, 495, 525, 0, 239 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 240 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 241 /* 16 - 1920x1080@60Hz */ 242 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 243 2052, 2200, 1080, 1084, 1089, 1125, 0, 244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 245 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 246 /* 17 - 720x576@50Hz */ 247 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 248 796, 864, 576, 581, 586, 625, 0, 249 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 250 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 251 /* 18 - 720x576@50Hz */ 252 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 253 796, 864, 576, 581, 586, 625, 0, 254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 255 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 256 /* 19 - 1280x720@50Hz */ 257 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 258 1760, 1980, 720, 725, 730, 750, 0, 259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 260 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 261 /* 20 - 1920x1080i@50Hz */ 262 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 263 2492, 2640, 1080, 1084, 1094, 1125, 0, 264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 265 DRM_MODE_FLAG_INTERLACE), 266 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 267 /* 21 - 720(1440)x576i@50Hz */ 268 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 269 795, 864, 576, 580, 586, 625, 0, 270 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 271 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 272 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 273 /* 22 - 720(1440)x576i@50Hz */ 274 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 275 795, 864, 576, 580, 586, 625, 0, 276 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 277 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 278 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 279 /* 23 - 720(1440)x288@50Hz */ 280 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 281 795, 864, 288, 290, 293, 312, 0, 282 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 283 DRM_MODE_FLAG_DBLCLK), 284 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 285 /* 24 - 720(1440)x288@50Hz */ 286 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 287 795, 864, 288, 290, 293, 312, 0, 288 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 289 DRM_MODE_FLAG_DBLCLK), 290 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 291 /* 25 - 2880x576i@50Hz */ 292 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 293 3180, 3456, 576, 580, 586, 625, 0, 294 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 295 DRM_MODE_FLAG_INTERLACE), 296 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 297 /* 26 - 2880x576i@50Hz */ 298 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 299 3180, 3456, 576, 580, 586, 625, 0, 300 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 301 DRM_MODE_FLAG_INTERLACE), 302 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 303 /* 27 - 2880x288@50Hz */ 304 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 305 3180, 3456, 288, 290, 293, 312, 0, 306 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 307 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 308 /* 28 - 2880x288@50Hz */ 309 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 310 3180, 3456, 288, 290, 293, 312, 0, 311 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 312 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 313 /* 29 - 1440x576@50Hz */ 314 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 315 1592, 1728, 576, 581, 586, 625, 0, 316 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 317 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 318 /* 30 - 1440x576@50Hz */ 319 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 320 1592, 1728, 576, 581, 586, 625, 0, 321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 322 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 323 /* 31 - 1920x1080@50Hz */ 324 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 325 2492, 2640, 1080, 1084, 1089, 1125, 0, 326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 327 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 328 /* 32 - 1920x1080@24Hz */ 329 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 330 2602, 2750, 1080, 1084, 1089, 1125, 0, 331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 332 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 333 /* 33 - 1920x1080@25Hz */ 334 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 335 2492, 2640, 1080, 1084, 1089, 1125, 0, 336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 337 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 338 /* 34 - 1920x1080@30Hz */ 339 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 340 2052, 2200, 1080, 1084, 1089, 1125, 0, 341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 342 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 343 /* 35 - 2880x480@60Hz */ 344 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 345 3192, 3432, 480, 489, 495, 525, 0, 346 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 347 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 348 /* 36 - 2880x480@60Hz */ 349 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 350 3192, 3432, 480, 489, 495, 525, 0, 351 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 352 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 353 /* 37 - 2880x576@50Hz */ 354 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 355 3184, 3456, 576, 581, 586, 625, 0, 356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 357 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 358 /* 38 - 2880x576@50Hz */ 359 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 360 3184, 3456, 576, 581, 586, 625, 0, 361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 362 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 363 /* 39 - 1920x1080i@50Hz */ 364 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 365 2120, 2304, 1080, 1126, 1136, 1250, 0, 366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 367 DRM_MODE_FLAG_INTERLACE), 368 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 369 /* 40 - 1920x1080i@100Hz */ 370 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 371 2492, 2640, 1080, 1084, 1094, 1125, 0, 372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 373 DRM_MODE_FLAG_INTERLACE), 374 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 375 /* 41 - 1280x720@100Hz */ 376 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 377 1760, 1980, 720, 725, 730, 750, 0, 378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 379 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 380 /* 42 - 720x576@100Hz */ 381 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 382 796, 864, 576, 581, 586, 625, 0, 383 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 384 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 385 /* 43 - 720x576@100Hz */ 386 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 387 796, 864, 576, 581, 586, 625, 0, 388 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 389 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 390 /* 44 - 720(1440)x576i@100Hz */ 391 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 392 795, 864, 576, 580, 586, 625, 0, 393 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 394 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 395 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 396 /* 45 - 720(1440)x576i@100Hz */ 397 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 398 795, 864, 576, 580, 586, 625, 0, 399 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 400 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 401 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 402 /* 46 - 1920x1080i@120Hz */ 403 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 404 2052, 2200, 1080, 1084, 1094, 1125, 0, 405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 406 DRM_MODE_FLAG_INTERLACE), 407 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 408 /* 47 - 1280x720@120Hz */ 409 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 410 1430, 1650, 720, 725, 730, 750, 0, 411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 412 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 413 /* 48 - 720x480@120Hz */ 414 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 415 798, 858, 480, 489, 495, 525, 0, 416 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 417 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 418 /* 49 - 720x480@120Hz */ 419 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 420 798, 858, 480, 489, 495, 525, 0, 421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 422 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 423 /* 50 - 720(1440)x480i@120Hz */ 424 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 425 801, 858, 480, 488, 494, 525, 0, 426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 427 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 428 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 429 /* 51 - 720(1440)x480i@120Hz */ 430 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 431 801, 858, 480, 488, 494, 525, 0, 432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 433 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 434 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 435 /* 52 - 720x576@200Hz */ 436 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 437 796, 864, 576, 581, 586, 625, 0, 438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 439 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 440 /* 53 - 720x576@200Hz */ 441 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 442 796, 864, 576, 581, 586, 625, 0, 443 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 444 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 445 /* 54 - 720(1440)x576i@200Hz */ 446 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 447 795, 864, 576, 580, 586, 625, 0, 448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 449 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 450 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 451 /* 55 - 720(1440)x576i@200Hz */ 452 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 453 795, 864, 576, 580, 586, 625, 0, 454 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 455 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 456 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 457 /* 56 - 720x480@240Hz */ 458 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 459 798, 858, 480, 489, 495, 525, 0, 460 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 461 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 462 /* 57 - 720x480@240Hz */ 463 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 464 798, 858, 480, 489, 495, 525, 0, 465 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 466 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 467 /* 58 - 720(1440)x480i@240 */ 468 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 469 801, 858, 480, 488, 494, 525, 0, 470 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 471 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 472 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 473 /* 59 - 720(1440)x480i@240 */ 474 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 475 801, 858, 480, 488, 494, 525, 0, 476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 477 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 478 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 479 /* 60 - 1280x720@24Hz */ 480 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 481 3080, 3300, 720, 725, 730, 750, 0, 482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 483 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 484 /* 61 - 1280x720@25Hz */ 485 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 486 3740, 3960, 720, 725, 730, 750, 0, 487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 488 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 489 /* 62 - 1280x720@30Hz */ 490 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 491 3080, 3300, 720, 725, 730, 750, 0, 492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 493 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 494 /* 63 - 1920x1080@120Hz */ 495 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 496 2052, 2200, 1080, 1084, 1089, 1125, 0, 497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 498 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 499 /* 64 - 1920x1080@100Hz */ 500 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 501 2492, 2640, 1080, 1084, 1089, 1125, 0, 502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 503 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 504 /* 65 - 1280x720@24Hz */ 505 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 506 3080, 3300, 720, 725, 730, 750, 0, 507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 508 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 509 /* 66 - 1280x720@25Hz */ 510 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 511 3740, 3960, 720, 725, 730, 750, 0, 512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 513 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 514 /* 67 - 1280x720@30Hz */ 515 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 516 3080, 3300, 720, 725, 730, 750, 0, 517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 518 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 519 /* 68 - 1280x720@50Hz */ 520 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 521 1760, 1980, 720, 725, 730, 750, 0, 522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 523 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 524 /* 69 - 1280x720@60Hz */ 525 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 526 1430, 1650, 720, 725, 730, 750, 0, 527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 528 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 529 /* 70 - 1280x720@100Hz */ 530 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 531 1760, 1980, 720, 725, 730, 750, 0, 532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 533 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 534 /* 71 - 1280x720@120Hz */ 535 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 536 1430, 1650, 720, 725, 730, 750, 0, 537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 538 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 539 /* 72 - 1920x1080@24Hz */ 540 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 541 2602, 2750, 1080, 1084, 1089, 1125, 0, 542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 543 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 544 /* 73 - 1920x1080@25Hz */ 545 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 546 2492, 2640, 1080, 1084, 1089, 1125, 0, 547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 548 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 549 /* 74 - 1920x1080@30Hz */ 550 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 551 2052, 2200, 1080, 1084, 1089, 1125, 0, 552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 553 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 554 /* 75 - 1920x1080@50Hz */ 555 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 556 2492, 2640, 1080, 1084, 1089, 1125, 0, 557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 558 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 559 /* 76 - 1920x1080@60Hz */ 560 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 561 2052, 2200, 1080, 1084, 1089, 1125, 0, 562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 563 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 564 /* 77 - 1920x1080@100Hz */ 565 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 566 2492, 2640, 1080, 1084, 1089, 1125, 0, 567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 568 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 569 /* 78 - 1920x1080@120Hz */ 570 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 571 2052, 2200, 1080, 1084, 1089, 1125, 0, 572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 573 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 574 /* 79 - 1680x720@24Hz */ 575 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 576 3080, 3300, 720, 725, 730, 750, 0, 577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 578 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 579 /* 80 - 1680x720@25Hz */ 580 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 581 2948, 3168, 720, 725, 730, 750, 0, 582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 583 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 584 /* 81 - 1680x720@30Hz */ 585 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 586 2420, 2640, 720, 725, 730, 750, 0, 587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 588 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 589 /* 82 - 1680x720@50Hz */ 590 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 591 1980, 2200, 720, 725, 730, 750, 0, 592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 593 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 594 /* 83 - 1680x720@60Hz */ 595 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 596 1980, 2200, 720, 725, 730, 750, 0, 597 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 598 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 599 /* 84 - 1680x720@100Hz */ 600 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 601 1780, 2000, 720, 725, 730, 825, 0, 602 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 603 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 604 /* 85 - 1680x720@120Hz */ 605 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 606 1780, 2000, 720, 725, 730, 825, 0, 607 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 608 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 609 /* 86 - 2560x1080@24Hz */ 610 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 611 3602, 3750, 1080, 1084, 1089, 1100, 0, 612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 613 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 614 /* 87 - 2560x1080@25Hz */ 615 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 616 3052, 3200, 1080, 1084, 1089, 1125, 0, 617 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 618 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 619 /* 88 - 2560x1080@30Hz */ 620 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 621 3372, 3520, 1080, 1084, 1089, 1125, 0, 622 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 623 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 624 /* 89 - 2560x1080@50Hz */ 625 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 626 3152, 3300, 1080, 1084, 1089, 1125, 0, 627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 628 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 629 /* 90 - 2560x1080@60Hz */ 630 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 631 2852, 3000, 1080, 1084, 1089, 1100, 0, 632 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 633 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 634 /* 91 - 2560x1080@100Hz */ 635 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 636 2822, 2970, 1080, 1084, 1089, 1250, 0, 637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 638 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 639 /* 92 - 2560x1080@120Hz */ 640 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 641 3152, 3300, 1080, 1084, 1089, 1250, 0, 642 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 643 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 644 /* 93 - 3840x2160p@24Hz 16:9 */ 645 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 646 5204, 5500, 2160, 2168, 2178, 2250, 0, 647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 648 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 649 /* 94 - 3840x2160p@25Hz 16:9 */ 650 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 651 4984, 5280, 2160, 2168, 2178, 2250, 0, 652 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 653 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 654 /* 95 - 3840x2160p@30Hz 16:9 */ 655 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 656 4104, 4400, 2160, 2168, 2178, 2250, 0, 657 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 658 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 659 /* 96 - 3840x2160p@50Hz 16:9 */ 660 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 661 4984, 5280, 2160, 2168, 2178, 2250, 0, 662 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 663 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 664 /* 97 - 3840x2160p@60Hz 16:9 */ 665 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 666 4104, 4400, 2160, 2168, 2178, 2250, 0, 667 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 668 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 669 /* 98 - 4096x2160p@24Hz 256:135 */ 670 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 671 5204, 5500, 2160, 2168, 2178, 2250, 0, 672 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 673 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 674 /* 99 - 4096x2160p@25Hz 256:135 */ 675 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 676 5152, 5280, 2160, 2168, 2178, 2250, 0, 677 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 678 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 679 /* 100 - 4096x2160p@30Hz 256:135 */ 680 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 681 4272, 4400, 2160, 2168, 2178, 2250, 0, 682 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 683 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 684 /* 101 - 4096x2160p@50Hz 256:135 */ 685 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 686 5152, 5280, 2160, 2168, 2178, 2250, 0, 687 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 688 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 689 /* 102 - 4096x2160p@60Hz 256:135 */ 690 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 691 4272, 4400, 2160, 2168, 2178, 2250, 0, 692 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 693 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 694 /* 103 - 3840x2160p@24Hz 64:27 */ 695 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 696 5204, 5500, 2160, 2168, 2178, 2250, 0, 697 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 698 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 699 /* 104 - 3840x2160p@25Hz 64:27 */ 700 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 701 4104, 4400, 2160, 2168, 2178, 2250, 0, 702 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 703 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 704 /* 105 - 3840x2160p@30Hz 64:27 */ 705 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 706 4104, 4400, 2160, 2168, 2178, 2250, 0, 707 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 708 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 709 /* 106 - 3840x2160p@50Hz 64:27 */ 710 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 711 4984, 5280, 2160, 2168, 2178, 2250, 0, 712 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 713 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 714 /* 107 - 3840x2160p@60Hz 64:27 */ 715 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 716 4104, 4400, 2160, 2168, 2178, 2250, 0, 717 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 718 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 719 }; 720 721 /* 722 * HDMI 1.4 4k modes. Index using the VIC. 723 */ 724 static const struct drm_display_mode edid_4k_modes[] = { 725 /* 0 - dummy, VICs start at 1 */ 726 { }, 727 /* 1 - 3840x2160@30Hz */ 728 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 729 3840, 4016, 4104, 4400, 730 2160, 2168, 2178, 2250, 0, 731 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 732 .vrefresh = 30, }, 733 /* 2 - 3840x2160@25Hz */ 734 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 735 3840, 4896, 4984, 5280, 736 2160, 2168, 2178, 2250, 0, 737 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 738 .vrefresh = 25, }, 739 /* 3 - 3840x2160@24Hz */ 740 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 741 3840, 5116, 5204, 5500, 742 2160, 2168, 2178, 2250, 0, 743 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 744 .vrefresh = 24, }, 745 /* 4 - 4096x2160@24Hz (SMPTE) */ 746 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 747 4096, 5116, 5204, 5500, 748 2160, 2168, 2178, 2250, 0, 749 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 750 .vrefresh = 24, }, 751 }; 752 753 /* 754 * Autogenerated from the DMT spec. 755 * This table is copied from xfree86/modes/xf86EdidModes.c. 756 */ 757 static const struct drm_display_mode drm_dmt_modes[] = { 758 /* 0x01 - 640x350@85Hz */ 759 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 760 736, 832, 350, 382, 385, 445, 0, 761 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 762 /* 0x02 - 640x400@85Hz */ 763 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 764 736, 832, 400, 401, 404, 445, 0, 765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 766 /* 0x03 - 720x400@85Hz */ 767 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 768 828, 936, 400, 401, 404, 446, 0, 769 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 770 /* 0x04 - 640x480@60Hz */ 771 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 772 752, 800, 480, 490, 492, 525, 0, 773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 774 /* 0x05 - 640x480@72Hz */ 775 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 776 704, 832, 480, 489, 492, 520, 0, 777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 778 /* 0x06 - 640x480@75Hz */ 779 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 780 720, 840, 480, 481, 484, 500, 0, 781 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 782 /* 0x07 - 640x480@85Hz */ 783 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 784 752, 832, 480, 481, 484, 509, 0, 785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 786 /* 0x08 - 800x600@56Hz */ 787 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 788 896, 1024, 600, 601, 603, 625, 0, 789 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 790 /* 0x09 - 800x600@60Hz */ 791 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 792 968, 1056, 600, 601, 605, 628, 0, 793 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 794 /* 0x0a - 800x600@72Hz */ 795 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 796 976, 1040, 600, 637, 643, 666, 0, 797 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 798 /* 0x0b - 800x600@75Hz */ 799 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 800 896, 1056, 600, 601, 604, 625, 0, 801 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 802 /* 0x0c - 800x600@85Hz */ 803 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 804 896, 1048, 600, 601, 604, 631, 0, 805 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 806 /* 0x0d - 800x600@120Hz RB */ 807 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 808 880, 960, 600, 603, 607, 636, 0, 809 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 810 /* 0x0e - 848x480@60Hz */ 811 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 812 976, 1088, 480, 486, 494, 517, 0, 813 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 814 /* 0x0f - 1024x768@43Hz, interlace */ 815 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 816 1208, 1264, 768, 768, 772, 817, 0, 817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 818 DRM_MODE_FLAG_INTERLACE) }, 819 /* 0x10 - 1024x768@60Hz */ 820 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 821 1184, 1344, 768, 771, 777, 806, 0, 822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 823 /* 0x11 - 1024x768@70Hz */ 824 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 825 1184, 1328, 768, 771, 777, 806, 0, 826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 827 /* 0x12 - 1024x768@75Hz */ 828 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 829 1136, 1312, 768, 769, 772, 800, 0, 830 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 831 /* 0x13 - 1024x768@85Hz */ 832 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 833 1168, 1376, 768, 769, 772, 808, 0, 834 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 835 /* 0x14 - 1024x768@120Hz RB */ 836 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 837 1104, 1184, 768, 771, 775, 813, 0, 838 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 839 /* 0x15 - 1152x864@75Hz */ 840 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 841 1344, 1600, 864, 865, 868, 900, 0, 842 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 843 /* 0x55 - 1280x720@60Hz */ 844 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 845 1430, 1650, 720, 725, 730, 750, 0, 846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 847 /* 0x16 - 1280x768@60Hz RB */ 848 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 849 1360, 1440, 768, 771, 778, 790, 0, 850 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 851 /* 0x17 - 1280x768@60Hz */ 852 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 853 1472, 1664, 768, 771, 778, 798, 0, 854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 855 /* 0x18 - 1280x768@75Hz */ 856 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 857 1488, 1696, 768, 771, 778, 805, 0, 858 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 859 /* 0x19 - 1280x768@85Hz */ 860 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 861 1496, 1712, 768, 771, 778, 809, 0, 862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 863 /* 0x1a - 1280x768@120Hz RB */ 864 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 865 1360, 1440, 768, 771, 778, 813, 0, 866 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 867 /* 0x1b - 1280x800@60Hz RB */ 868 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 869 1360, 1440, 800, 803, 809, 823, 0, 870 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 871 /* 0x1c - 1280x800@60Hz */ 872 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 873 1480, 1680, 800, 803, 809, 831, 0, 874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 875 /* 0x1d - 1280x800@75Hz */ 876 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 877 1488, 1696, 800, 803, 809, 838, 0, 878 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 879 /* 0x1e - 1280x800@85Hz */ 880 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 881 1496, 1712, 800, 803, 809, 843, 0, 882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 883 /* 0x1f - 1280x800@120Hz RB */ 884 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 885 1360, 1440, 800, 803, 809, 847, 0, 886 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 887 /* 0x20 - 1280x960@60Hz */ 888 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 889 1488, 1800, 960, 961, 964, 1000, 0, 890 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 891 /* 0x21 - 1280x960@85Hz */ 892 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 893 1504, 1728, 960, 961, 964, 1011, 0, 894 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 895 /* 0x22 - 1280x960@120Hz RB */ 896 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 897 1360, 1440, 960, 963, 967, 1017, 0, 898 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 899 /* 0x23 - 1280x1024@60Hz */ 900 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 901 1440, 1688, 1024, 1025, 1028, 1066, 0, 902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 903 /* 0x24 - 1280x1024@75Hz */ 904 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 905 1440, 1688, 1024, 1025, 1028, 1066, 0, 906 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 907 /* 0x25 - 1280x1024@85Hz */ 908 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 909 1504, 1728, 1024, 1025, 1028, 1072, 0, 910 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 911 /* 0x26 - 1280x1024@120Hz RB */ 912 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 913 1360, 1440, 1024, 1027, 1034, 1084, 0, 914 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 915 /* 0x27 - 1360x768@60Hz */ 916 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 917 1536, 1792, 768, 771, 777, 795, 0, 918 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 919 /* 0x28 - 1360x768@120Hz RB */ 920 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 921 1440, 1520, 768, 771, 776, 813, 0, 922 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 923 /* 0x51 - 1366x768@60Hz */ 924 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 925 1579, 1792, 768, 771, 774, 798, 0, 926 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 927 /* 0x56 - 1366x768@60Hz */ 928 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 929 1436, 1500, 768, 769, 772, 800, 0, 930 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 931 /* 0x29 - 1400x1050@60Hz RB */ 932 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 933 1480, 1560, 1050, 1053, 1057, 1080, 0, 934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 935 /* 0x2a - 1400x1050@60Hz */ 936 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 937 1632, 1864, 1050, 1053, 1057, 1089, 0, 938 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 939 /* 0x2b - 1400x1050@75Hz */ 940 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 941 1648, 1896, 1050, 1053, 1057, 1099, 0, 942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 943 /* 0x2c - 1400x1050@85Hz */ 944 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 945 1656, 1912, 1050, 1053, 1057, 1105, 0, 946 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 947 /* 0x2d - 1400x1050@120Hz RB */ 948 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 949 1480, 1560, 1050, 1053, 1057, 1112, 0, 950 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 951 /* 0x2e - 1440x900@60Hz RB */ 952 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 953 1520, 1600, 900, 903, 909, 926, 0, 954 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 955 /* 0x2f - 1440x900@60Hz */ 956 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 957 1672, 1904, 900, 903, 909, 934, 0, 958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 959 /* 0x30 - 1440x900@75Hz */ 960 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 961 1688, 1936, 900, 903, 909, 942, 0, 962 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 963 /* 0x31 - 1440x900@85Hz */ 964 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 965 1696, 1952, 900, 903, 909, 948, 0, 966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 967 /* 0x32 - 1440x900@120Hz RB */ 968 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 969 1520, 1600, 900, 903, 909, 953, 0, 970 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 971 /* 0x53 - 1600x900@60Hz */ 972 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 973 1704, 1800, 900, 901, 904, 1000, 0, 974 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 975 /* 0x33 - 1600x1200@60Hz */ 976 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 977 1856, 2160, 1200, 1201, 1204, 1250, 0, 978 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 979 /* 0x34 - 1600x1200@65Hz */ 980 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 981 1856, 2160, 1200, 1201, 1204, 1250, 0, 982 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 983 /* 0x35 - 1600x1200@70Hz */ 984 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 985 1856, 2160, 1200, 1201, 1204, 1250, 0, 986 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 987 /* 0x36 - 1600x1200@75Hz */ 988 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 989 1856, 2160, 1200, 1201, 1204, 1250, 0, 990 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 991 /* 0x37 - 1600x1200@85Hz */ 992 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 993 1856, 2160, 1200, 1201, 1204, 1250, 0, 994 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 995 /* 0x38 - 1600x1200@120Hz RB */ 996 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 997 1680, 1760, 1200, 1203, 1207, 1271, 0, 998 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 999 /* 0x39 - 1680x1050@60Hz RB */ 1000 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 1001 1760, 1840, 1050, 1053, 1059, 1080, 0, 1002 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1003 /* 0x3a - 1680x1050@60Hz */ 1004 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 1005 1960, 2240, 1050, 1053, 1059, 1089, 0, 1006 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1007 /* 0x3b - 1680x1050@75Hz */ 1008 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 1009 1976, 2272, 1050, 1053, 1059, 1099, 0, 1010 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1011 /* 0x3c - 1680x1050@85Hz */ 1012 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 1013 1984, 2288, 1050, 1053, 1059, 1105, 0, 1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1015 /* 0x3d - 1680x1050@120Hz RB */ 1016 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 1017 1760, 1840, 1050, 1053, 1059, 1112, 0, 1018 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1019 /* 0x3e - 1792x1344@60Hz */ 1020 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 1021 2120, 2448, 1344, 1345, 1348, 1394, 0, 1022 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1023 /* 0x3f - 1792x1344@75Hz */ 1024 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 1025 2104, 2456, 1344, 1345, 1348, 1417, 0, 1026 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1027 /* 0x40 - 1792x1344@120Hz RB */ 1028 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 1029 1872, 1952, 1344, 1347, 1351, 1423, 0, 1030 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1031 /* 0x41 - 1856x1392@60Hz */ 1032 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 1033 2176, 2528, 1392, 1393, 1396, 1439, 0, 1034 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1035 /* 0x42 - 1856x1392@75Hz */ 1036 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 1037 2208, 2560, 1392, 1393, 1396, 1500, 0, 1038 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1039 /* 0x43 - 1856x1392@120Hz RB */ 1040 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 1041 1936, 2016, 1392, 1395, 1399, 1474, 0, 1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1043 /* 0x52 - 1920x1080@60Hz */ 1044 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1045 2052, 2200, 1080, 1084, 1089, 1125, 0, 1046 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1047 /* 0x44 - 1920x1200@60Hz RB */ 1048 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 1049 2000, 2080, 1200, 1203, 1209, 1235, 0, 1050 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1051 /* 0x45 - 1920x1200@60Hz */ 1052 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 1053 2256, 2592, 1200, 1203, 1209, 1245, 0, 1054 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1055 /* 0x46 - 1920x1200@75Hz */ 1056 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 1057 2264, 2608, 1200, 1203, 1209, 1255, 0, 1058 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1059 /* 0x47 - 1920x1200@85Hz */ 1060 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 1061 2272, 2624, 1200, 1203, 1209, 1262, 0, 1062 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1063 /* 0x48 - 1920x1200@120Hz RB */ 1064 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 1065 2000, 2080, 1200, 1203, 1209, 1271, 0, 1066 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1067 /* 0x49 - 1920x1440@60Hz */ 1068 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 1069 2256, 2600, 1440, 1441, 1444, 1500, 0, 1070 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1071 /* 0x4a - 1920x1440@75Hz */ 1072 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 1073 2288, 2640, 1440, 1441, 1444, 1500, 0, 1074 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1075 /* 0x4b - 1920x1440@120Hz RB */ 1076 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 1077 2000, 2080, 1440, 1443, 1447, 1525, 0, 1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1079 /* 0x54 - 2048x1152@60Hz */ 1080 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 1081 2154, 2250, 1152, 1153, 1156, 1200, 0, 1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1083 /* 0x4c - 2560x1600@60Hz RB */ 1084 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 1085 2640, 2720, 1600, 1603, 1609, 1646, 0, 1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1087 /* 0x4d - 2560x1600@60Hz */ 1088 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 1089 3032, 3504, 1600, 1603, 1609, 1658, 0, 1090 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1091 /* 0x4e - 2560x1600@75Hz */ 1092 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 1093 3048, 3536, 1600, 1603, 1609, 1672, 0, 1094 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1095 /* 0x4f - 2560x1600@85Hz */ 1096 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 1097 3048, 3536, 1600, 1603, 1609, 1682, 0, 1098 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1099 /* 0x50 - 2560x1600@120Hz RB */ 1100 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 1101 2640, 2720, 1600, 1603, 1609, 1694, 0, 1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1103 /* 0x57 - 4096x2160@60Hz RB */ 1104 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 1105 4136, 4176, 2160, 2208, 2216, 2222, 0, 1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1107 /* 0x58 - 4096x2160@59.94Hz RB */ 1108 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 1109 4136, 4176, 2160, 2208, 2216, 2222, 0, 1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1111 }; 1112 1113 /* 1114 * These more or less come from the DMT spec. The 720x400 modes are 1115 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 1116 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 1117 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 1118 * mode. 1119 * 1120 * The DMT modes have been fact-checked; the rest are mild guesses. 1121 */ 1122 static const struct drm_display_mode edid_est_modes[] = { 1123 /* 800x600@60Hz */ 1124 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 1125 968, 1056, 600, 601, 605, 628, 0, 1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1127 /* 800x600@56Hz */ 1128 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 1129 896, 1024, 600, 601, 603, 625, 0, 1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1131 /* 640x480@75Hz */ 1132 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 1133 720, 840, 480, 481, 484, 500, 0, 1134 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1135 /* 640x480@72Hz */ 1136 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 1137 704, 832, 480, 489, 492, 520, 0, 1138 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1139 /* 640x480@67Hz */ 1140 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 1141 768, 864, 480, 483, 486, 525, 0, 1142 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1143 /* 640x480@60Hz */ 1144 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 1145 752, 800, 480, 490, 492, 525, 0, 1146 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1147 /* 720x400@88Hz */ 1148 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 1149 846, 900, 400, 421, 423, 449, 0, 1150 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1151 /* 720x400@70Hz */ 1152 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 1153 846, 900, 400, 412, 414, 449, 0, 1154 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1155 /* 1280x1024@75Hz */ 1156 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 1157 1440, 1688, 1024, 1025, 1028, 1066, 0, 1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1159 /* 1024x768@75Hz */ 1160 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 1161 1136, 1312, 768, 769, 772, 800, 0, 1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1163 /* 1024x768@70Hz */ 1164 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 1165 1184, 1328, 768, 771, 777, 806, 0, 1166 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1167 /* 1024x768@60Hz */ 1168 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 1169 1184, 1344, 768, 771, 777, 806, 0, 1170 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1171 /* 1024x768@43Hz */ 1172 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 1173 1208, 1264, 768, 768, 776, 817, 0, 1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1175 DRM_MODE_FLAG_INTERLACE) }, 1176 /* 832x624@75Hz */ 1177 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 1178 928, 1152, 624, 625, 628, 667, 0, 1179 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1180 /* 800x600@75Hz */ 1181 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 1182 896, 1056, 600, 601, 604, 625, 0, 1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1184 /* 800x600@72Hz */ 1185 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 1186 976, 1040, 600, 637, 643, 666, 0, 1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1188 /* 1152x864@75Hz */ 1189 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 1190 1344, 1600, 864, 865, 868, 900, 0, 1191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1192 }; 1193 1194 struct minimode { 1195 short w; 1196 short h; 1197 short r; 1198 short rb; 1199 }; 1200 1201 static const struct minimode est3_modes[] = { 1202 /* byte 6 */ 1203 { 640, 350, 85, 0 }, 1204 { 640, 400, 85, 0 }, 1205 { 720, 400, 85, 0 }, 1206 { 640, 480, 85, 0 }, 1207 { 848, 480, 60, 0 }, 1208 { 800, 600, 85, 0 }, 1209 { 1024, 768, 85, 0 }, 1210 { 1152, 864, 75, 0 }, 1211 /* byte 7 */ 1212 { 1280, 768, 60, 1 }, 1213 { 1280, 768, 60, 0 }, 1214 { 1280, 768, 75, 0 }, 1215 { 1280, 768, 85, 0 }, 1216 { 1280, 960, 60, 0 }, 1217 { 1280, 960, 85, 0 }, 1218 { 1280, 1024, 60, 0 }, 1219 { 1280, 1024, 85, 0 }, 1220 /* byte 8 */ 1221 { 1360, 768, 60, 0 }, 1222 { 1440, 900, 60, 1 }, 1223 { 1440, 900, 60, 0 }, 1224 { 1440, 900, 75, 0 }, 1225 { 1440, 900, 85, 0 }, 1226 { 1400, 1050, 60, 1 }, 1227 { 1400, 1050, 60, 0 }, 1228 { 1400, 1050, 75, 0 }, 1229 /* byte 9 */ 1230 { 1400, 1050, 85, 0 }, 1231 { 1680, 1050, 60, 1 }, 1232 { 1680, 1050, 60, 0 }, 1233 { 1680, 1050, 75, 0 }, 1234 { 1680, 1050, 85, 0 }, 1235 { 1600, 1200, 60, 0 }, 1236 { 1600, 1200, 65, 0 }, 1237 { 1600, 1200, 70, 0 }, 1238 /* byte 10 */ 1239 { 1600, 1200, 75, 0 }, 1240 { 1600, 1200, 85, 0 }, 1241 { 1792, 1344, 60, 0 }, 1242 { 1792, 1344, 75, 0 }, 1243 { 1856, 1392, 60, 0 }, 1244 { 1856, 1392, 75, 0 }, 1245 { 1920, 1200, 60, 1 }, 1246 { 1920, 1200, 60, 0 }, 1247 /* byte 11 */ 1248 { 1920, 1200, 75, 0 }, 1249 { 1920, 1200, 85, 0 }, 1250 { 1920, 1440, 60, 0 }, 1251 { 1920, 1440, 75, 0 }, 1252 }; 1253 1254 static const struct minimode extra_modes[] = { 1255 { 1024, 576, 60, 0 }, 1256 { 1366, 768, 60, 0 }, 1257 { 1600, 900, 60, 0 }, 1258 { 1680, 945, 60, 0 }, 1259 { 1920, 1080, 60, 0 }, 1260 { 2048, 1152, 60, 0 }, 1261 { 2048, 1536, 60, 0 }, 1262 }; 1263 1264 int edid_check_info(struct edid1_info *edid_info) 1265 { 1266 if ((edid_info == NULL) || (edid_info->version == 0)) 1267 return -1; 1268 1269 if (memcmp(edid_info->header, "\x0\xff\xff\xff\xff\xff\xff\x0", 8)) 1270 return -1; 1271 1272 if (edid_info->version == 0xff && edid_info->revision == 0xff) 1273 return -1; 1274 1275 return 0; 1276 } 1277 1278 int edid_check_checksum(u8 *edid_block) 1279 { 1280 u8 checksum = 0; 1281 int i; 1282 1283 for (i = 0; i < 128; i++) 1284 checksum += edid_block[i]; 1285 1286 return (checksum == 0) ? 0 : -EINVAL; 1287 } 1288 1289 int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin, 1290 unsigned int *hmax, unsigned int *vmin, 1291 unsigned int *vmax) 1292 { 1293 int i; 1294 struct edid_monitor_descriptor *monitor; 1295 1296 *hmin = *hmax = *vmin = *vmax = 0; 1297 if (edid_check_info(edid)) 1298 return -1; 1299 1300 for (i = 0; i < ARRAY_SIZE(edid->monitor_details.descriptor); i++) { 1301 monitor = &edid->monitor_details.descriptor[i]; 1302 if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) { 1303 *hmin = monitor->data.range_data.horizontal_min; 1304 *hmax = monitor->data.range_data.horizontal_max; 1305 *vmin = monitor->data.range_data.vertical_min; 1306 *vmax = monitor->data.range_data.vertical_max; 1307 return 0; 1308 } 1309 } 1310 return -1; 1311 } 1312 1313 /* Set all parts of a timing entry to the same value */ 1314 static void set_entry(struct timing_entry *entry, u32 value) 1315 { 1316 entry->min = value; 1317 entry->typ = value; 1318 entry->max = value; 1319 } 1320 1321 /** 1322 * decode_timing() - Decoding an 18-byte detailed timing record 1323 * 1324 * @buf: Pointer to EDID detailed timing record 1325 * @timing: Place to put timing 1326 */ 1327 static void decode_timing(u8 *buf, struct display_timing *timing) 1328 { 1329 uint x_mm, y_mm; 1330 unsigned int ha, hbl, hso, hspw, hborder; 1331 unsigned int va, vbl, vso, vspw, vborder; 1332 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1333 1334 /* Edid contains pixel clock in terms of 10KHz */ 1335 set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 10000); 1336 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1337 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1338 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1339 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1340 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1341 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1342 hborder = buf[15]; 1343 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1344 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1345 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1346 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1347 vborder = buf[16]; 1348 1349 set_entry(&timing->hactive, ha); 1350 set_entry(&timing->hfront_porch, hso); 1351 set_entry(&timing->hback_porch, hbl - hso - hspw); 1352 set_entry(&timing->hsync_len, hspw); 1353 1354 set_entry(&timing->vactive, va); 1355 set_entry(&timing->vfront_porch, vso); 1356 set_entry(&timing->vback_porch, vbl - vso - vspw); 1357 set_entry(&timing->vsync_len, vspw); 1358 1359 timing->flags = 0; 1360 if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t)) 1361 timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH; 1362 else 1363 timing->flags |= DISPLAY_FLAGS_HSYNC_LOW; 1364 if (EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t)) 1365 timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH; 1366 else 1367 timing->flags |= DISPLAY_FLAGS_VSYNC_LOW; 1368 1369 if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t)) 1370 timing->flags = DISPLAY_FLAGS_INTERLACED; 1371 1372 debug("Detailed mode clock %u Hz, %d mm x %d mm\n" 1373 " %04x %04x %04x %04x hborder %x\n" 1374 " %04x %04x %04x %04x vborder %x\n", 1375 timing->pixelclock.typ, 1376 x_mm, y_mm, 1377 ha, ha + hso, ha + hso + hspw, 1378 ha + hbl, hborder, 1379 va, va + vso, va + vso + vspw, 1380 va + vbl, vborder); 1381 } 1382 1383 /** 1384 * decode_mode() - Decoding an 18-byte detailed timing record 1385 * 1386 * @buf: Pointer to EDID detailed timing record 1387 * @timing: Place to put timing 1388 */ 1389 static void decode_mode(u8 *buf, struct drm_display_mode *mode) 1390 { 1391 uint x_mm, y_mm; 1392 unsigned int ha, hbl, hso, hspw, hborder; 1393 unsigned int va, vbl, vso, vspw, vborder; 1394 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1395 1396 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1397 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1398 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1399 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1400 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1401 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1402 hborder = buf[15]; 1403 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1404 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1405 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1406 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1407 vborder = buf[16]; 1408 1409 /* Edid contains pixel clock in terms of 10KHz */ 1410 mode->clock = (buf[0] + (buf[1] << 8)) * 10; 1411 mode->hdisplay = ha; 1412 mode->hsync_start = ha + hso; 1413 mode->hsync_end = ha + hso + hspw; 1414 mode->htotal = ha + hbl; 1415 mode->vdisplay = va; 1416 mode->vsync_start = va + vso; 1417 mode->vsync_end = va + vso + vspw; 1418 mode->vtotal = va + vbl; 1419 1420 mode->flags = EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t) ? 1421 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1422 mode->flags |= EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t) ? 1423 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1424 1425 if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t)) 1426 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1427 1428 debug("Detailed mode clock %u kHz, %d mm x %d mm, flags[%x]\n" 1429 " %04d %04d %04d %04d hborder %d\n" 1430 " %04d %04d %04d %04d vborder %d\n", 1431 mode->clock, 1432 x_mm, y_mm, mode->flags, 1433 mode->hdisplay, mode->hsync_start, mode->hsync_end, 1434 mode->htotal, hborder, 1435 mode->vdisplay, mode->vsync_start, mode->vsync_end, 1436 mode->vtotal, vborder); 1437 } 1438 1439 /** 1440 * edid_vendor - match a string against EDID's obfuscated vendor field 1441 * @edid: EDID to match 1442 * @vendor: vendor string 1443 * 1444 * Returns true if @vendor is in @edid, false otherwise 1445 */ 1446 static bool edid_vendor(struct edid *edid, char *vendor) 1447 { 1448 char edid_vendor[3]; 1449 1450 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1451 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1452 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1453 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1454 1455 return !strncmp(edid_vendor, vendor, 3); 1456 } 1457 1458 /** 1459 * Check if HDMI vendor specific data block is present in CEA block 1460 * @param info CEA extension block 1461 * @return true if block is found 1462 */ 1463 static bool cea_is_hdmi_vsdb_present(struct edid_cea861_info *info) 1464 { 1465 u8 end, i = 0; 1466 1467 /* check for end of data block */ 1468 end = info->dtd_offset; 1469 if (end == 0) 1470 end = sizeof(info->data); 1471 if (end < 4 || end > sizeof(info->data)) 1472 return false; 1473 end -= 4; 1474 1475 while (i < end) { 1476 /* Look for vendor specific data block of appropriate size */ 1477 if ((EDID_CEA861_DB_TYPE(*info, i) == EDID_CEA861_DB_VENDOR) && 1478 (EDID_CEA861_DB_LEN(*info, i) >= 5)) { 1479 u8 *db = &info->data[i + 1]; 1480 u32 oui = db[0] | (db[1] << 8) | (db[2] << 16); 1481 1482 if (oui == HDMI_IEEE_OUI) 1483 return true; 1484 } 1485 i += EDID_CEA861_DB_LEN(*info, i) + 1; 1486 } 1487 1488 return false; 1489 } 1490 1491 static int drm_get_vrefresh(const struct drm_display_mode *mode) 1492 { 1493 int refresh = 0; 1494 unsigned int calc_val; 1495 1496 if (mode->vrefresh > 0) { 1497 refresh = mode->vrefresh; 1498 } else if (mode->htotal > 0 && mode->vtotal > 0) { 1499 int vtotal; 1500 1501 vtotal = mode->vtotal; 1502 /* work out vrefresh the value will be x1000 */ 1503 calc_val = (mode->clock * 1000); 1504 calc_val /= mode->htotal; 1505 refresh = (calc_val + vtotal / 2) / vtotal; 1506 1507 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1508 refresh *= 2; 1509 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1510 refresh /= 2; 1511 if (mode->vscan > 1) 1512 refresh /= mode->vscan; 1513 } 1514 return refresh; 1515 } 1516 1517 int edid_get_drm_mode(u8 *buf, int buf_size, struct drm_display_mode *mode, 1518 int *panel_bits_per_colourp) 1519 { 1520 struct edid1_info *edid = (struct edid1_info *)buf; 1521 bool timing_done; 1522 int i; 1523 1524 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 1525 debug("%s: Invalid buffer\n", __func__); 1526 return -EINVAL; 1527 } 1528 1529 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 1530 debug("%s: No preferred timing\n", __func__); 1531 return -ENOENT; 1532 } 1533 1534 /* Look for detailed timing */ 1535 timing_done = false; 1536 for (i = 0; i < 4; i++) { 1537 struct edid_monitor_descriptor *desc; 1538 1539 desc = &edid->monitor_details.descriptor[i]; 1540 if (desc->zero_flag_1 != 0) { 1541 decode_mode((u8 *)desc, mode); 1542 timing_done = true; 1543 break; 1544 } 1545 } 1546 if (!timing_done) 1547 return -EINVAL; 1548 1549 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 1550 debug("%s: Not a digital display\n", __func__); 1551 return -ENOSYS; 1552 } 1553 if (edid->version != 1 || edid->revision < 4) { 1554 debug("%s: EDID version %d.%d does not have required info\n", 1555 __func__, edid->version, edid->revision); 1556 *panel_bits_per_colourp = -1; 1557 } else { 1558 *panel_bits_per_colourp = 1559 ((edid->video_input_definition & 0x70) >> 3) + 4; 1560 } 1561 1562 return 0; 1563 } 1564 1565 int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing, 1566 int *panel_bits_per_colourp) 1567 { 1568 struct edid1_info *edid = (struct edid1_info *)buf; 1569 bool timing_done; 1570 int i; 1571 1572 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 1573 debug("%s: Invalid buffer\n", __func__); 1574 return -EINVAL; 1575 } 1576 1577 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 1578 debug("%s: No preferred timing\n", __func__); 1579 return -ENOENT; 1580 } 1581 1582 /* Look for detailed timing */ 1583 timing_done = false; 1584 for (i = 0; i < 4; i++) { 1585 struct edid_monitor_descriptor *desc; 1586 1587 desc = &edid->monitor_details.descriptor[i]; 1588 if (desc->zero_flag_1 != 0) { 1589 decode_timing((u8 *)desc, timing); 1590 timing_done = true; 1591 break; 1592 } 1593 } 1594 if (!timing_done) 1595 return -EINVAL; 1596 1597 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 1598 debug("%s: Not a digital display\n", __func__); 1599 return -ENOSYS; 1600 } 1601 if (edid->version != 1 || edid->revision < 4) { 1602 debug("%s: EDID version %d.%d does not have required info\n", 1603 __func__, edid->version, edid->revision); 1604 *panel_bits_per_colourp = -1; 1605 } else { 1606 *panel_bits_per_colourp = 1607 ((edid->video_input_definition & 0x70) >> 3) + 4; 1608 } 1609 1610 timing->hdmi_monitor = false; 1611 if (edid->extension_flag && (buf_size >= EDID_EXT_SIZE)) { 1612 struct edid_cea861_info *info = 1613 (struct edid_cea861_info *)(buf + sizeof(*edid)); 1614 1615 if (info->extension_tag == EDID_CEA861_EXTENSION_TAG) 1616 timing->hdmi_monitor = cea_is_hdmi_vsdb_present(info); 1617 } 1618 1619 return 0; 1620 } 1621 1622 /** 1623 * Snip the tailing whitespace/return of a string. 1624 * 1625 * @param string The string to be snipped 1626 * @return the snipped string 1627 */ 1628 static char *snip(char *string) 1629 { 1630 char *s; 1631 1632 /* 1633 * This is always a 13 character buffer 1634 * and it's not always terminated. 1635 */ 1636 string[12] = '\0'; 1637 s = &string[strlen(string) - 1]; 1638 1639 while (s >= string && (isspace(*s) || *s == '\n' || *s == '\r' || 1640 *s == '\0')) 1641 *(s--) = '\0'; 1642 1643 return string; 1644 } 1645 1646 /** 1647 * Print an EDID monitor descriptor block 1648 * 1649 * @param monitor The EDID monitor descriptor block 1650 * @have_timing Modifies to 1 if the desciptor contains timing info 1651 */ 1652 static void edid_print_dtd(struct edid_monitor_descriptor *monitor, 1653 unsigned int *have_timing) 1654 { 1655 unsigned char *bytes = (unsigned char *)monitor; 1656 struct edid_detailed_timing *timing = 1657 (struct edid_detailed_timing *)monitor; 1658 1659 if (bytes[0] == 0 && bytes[1] == 0) { 1660 if (monitor->type == EDID_MONITOR_DESCRIPTOR_SERIAL) 1661 printf("Monitor serial number: %s\n", 1662 snip(monitor->data.string)); 1663 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_ASCII) 1664 printf("Monitor ID: %s\n", 1665 snip(monitor->data.string)); 1666 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_NAME) 1667 printf("Monitor name: %s\n", 1668 snip(monitor->data.string)); 1669 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) 1670 printf("Monitor range limits, horizontal sync: " 1671 "%d-%d kHz, vertical refresh: " 1672 "%d-%d Hz, max pixel clock: " 1673 "%d MHz\n", 1674 monitor->data.range_data.horizontal_min, 1675 monitor->data.range_data.horizontal_max, 1676 monitor->data.range_data.vertical_min, 1677 monitor->data.range_data.vertical_max, 1678 monitor->data.range_data.pixel_clock_max * 10); 1679 } else { 1680 u32 pixclock, h_active, h_blanking, v_active, v_blanking; 1681 u32 h_total, v_total, vfreq; 1682 1683 pixclock = EDID_DETAILED_TIMING_PIXEL_CLOCK(*timing); 1684 h_active = EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(*timing); 1685 h_blanking = EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(*timing); 1686 v_active = EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*timing); 1687 v_blanking = EDID_DETAILED_TIMING_VERTICAL_BLANKING(*timing); 1688 1689 h_total = h_active + h_blanking; 1690 v_total = v_active + v_blanking; 1691 if (v_total > 0 && h_total > 0) 1692 vfreq = pixclock / (v_total * h_total); 1693 else 1694 vfreq = 1; /* Error case */ 1695 printf("\t%dx%d\%c\t%d Hz (detailed)\n", h_active, 1696 v_active, h_active > 1000 ? ' ' : '\t', vfreq); 1697 *have_timing = 1; 1698 } 1699 } 1700 1701 /** 1702 * Get the manufacturer name from an EDID info. 1703 * 1704 * @param edid_info The EDID info to be printed 1705 * @param name Returns the string of the manufacturer name 1706 */ 1707 static void edid_get_manufacturer_name(struct edid1_info *edid, char *name) 1708 { 1709 name[0] = EDID1_INFO_MANUFACTURER_NAME_CHAR1(*edid) + 'A' - 1; 1710 name[1] = EDID1_INFO_MANUFACTURER_NAME_CHAR2(*edid) + 'A' - 1; 1711 name[2] = EDID1_INFO_MANUFACTURER_NAME_CHAR3(*edid) + 'A' - 1; 1712 name[3] = '\0'; 1713 } 1714 1715 void edid_print_info(struct edid1_info *edid_info) 1716 { 1717 int i; 1718 char manufacturer[4]; 1719 unsigned int have_timing = 0; 1720 u32 serial_number; 1721 1722 if (edid_check_info(edid_info)) { 1723 printf("Not a valid EDID\n"); 1724 return; 1725 } 1726 1727 printf("EDID version: %d.%d\n", 1728 edid_info->version, edid_info->revision); 1729 1730 printf("Product ID code: %04x\n", EDID1_INFO_PRODUCT_CODE(*edid_info)); 1731 1732 edid_get_manufacturer_name(edid_info, manufacturer); 1733 printf("Manufacturer: %s\n", manufacturer); 1734 1735 serial_number = EDID1_INFO_SERIAL_NUMBER(*edid_info); 1736 if (serial_number != 0xffffffff) { 1737 if (strcmp(manufacturer, "MAG") == 0) 1738 serial_number -= 0x7000000; 1739 if (strcmp(manufacturer, "OQI") == 0) 1740 serial_number -= 456150000; 1741 if (strcmp(manufacturer, "VSC") == 0) 1742 serial_number -= 640000000; 1743 } 1744 printf("Serial number: %08x\n", serial_number); 1745 printf("Manufactured in week: %d year: %d\n", 1746 edid_info->week, edid_info->year + 1990); 1747 1748 printf("Video input definition: %svoltage level %d%s%s%s%s%s\n", 1749 EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid_info) ? 1750 "digital signal, " : "analog signal, ", 1751 EDID1_INFO_VIDEO_INPUT_VOLTAGE_LEVEL(*edid_info), 1752 EDID1_INFO_VIDEO_INPUT_BLANK_TO_BLACK(*edid_info) ? 1753 ", blank to black" : "", 1754 EDID1_INFO_VIDEO_INPUT_SEPARATE_SYNC(*edid_info) ? 1755 ", separate sync" : "", 1756 EDID1_INFO_VIDEO_INPUT_COMPOSITE_SYNC(*edid_info) ? 1757 ", composite sync" : "", 1758 EDID1_INFO_VIDEO_INPUT_SYNC_ON_GREEN(*edid_info) ? 1759 ", sync on green" : "", 1760 EDID1_INFO_VIDEO_INPUT_SERRATION_V(*edid_info) ? 1761 ", serration v" : ""); 1762 1763 printf("Monitor is %s\n", 1764 EDID1_INFO_FEATURE_RGB(*edid_info) ? "RGB" : "non-RGB"); 1765 1766 printf("Maximum visible display size: %d cm x %d cm\n", 1767 edid_info->max_size_horizontal, 1768 edid_info->max_size_vertical); 1769 1770 printf("Power management features: %s%s, %s%s, %s%s\n", 1771 EDID1_INFO_FEATURE_ACTIVE_OFF(*edid_info) ? 1772 "" : "no ", "active off", 1773 EDID1_INFO_FEATURE_SUSPEND(*edid_info) ? "" : "no ", "suspend", 1774 EDID1_INFO_FEATURE_STANDBY(*edid_info) ? "" : "no ", "standby"); 1775 1776 printf("Estabilished timings:\n"); 1777 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_70(*edid_info)) 1778 printf("\t720x400\t\t70 Hz (VGA 640x400, IBM)\n"); 1779 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_88(*edid_info)) 1780 printf("\t720x400\t\t88 Hz (XGA2)\n"); 1781 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_60(*edid_info)) 1782 printf("\t640x480\t\t60 Hz (VGA)\n"); 1783 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_67(*edid_info)) 1784 printf("\t640x480\t\t67 Hz (Mac II, Apple)\n"); 1785 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_72(*edid_info)) 1786 printf("\t640x480\t\t72 Hz (VESA)\n"); 1787 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_75(*edid_info)) 1788 printf("\t640x480\t\t75 Hz (VESA)\n"); 1789 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_56(*edid_info)) 1790 printf("\t800x600\t\t56 Hz (VESA)\n"); 1791 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_60(*edid_info)) 1792 printf("\t800x600\t\t60 Hz (VESA)\n"); 1793 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_72(*edid_info)) 1794 printf("\t800x600\t\t72 Hz (VESA)\n"); 1795 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_75(*edid_info)) 1796 printf("\t800x600\t\t75 Hz (VESA)\n"); 1797 if (EDID1_INFO_ESTABLISHED_TIMING_832X624_75(*edid_info)) 1798 printf("\t832x624\t\t75 Hz (Mac II)\n"); 1799 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_87I(*edid_info)) 1800 printf("\t1024x768\t87 Hz Interlaced (8514A)\n"); 1801 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_60(*edid_info)) 1802 printf("\t1024x768\t60 Hz (VESA)\n"); 1803 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_70(*edid_info)) 1804 printf("\t1024x768\t70 Hz (VESA)\n"); 1805 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_75(*edid_info)) 1806 printf("\t1024x768\t75 Hz (VESA)\n"); 1807 if (EDID1_INFO_ESTABLISHED_TIMING_1280X1024_75(*edid_info)) 1808 printf("\t1280x1024\t75 (VESA)\n"); 1809 if (EDID1_INFO_ESTABLISHED_TIMING_1152X870_75(*edid_info)) 1810 printf("\t1152x870\t75 (Mac II)\n"); 1811 1812 /* Standard timings. */ 1813 printf("Standard timings:\n"); 1814 for (i = 0; i < ARRAY_SIZE(edid_info->standard_timings); i++) { 1815 unsigned int aspect = 10000; 1816 unsigned int x, y; 1817 unsigned char xres, vfreq; 1818 1819 xres = EDID1_INFO_STANDARD_TIMING_XRESOLUTION(*edid_info, i); 1820 vfreq = EDID1_INFO_STANDARD_TIMING_VFREQ(*edid_info, i); 1821 if ((xres != vfreq) || 1822 ((xres != 0) && (xres != 1)) || 1823 ((vfreq != 0) && (vfreq != 1))) { 1824 switch (EDID1_INFO_STANDARD_TIMING_ASPECT(*edid_info, 1825 i)) { 1826 case ASPECT_625: 1827 aspect = 6250; 1828 break; 1829 case ASPECT_75: 1830 aspect = 7500; 1831 break; 1832 case ASPECT_8: 1833 aspect = 8000; 1834 break; 1835 case ASPECT_5625: 1836 aspect = 5625; 1837 break; 1838 } 1839 x = (xres + 31) * 8; 1840 y = x * aspect / 10000; 1841 printf("\t%dx%d%c\t%d Hz\n", x, y, 1842 x > 1000 ? ' ' : '\t', (vfreq & 0x3f) + 60); 1843 have_timing = 1; 1844 } 1845 } 1846 1847 /* Detailed timing information. */ 1848 for (i = 0; i < ARRAY_SIZE(edid_info->monitor_details.descriptor); 1849 i++) { 1850 edid_print_dtd(&edid_info->monitor_details.descriptor[i], 1851 &have_timing); 1852 } 1853 1854 if (!have_timing) 1855 printf("\tNone\n"); 1856 } 1857 1858 /** 1859 * drm_mode_create - create a new display mode 1860 * 1861 * Create a new, cleared drm_display_mode. 1862 * 1863 * Returns: 1864 * Pointer to new mode on success, NULL on error. 1865 */ 1866 static struct drm_display_mode *drm_mode_create(void) 1867 { 1868 struct drm_display_mode *nmode; 1869 1870 nmode = malloc(sizeof(struct drm_display_mode)); 1871 memset(nmode, 0, sizeof(struct drm_display_mode)); 1872 if (!nmode) 1873 return NULL; 1874 1875 return nmode; 1876 } 1877 1878 /** 1879 * drm_mode_destroy - remove a mode 1880 * @mode: mode to remove 1881 * 1882 */ 1883 static void drm_mode_destroy(struct drm_display_mode *mode) 1884 { 1885 if (!mode) 1886 return; 1887 1888 kfree(mode); 1889 } 1890 1891 /** 1892 * drm_cvt_mode -create a modeline based on the CVT algorithm 1893 * @hdisplay: hdisplay size 1894 * @vdisplay: vdisplay size 1895 * @vrefresh: vrefresh rate 1896 * @reduced: whether to use reduced blanking 1897 * @interlaced: whether to compute an interlaced mode 1898 * @margins: whether to add margins (borders) 1899 * 1900 * This function is called to generate the modeline based on CVT algorithm 1901 * according to the hdisplay, vdisplay, vrefresh. 1902 * It is based from the VESA(TM) Coordinated Video Timing Generator by 1903 * Graham Loveridge April 9, 2003 available at 1904 * http://www.elo.utfsm.cl/~elo212/docs/CVTd6r1.xls 1905 * 1906 * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c. 1907 * What I have done is to translate it by using integer calculation. 1908 * 1909 * Returns: 1910 * The modeline based on the CVT algorithm stored in a drm_display_mode object. 1911 * The display mode object is allocated with drm_mode_create(). Returns NULL 1912 * when no mode could be allocated. 1913 */ 1914 static 1915 struct drm_display_mode *drm_cvt_mode(int hdisplay, int vdisplay, int vrefresh, 1916 bool reduced, bool interlaced, 1917 bool margins) 1918 { 1919 #define HV_FACTOR 1000 1920 /* 1) top/bottom margin size (% of height) - default: 1.8, */ 1921 #define CVT_MARGIN_PERCENTAGE 18 1922 /* 2) character cell horizontal granularity (pixels) - default 8 */ 1923 #define CVT_H_GRANULARITY 8 1924 /* 3) Minimum vertical porch (lines) - default 3 */ 1925 #define CVT_MIN_V_PORCH 3 1926 /* 4) Minimum number of vertical back porch lines - default 6 */ 1927 #define CVT_MIN_V_BPORCH 6 1928 /* Pixel Clock step (kHz) */ 1929 #define CVT_CLOCK_STEP 250 1930 struct drm_display_mode *drm_mode; 1931 unsigned int vfieldrate, hperiod; 1932 int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync; 1933 int interlace; 1934 1935 /* allocate the drm_display_mode structure. If failure, we will 1936 * return directly 1937 */ 1938 drm_mode = drm_mode_create(); 1939 if (!drm_mode) 1940 return NULL; 1941 1942 /* the CVT default refresh rate is 60Hz */ 1943 if (!vrefresh) 1944 vrefresh = 60; 1945 1946 /* the required field fresh rate */ 1947 if (interlaced) 1948 vfieldrate = vrefresh * 2; 1949 else 1950 vfieldrate = vrefresh; 1951 1952 /* horizontal pixels */ 1953 hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY); 1954 1955 /* determine the left&right borders */ 1956 hmargin = 0; 1957 if (margins) { 1958 hmargin = hdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 1959 hmargin -= hmargin % CVT_H_GRANULARITY; 1960 } 1961 /* find the total active pixels */ 1962 drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin; 1963 1964 /* find the number of lines per field */ 1965 if (interlaced) 1966 vdisplay_rnd = vdisplay / 2; 1967 else 1968 vdisplay_rnd = vdisplay; 1969 1970 /* find the top & bottom borders */ 1971 vmargin = 0; 1972 if (margins) 1973 vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 1974 1975 drm_mode->vdisplay = vdisplay + 2 * vmargin; 1976 1977 /* Interlaced */ 1978 if (interlaced) 1979 interlace = 1; 1980 else 1981 interlace = 0; 1982 1983 /* Determine VSync Width from aspect ratio */ 1984 if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay)) 1985 vsync = 4; 1986 else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay)) 1987 vsync = 5; 1988 else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay)) 1989 vsync = 6; 1990 else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay)) 1991 vsync = 7; 1992 else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay)) 1993 vsync = 7; 1994 else /* custom */ 1995 vsync = 10; 1996 1997 if (!reduced) { 1998 /* simplify the GTF calculation */ 1999 /* 4) Minimum time of vertical sync + back porch interval 2000 * default 550.0 2001 */ 2002 int tmp1, tmp2; 2003 #define CVT_MIN_VSYNC_BP 550 2004 /* 3) Nominal HSync width (% of line period) - default 8 */ 2005 #define CVT_HSYNC_PERCENTAGE 8 2006 unsigned int hblank_percentage; 2007 int vsyncandback_porch, hblank; 2008 2009 /* estimated the horizontal period */ 2010 tmp1 = HV_FACTOR * 1000000 - 2011 CVT_MIN_VSYNC_BP * HV_FACTOR * vfieldrate; 2012 tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 + 2013 interlace; 2014 hperiod = tmp1 * 2 / (tmp2 * vfieldrate); 2015 2016 tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1; 2017 /* 9. Find number of lines in sync + backporch */ 2018 if (tmp1 < (vsync + CVT_MIN_V_PORCH)) 2019 vsyncandback_porch = vsync + CVT_MIN_V_PORCH; 2020 else 2021 vsyncandback_porch = tmp1; 2022 /* 10. Find number of lines in back porch 2023 * vback_porch = vsyncandback_porch - vsync; 2024 */ 2025 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + 2026 vsyncandback_porch + CVT_MIN_V_PORCH; 2027 /* 5) Definition of Horizontal blanking time limitation */ 2028 /* Gradient (%/kHz) - default 600 */ 2029 #define CVT_M_FACTOR 600 2030 /* Offset (%) - default 40 */ 2031 #define CVT_C_FACTOR 40 2032 /* Blanking time scaling factor - default 128 */ 2033 #define CVT_K_FACTOR 128 2034 /* Scaling factor weighting - default 20 */ 2035 #define CVT_J_FACTOR 20 2036 #define CVT_M_PRIME (CVT_M_FACTOR * CVT_K_FACTOR / 256) 2037 #define CVT_C_PRIME ((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \ 2038 CVT_J_FACTOR) 2039 /* 12. Find ideal blanking duty cycle from formula */ 2040 hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME * 2041 hperiod / 1000; 2042 /* 13. Blanking time */ 2043 if (hblank_percentage < 20 * HV_FACTOR) 2044 hblank_percentage = 20 * HV_FACTOR; 2045 hblank = drm_mode->hdisplay * hblank_percentage / 2046 (100 * HV_FACTOR - hblank_percentage); 2047 hblank -= hblank % (2 * CVT_H_GRANULARITY); 2048 /* 14. find the total pixels per line */ 2049 drm_mode->htotal = drm_mode->hdisplay + hblank; 2050 drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2; 2051 drm_mode->hsync_start = drm_mode->hsync_end - 2052 (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100; 2053 drm_mode->hsync_start += CVT_H_GRANULARITY - 2054 drm_mode->hsync_start % CVT_H_GRANULARITY; 2055 /* fill the Vsync values */ 2056 drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH; 2057 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2058 } else { 2059 /* Reduced blanking */ 2060 /* Minimum vertical blanking interval time - default 460 */ 2061 #define CVT_RB_MIN_VBLANK 460 2062 /* Fixed number of clocks for horizontal sync */ 2063 #define CVT_RB_H_SYNC 32 2064 /* Fixed number of clocks for horizontal blanking */ 2065 #define CVT_RB_H_BLANK 160 2066 /* Fixed number of lines for vertical front porch - default 3*/ 2067 #define CVT_RB_VFPORCH 3 2068 int vbilines; 2069 int tmp1, tmp2; 2070 /* 8. Estimate Horizontal period. */ 2071 tmp1 = HV_FACTOR * 1000000 - 2072 CVT_RB_MIN_VBLANK * HV_FACTOR * vfieldrate; 2073 tmp2 = vdisplay_rnd + 2 * vmargin; 2074 hperiod = tmp1 / (tmp2 * vfieldrate); 2075 /* 9. Find number of lines in vertical blanking */ 2076 vbilines = CVT_RB_MIN_VBLANK * HV_FACTOR / hperiod + 1; 2077 /* 10. Check if vertical blanking is sufficient */ 2078 if (vbilines < (CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH)) 2079 vbilines = CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH; 2080 /* 11. Find total number of lines in vertical field */ 2081 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines; 2082 /* 12. Find total number of pixels in a line */ 2083 drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK; 2084 /* Fill in HSync values */ 2085 drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2; 2086 drm_mode->hsync_start = drm_mode->hsync_end - CVT_RB_H_SYNC; 2087 /* Fill in VSync values */ 2088 drm_mode->vsync_start = drm_mode->vdisplay + CVT_RB_VFPORCH; 2089 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2090 } 2091 /* 15/13. Find pixel clock frequency (kHz for xf86) */ 2092 drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod; 2093 drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP; 2094 /* 18/16. Find actual vertical frame frequency */ 2095 /* ignore - just set the mode flag for interlaced */ 2096 if (interlaced) { 2097 drm_mode->vtotal *= 2; 2098 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2099 } 2100 2101 if (reduced) 2102 drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC | 2103 DRM_MODE_FLAG_NVSYNC); 2104 else 2105 drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC | 2106 DRM_MODE_FLAG_NHSYNC); 2107 2108 return drm_mode; 2109 } 2110 2111 static int 2112 cea_db_payload_len(const u8 *db) 2113 { 2114 return db[0] & 0x1f; 2115 } 2116 2117 static int 2118 cea_db_extended_tag(const u8 *db) 2119 { 2120 return db[1]; 2121 } 2122 2123 static int 2124 cea_db_tag(const u8 *db) 2125 { 2126 return db[0] >> 5; 2127 } 2128 2129 #define for_each_cea_db(cea, i, start, end) \ 2130 for ((i) = (start); (i) < (end) && (i) + \ 2131 cea_db_payload_len(&(cea)[(i)]) < \ 2132 (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 2133 2134 static int 2135 cea_revision(const u8 *cea) 2136 { 2137 return cea[1]; 2138 } 2139 2140 static int 2141 cea_db_offsets(const u8 *cea, int *start, int *end) 2142 { 2143 /* Data block offset in CEA extension block */ 2144 *start = 4; 2145 *end = cea[2]; 2146 if (*end == 0) 2147 *end = 127; 2148 if (*end < 4 || *end > 127) 2149 return -ERANGE; 2150 2151 /* 2152 * XXX: cea[2] is equal to the real value minus one in some sink edid. 2153 */ 2154 if (*end != 4) { 2155 int i; 2156 2157 i = *start; 2158 while (i < (*end) && 2159 i + cea_db_payload_len(&(cea)[i]) < (*end)) 2160 i += cea_db_payload_len(&(cea)[i]) + 1; 2161 2162 if (cea_db_payload_len(&(cea)[i]) && 2163 i + cea_db_payload_len(&(cea)[i]) == (*end)) 2164 (*end)++; 2165 } 2166 2167 return 0; 2168 } 2169 2170 static bool cea_db_is_hdmi_vsdb(const u8 *db) 2171 { 2172 int hdmi_id; 2173 2174 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2175 return false; 2176 2177 if (cea_db_payload_len(db) < 5) 2178 return false; 2179 2180 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 2181 2182 return hdmi_id == HDMI_IEEE_OUI; 2183 } 2184 2185 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 2186 { 2187 unsigned int oui; 2188 2189 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2190 return false; 2191 2192 if (cea_db_payload_len(db) < 7) 2193 return false; 2194 2195 oui = db[3] << 16 | db[2] << 8 | db[1]; 2196 2197 return oui == HDMI_FORUM_IEEE_OUI; 2198 } 2199 2200 static bool cea_db_is_y420cmdb(const u8 *db) 2201 { 2202 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2203 return false; 2204 2205 if (!cea_db_payload_len(db)) 2206 return false; 2207 2208 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 2209 return false; 2210 2211 return true; 2212 } 2213 2214 static bool cea_db_is_y420vdb(const u8 *db) 2215 { 2216 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2217 return false; 2218 2219 if (!cea_db_payload_len(db)) 2220 return false; 2221 2222 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 2223 return false; 2224 2225 return true; 2226 } 2227 2228 static bool drm_valid_hdmi_vic(u8 vic) 2229 { 2230 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 2231 } 2232 2233 static void drm_add_hdmi_modes(struct hdmi_edid_data *data, 2234 const struct drm_display_mode *mode) 2235 { 2236 struct drm_display_mode *mode_buf = data->mode_buf; 2237 2238 if (data->modes >= MODE_LEN) 2239 return; 2240 mode_buf[(data->modes)++] = *mode; 2241 } 2242 2243 static bool drm_valid_cea_vic(u8 vic) 2244 { 2245 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 2246 } 2247 2248 static u8 svd_to_vic(u8 svd) 2249 { 2250 /* 0-6 bit vic, 7th bit native mode indicator */ 2251 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 2252 return svd & 127; 2253 2254 return svd; 2255 } 2256 2257 static struct drm_display_mode * 2258 drm_display_mode_from_vic_index(const u8 *video_db, u8 video_len, 2259 u8 video_index) 2260 { 2261 struct drm_display_mode *newmode; 2262 u8 vic; 2263 2264 if (!video_db || video_index >= video_len) 2265 return NULL; 2266 2267 /* CEA modes are numbered 1..127 */ 2268 vic = svd_to_vic(video_db[video_index]); 2269 if (!drm_valid_cea_vic(vic)) 2270 return NULL; 2271 2272 newmode = drm_mode_create(); 2273 if (!newmode) 2274 return NULL; 2275 2276 *newmode = edid_cea_modes[vic]; 2277 newmode->vrefresh = 0; 2278 2279 return newmode; 2280 } 2281 2282 static void bitmap_set(unsigned long *map, unsigned int start, int len) 2283 { 2284 unsigned long *p = map + BIT_WORD(start); 2285 const unsigned int size = start + len; 2286 int bits_to_set = BITS_PER_LONG - (start % BITS_PER_LONG); 2287 unsigned long mask_to_set = BITMAP_FIRST_WORD_MASK(start); 2288 2289 while (len - bits_to_set >= 0) { 2290 *p |= mask_to_set; 2291 len -= bits_to_set; 2292 bits_to_set = BITS_PER_LONG; 2293 mask_to_set = ~0UL; 2294 p++; 2295 } 2296 if (len) { 2297 mask_to_set &= BITMAP_LAST_WORD_MASK(size); 2298 *p |= mask_to_set; 2299 } 2300 } 2301 2302 static void 2303 drm_add_cmdb_modes(u8 svd, struct drm_hdmi_info *hdmi) 2304 { 2305 u8 vic = svd_to_vic(svd); 2306 2307 if (!drm_valid_cea_vic(vic)) 2308 return; 2309 2310 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 2311 } 2312 2313 int do_cea_modes(struct hdmi_edid_data *data, const u8 *db, u8 len) 2314 { 2315 int i, modes = 0; 2316 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2317 2318 for (i = 0; i < len; i++) { 2319 struct drm_display_mode *mode; 2320 2321 mode = drm_display_mode_from_vic_index(db, len, i); 2322 if (mode) { 2323 /* 2324 * YCBCR420 capability block contains a bitmap which 2325 * gives the index of CEA modes from CEA VDB, which 2326 * can support YCBCR 420 sampling output also (apart 2327 * from RGB/YCBCR444 etc). 2328 * For example, if the bit 0 in bitmap is set, 2329 * first mode in VDB can support YCBCR420 output too. 2330 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 2331 */ 2332 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 2333 drm_add_cmdb_modes(db[i], hdmi); 2334 drm_add_hdmi_modes(data, mode); 2335 drm_mode_destroy(mode); 2336 modes++; 2337 } 2338 } 2339 2340 return modes; 2341 } 2342 2343 /* 2344 * do_y420vdb_modes - Parse YCBCR 420 only modes 2345 * @data: the structure that save parsed hdmi edid data 2346 * @svds: start of the data block of CEA YCBCR 420 VDB 2347 * @svds_len: length of the CEA YCBCR 420 VDB 2348 * @hdmi: runtime information about the connected HDMI sink 2349 * 2350 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 2351 * which contains modes which can be supported in YCBCR 420 2352 * output format only. 2353 */ 2354 static int 2355 do_y420vdb_modes(struct hdmi_edid_data *data, const u8 *svds, u8 svds_len) 2356 { 2357 int modes = 0, i; 2358 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2359 2360 for (i = 0; i < svds_len; i++) { 2361 u8 vic = svd_to_vic(svds[i]); 2362 2363 if (!drm_valid_cea_vic(vic)) 2364 continue; 2365 2366 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 2367 drm_add_hdmi_modes(data, &edid_cea_modes[vic]); 2368 modes++; 2369 } 2370 2371 return modes; 2372 } 2373 2374 struct stereo_mandatory_mode { 2375 int width, height, vrefresh; 2376 unsigned int flags; 2377 }; 2378 2379 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2380 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2381 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2382 { 1920, 1080, 50, 2383 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2384 { 1920, 1080, 60, 2385 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2386 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2387 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2388 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2389 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2390 }; 2391 2392 static bool 2393 stereo_match_mandatory(const struct drm_display_mode *mode, 2394 const struct stereo_mandatory_mode *stereo_mode) 2395 { 2396 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2397 2398 return mode->hdisplay == stereo_mode->width && 2399 mode->vdisplay == stereo_mode->height && 2400 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2401 drm_get_vrefresh(mode) == stereo_mode->vrefresh; 2402 } 2403 2404 static int add_hdmi_mandatory_stereo_modes(struct hdmi_edid_data *data) 2405 { 2406 const struct drm_display_mode *mode; 2407 int num = data->modes, modes = 0, i, k; 2408 2409 for (k = 0; k < num; k++) { 2410 mode = &data->mode_buf[k]; 2411 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2412 const struct stereo_mandatory_mode *mandatory; 2413 struct drm_display_mode *new_mode; 2414 2415 if (!stereo_match_mandatory(mode, 2416 &stereo_mandatory_modes[i])) 2417 continue; 2418 2419 mandatory = &stereo_mandatory_modes[i]; 2420 new_mode = drm_mode_create(); 2421 if (!new_mode) 2422 continue; 2423 2424 *new_mode = *mode; 2425 new_mode->flags |= mandatory->flags; 2426 drm_add_hdmi_modes(data, new_mode); 2427 drm_mode_destroy(new_mode); 2428 modes++; 2429 } 2430 } 2431 2432 return modes; 2433 } 2434 2435 static int add_3d_struct_modes(struct hdmi_edid_data *data, u16 structure, 2436 const u8 *video_db, u8 video_len, u8 video_index) 2437 { 2438 struct drm_display_mode *newmode; 2439 int modes = 0; 2440 2441 if (structure & (1 << 0)) { 2442 newmode = drm_display_mode_from_vic_index(video_db, 2443 video_len, 2444 video_index); 2445 if (newmode) { 2446 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2447 drm_add_hdmi_modes(data, newmode); 2448 modes++; 2449 drm_mode_destroy(newmode); 2450 } 2451 } 2452 if (structure & (1 << 6)) { 2453 newmode = drm_display_mode_from_vic_index(video_db, 2454 video_len, 2455 video_index); 2456 if (newmode) { 2457 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2458 drm_add_hdmi_modes(data, newmode); 2459 modes++; 2460 drm_mode_destroy(newmode); 2461 } 2462 } 2463 if (structure & (1 << 8)) { 2464 newmode = drm_display_mode_from_vic_index(video_db, 2465 video_len, 2466 video_index); 2467 if (newmode) { 2468 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2469 drm_add_hdmi_modes(data, newmode); 2470 modes++; 2471 drm_mode_destroy(newmode); 2472 } 2473 } 2474 2475 return modes; 2476 } 2477 2478 static int add_hdmi_mode(struct hdmi_edid_data *data, u8 vic) 2479 { 2480 if (!drm_valid_hdmi_vic(vic)) { 2481 debug("Unknown HDMI VIC: %d\n", vic); 2482 return 0; 2483 } 2484 2485 drm_add_hdmi_modes(data, &edid_4k_modes[vic]); 2486 2487 return 1; 2488 } 2489 2490 /* 2491 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2492 * @db: start of the CEA vendor specific block 2493 * @len: length of the CEA block payload, ie. one can access up to db[len] 2494 * 2495 * Parses the HDMI VSDB looking for modes to add to @data. This function 2496 * also adds the stereo 3d modes when applicable. 2497 */ 2498 static int 2499 do_hdmi_vsdb_modes(const u8 *db, u8 len, const u8 *video_db, u8 video_len, 2500 struct hdmi_edid_data *data) 2501 { 2502 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2503 u8 vic_len, hdmi_3d_len = 0; 2504 u16 mask; 2505 u16 structure_all; 2506 2507 if (len < 8) 2508 goto out; 2509 2510 /* no HDMI_Video_Present */ 2511 if (!(db[8] & (1 << 5))) 2512 goto out; 2513 2514 /* Latency_Fields_Present */ 2515 if (db[8] & (1 << 7)) 2516 offset += 2; 2517 2518 /* I_Latency_Fields_Present */ 2519 if (db[8] & (1 << 6)) 2520 offset += 2; 2521 2522 /* the declared length is not long enough for the 2 first bytes 2523 * of additional video format capabilities 2524 */ 2525 if (len < (8 + offset + 2)) 2526 goto out; 2527 2528 /* 3D_Present */ 2529 offset++; 2530 if (db[8 + offset] & (1 << 7)) { 2531 modes += add_hdmi_mandatory_stereo_modes(data); 2532 2533 /* 3D_Multi_present */ 2534 multi_present = (db[8 + offset] & 0x60) >> 5; 2535 } 2536 2537 offset++; 2538 vic_len = db[8 + offset] >> 5; 2539 hdmi_3d_len = db[8 + offset] & 0x1f; 2540 2541 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 2542 u8 vic; 2543 2544 vic = db[9 + offset + i]; 2545 modes += add_hdmi_mode(data, vic); 2546 } 2547 2548 offset += 1 + vic_len; 2549 2550 if (multi_present == 1) 2551 multi_len = 2; 2552 else if (multi_present == 2) 2553 multi_len = 4; 2554 else 2555 multi_len = 0; 2556 2557 if (len < (8 + offset + hdmi_3d_len - 1)) 2558 goto out; 2559 2560 if (hdmi_3d_len < multi_len) 2561 goto out; 2562 2563 if (multi_present == 1 || multi_present == 2) { 2564 /* 3D_Structure_ALL */ 2565 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 2566 2567 /* check if 3D_MASK is present */ 2568 if (multi_present == 2) 2569 mask = (db[10 + offset] << 8) | db[11 + offset]; 2570 else 2571 mask = 0xffff; 2572 2573 for (i = 0; i < 16; i++) { 2574 if (mask & (1 << i)) 2575 modes += add_3d_struct_modes(data, 2576 structure_all, 2577 video_db, 2578 video_len, i); 2579 } 2580 } 2581 2582 offset += multi_len; 2583 2584 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 2585 int vic_index; 2586 struct drm_display_mode *newmode = NULL; 2587 unsigned int newflag = 0; 2588 bool detail_present; 2589 2590 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 2591 2592 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 2593 break; 2594 2595 /* 2D_VIC_order_X */ 2596 vic_index = db[8 + offset + i] >> 4; 2597 2598 /* 3D_Structure_X */ 2599 switch (db[8 + offset + i] & 0x0f) { 2600 case 0: 2601 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 2602 break; 2603 case 6: 2604 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2605 break; 2606 case 8: 2607 /* 3D_Detail_X */ 2608 if ((db[9 + offset + i] >> 4) == 1) 2609 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2610 break; 2611 } 2612 2613 if (newflag != 0) { 2614 newmode = drm_display_mode_from_vic_index( 2615 video_db, 2616 video_len, 2617 vic_index); 2618 2619 if (newmode) { 2620 newmode->flags |= newflag; 2621 drm_add_hdmi_modes(data, newmode); 2622 modes++; 2623 drm_mode_destroy(newmode); 2624 } 2625 } 2626 2627 if (detail_present) 2628 i++; 2629 } 2630 2631 out: 2632 return modes; 2633 } 2634 2635 /** 2636 * edid_get_quirks - return quirk flags for a given EDID 2637 * @edid: EDID to process 2638 * 2639 * This tells subsequent routines what fixes they need to apply. 2640 */ 2641 static u32 edid_get_quirks(struct edid *edid) 2642 { 2643 struct edid_quirk *quirk; 2644 int i; 2645 2646 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2647 quirk = &edid_quirk_list[i]; 2648 2649 if (edid_vendor(edid, quirk->vendor) && 2650 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 2651 return quirk->quirks; 2652 } 2653 2654 return 0; 2655 } 2656 2657 static void drm_parse_y420cmdb_bitmap(struct hdmi_edid_data *data, 2658 const u8 *db) 2659 { 2660 struct drm_display_info *info = &data->display_info; 2661 struct drm_hdmi_info *hdmi = &info->hdmi; 2662 u8 map_len = cea_db_payload_len(db) - 1; 2663 u8 count; 2664 u64 map = 0; 2665 2666 if (map_len == 0) { 2667 /* All CEA modes support ycbcr420 sampling also.*/ 2668 hdmi->y420_cmdb_map = U64_MAX; 2669 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 2670 return; 2671 } 2672 2673 /* 2674 * This map indicates which of the existing CEA block modes 2675 * from VDB can support YCBCR420 output too. So if bit=0 is 2676 * set, first mode from VDB can support YCBCR420 output too. 2677 * We will parse and keep this map, before parsing VDB itself 2678 * to avoid going through the same block again and again. 2679 * 2680 * Spec is not clear about max possible size of this block. 2681 * Clamping max bitmap block size at 8 bytes. Every byte can 2682 * address 8 CEA modes, in this way this map can address 2683 * 8*8 = first 64 SVDs. 2684 */ 2685 if (map_len > 8) 2686 map_len = 8; 2687 2688 for (count = 0; count < map_len; count++) 2689 map |= (u64)db[2 + count] << (8 * count); 2690 2691 if (map) 2692 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 2693 2694 hdmi->y420_cmdb_map = map; 2695 } 2696 2697 static void drm_parse_ycbcr420_deep_color_info(struct hdmi_edid_data *data, 2698 const u8 *db) 2699 { 2700 u8 dc_mask; 2701 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2702 2703 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 2704 hdmi->y420_dc_modes |= dc_mask; 2705 } 2706 2707 static void drm_parse_hdmi_forum_vsdb(struct hdmi_edid_data *data, 2708 const u8 *hf_vsdb) 2709 { 2710 struct drm_display_info *display = &data->display_info; 2711 struct drm_hdmi_info *hdmi = &display->hdmi; 2712 2713 if (hf_vsdb[6] & 0x80) { 2714 hdmi->scdc.supported = true; 2715 if (hf_vsdb[6] & 0x40) 2716 hdmi->scdc.read_request = true; 2717 } 2718 2719 /* 2720 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 2721 * And as per the spec, three factors confirm this: 2722 * * Availability of a HF-VSDB block in EDID (check) 2723 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 2724 * * SCDC support available (let's check) 2725 * Lets check it out. 2726 */ 2727 2728 if (hf_vsdb[5]) { 2729 /* max clock is 5000 KHz times block value */ 2730 u32 max_tmds_clock = hf_vsdb[5] * 5000; 2731 struct drm_scdc *scdc = &hdmi->scdc; 2732 2733 if (max_tmds_clock > 340000) { 2734 display->max_tmds_clock = max_tmds_clock; 2735 debug("HF-VSDB: max TMDS clock %d kHz\n", 2736 display->max_tmds_clock); 2737 } 2738 2739 if (scdc->supported) { 2740 scdc->scrambling.supported = true; 2741 2742 /* Few sinks support scrambling for cloks < 340M */ 2743 if ((hf_vsdb[6] & 0x8)) 2744 scdc->scrambling.low_rates = true; 2745 } 2746 } 2747 2748 drm_parse_ycbcr420_deep_color_info(data, hf_vsdb); 2749 } 2750 2751 static void drm_parse_hdmi_deep_color_info(struct hdmi_edid_data *data, 2752 const u8 *hdmi) 2753 { 2754 struct drm_display_info *info = &data->display_info; 2755 unsigned int dc_bpc = 0; 2756 2757 /* HDMI supports at least 8 bpc */ 2758 info->bpc = 8; 2759 2760 if (cea_db_payload_len(hdmi) < 6) 2761 return; 2762 2763 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 2764 dc_bpc = 10; 2765 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 2766 debug("HDMI sink does deep color 30.\n"); 2767 } 2768 2769 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 2770 dc_bpc = 12; 2771 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 2772 debug("HDMI sink does deep color 36.\n"); 2773 } 2774 2775 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 2776 dc_bpc = 16; 2777 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 2778 debug("HDMI sink does deep color 48.\n"); 2779 } 2780 2781 if (dc_bpc == 0) { 2782 debug("No deep color support on this HDMI sink.\n"); 2783 return; 2784 } 2785 2786 debug("Assigning HDMI sink color depth as %d bpc.\n", dc_bpc); 2787 info->bpc = dc_bpc; 2788 2789 /* YCRCB444 is optional according to spec. */ 2790 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 2791 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_Y444; 2792 debug("HDMI sink does YCRCB444 in deep color.\n"); 2793 } 2794 2795 /* 2796 * Spec says that if any deep color mode is supported at all, 2797 * then deep color 36 bit must be supported. 2798 */ 2799 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) 2800 debug("HDMI sink should do DC_36, but does not!\n"); 2801 } 2802 2803 /* 2804 * Search EDID for CEA extension block. 2805 */ 2806 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 2807 { 2808 u8 *edid_ext = NULL; 2809 int i; 2810 2811 /* No EDID or EDID extensions */ 2812 if (!edid || !edid->extensions) 2813 return NULL; 2814 2815 /* Find CEA extension */ 2816 for (i = 0; i < edid->extensions; i++) { 2817 edid_ext = (u8 *)edid + EDID_SIZE * (i + 1); 2818 if (edid_ext[0] == ext_id) 2819 break; 2820 } 2821 2822 if (i == edid->extensions) 2823 return NULL; 2824 2825 return edid_ext; 2826 } 2827 2828 static u8 *drm_find_cea_extension(struct edid *edid) 2829 { 2830 return drm_find_edid_extension(edid, 0x02); 2831 } 2832 2833 #define AUDIO_BLOCK 0x01 2834 #define VIDEO_BLOCK 0x02 2835 #define VENDOR_BLOCK 0x03 2836 #define SPEAKER_BLOCK 0x04 2837 #define EDID_BASIC_AUDIO BIT(6) 2838 2839 /** 2840 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 2841 * @edid: monitor EDID information 2842 * 2843 * Parse the CEA extension according to CEA-861-B. 2844 * 2845 * Return: True if the monitor is HDMI, false if not or unknown. 2846 */ 2847 bool drm_detect_hdmi_monitor(struct edid *edid) 2848 { 2849 u8 *edid_ext; 2850 int i; 2851 int start_offset, end_offset; 2852 2853 edid_ext = drm_find_cea_extension(edid); 2854 if (!edid_ext) 2855 return false; 2856 2857 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 2858 return false; 2859 2860 /* 2861 * Because HDMI identifier is in Vendor Specific Block, 2862 * search it from all data blocks of CEA extension. 2863 */ 2864 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 2865 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 2866 return true; 2867 } 2868 2869 return false; 2870 } 2871 2872 /** 2873 * drm_detect_monitor_audio - check monitor audio capability 2874 * @edid: EDID block to scan 2875 * 2876 * Monitor should have CEA extension block. 2877 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 2878 * audio' only. If there is any audio extension block and supported 2879 * audio format, assume at least 'basic audio' support, even if 'basic 2880 * audio' is not defined in EDID. 2881 * 2882 * Return: True if the monitor supports audio, false otherwise. 2883 */ 2884 bool drm_detect_monitor_audio(struct edid *edid) 2885 { 2886 u8 *edid_ext; 2887 int i, j; 2888 bool has_audio = false; 2889 int start_offset, end_offset; 2890 2891 edid_ext = drm_find_cea_extension(edid); 2892 if (!edid_ext) 2893 goto end; 2894 2895 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 2896 2897 if (has_audio) { 2898 printf("Monitor has basic audio support\n"); 2899 goto end; 2900 } 2901 2902 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 2903 goto end; 2904 2905 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 2906 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 2907 has_audio = true; 2908 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; 2909 j += 3) 2910 debug("CEA audio format %d\n", 2911 (edid_ext[i + j] >> 3) & 0xf); 2912 goto end; 2913 } 2914 } 2915 end: 2916 return has_audio; 2917 } 2918 2919 static void 2920 drm_parse_hdmi_vsdb_video(struct hdmi_edid_data *data, const u8 *db) 2921 { 2922 struct drm_display_info *info = &data->display_info; 2923 u8 len = cea_db_payload_len(db); 2924 2925 if (len >= 6) 2926 info->dvi_dual = db[6] & 1; 2927 if (len >= 7) 2928 info->max_tmds_clock = db[7] * 5000; 2929 2930 drm_parse_hdmi_deep_color_info(data, db); 2931 } 2932 2933 static void drm_parse_cea_ext(struct hdmi_edid_data *data, 2934 struct edid *edid) 2935 { 2936 struct drm_display_info *info = &data->display_info; 2937 const u8 *edid_ext; 2938 int i, start, end; 2939 2940 edid_ext = drm_find_cea_extension(edid); 2941 if (!edid_ext) 2942 return; 2943 2944 info->cea_rev = edid_ext[1]; 2945 2946 /* The existence of a CEA block should imply RGB support */ 2947 info->color_formats = DRM_COLOR_FORMAT_RGB444; 2948 if (edid_ext[3] & EDID_CEA_YCRCB444) 2949 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 2950 if (edid_ext[3] & EDID_CEA_YCRCB422) 2951 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 2952 2953 if (cea_db_offsets(edid_ext, &start, &end)) 2954 return; 2955 2956 for_each_cea_db(edid_ext, i, start, end) { 2957 const u8 *db = &edid_ext[i]; 2958 2959 if (cea_db_is_hdmi_vsdb(db)) 2960 drm_parse_hdmi_vsdb_video(data, db); 2961 if (cea_db_is_hdmi_forum_vsdb(db)) 2962 drm_parse_hdmi_forum_vsdb(data, db); 2963 if (cea_db_is_y420cmdb(db)) 2964 drm_parse_y420cmdb_bitmap(data, db); 2965 } 2966 } 2967 2968 static void drm_add_display_info(struct hdmi_edid_data *data, struct edid *edid) 2969 { 2970 struct drm_display_info *info = &data->display_info; 2971 2972 info->width_mm = edid->width_cm * 10; 2973 info->height_mm = edid->height_cm * 10; 2974 2975 /* driver figures it out in this case */ 2976 info->bpc = 0; 2977 info->color_formats = 0; 2978 info->cea_rev = 0; 2979 info->max_tmds_clock = 0; 2980 info->dvi_dual = false; 2981 info->edid_hdmi_dc_modes = 0; 2982 2983 memset(&info->hdmi, 0, sizeof(info->hdmi)); 2984 2985 if (edid->revision < 3) 2986 return; 2987 2988 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 2989 return; 2990 2991 drm_parse_cea_ext(data, edid); 2992 2993 /* 2994 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 2995 * 2996 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 2997 * tells us to assume 8 bpc color depth if the EDID doesn't have 2998 * extensions which tell otherwise. 2999 */ 3000 if ((info->bpc == 0) && (edid->revision < 4) && 3001 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 3002 info->bpc = 8; 3003 debug("Assigning DFP sink color depth as %d bpc.\n", info->bpc); 3004 } 3005 3006 /* Only defined for 1.4 with digital displays */ 3007 if (edid->revision < 4) 3008 return; 3009 3010 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3011 case DRM_EDID_DIGITAL_DEPTH_6: 3012 info->bpc = 6; 3013 break; 3014 case DRM_EDID_DIGITAL_DEPTH_8: 3015 info->bpc = 8; 3016 break; 3017 case DRM_EDID_DIGITAL_DEPTH_10: 3018 info->bpc = 10; 3019 break; 3020 case DRM_EDID_DIGITAL_DEPTH_12: 3021 info->bpc = 12; 3022 break; 3023 case DRM_EDID_DIGITAL_DEPTH_14: 3024 info->bpc = 14; 3025 break; 3026 case DRM_EDID_DIGITAL_DEPTH_16: 3027 info->bpc = 16; 3028 break; 3029 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3030 default: 3031 info->bpc = 0; 3032 break; 3033 } 3034 3035 debug("Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3036 info->bpc); 3037 3038 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3039 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3040 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3041 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3042 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3043 } 3044 3045 static 3046 int add_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 3047 { 3048 const u8 *cea = drm_find_cea_extension(edid); 3049 const u8 *db, *hdmi = NULL, *video = NULL; 3050 u8 dbl, hdmi_len, video_len = 0; 3051 int modes = 0; 3052 3053 if (cea && cea_revision(cea) >= 3) { 3054 int i, start, end; 3055 3056 if (cea_db_offsets(cea, &start, &end)) 3057 return 0; 3058 3059 for_each_cea_db(cea, i, start, end) { 3060 db = &cea[i]; 3061 dbl = cea_db_payload_len(db); 3062 3063 if (cea_db_tag(db) == EDID_CEA861_DB_VIDEO) { 3064 video = db + 1; 3065 video_len = dbl; 3066 modes += do_cea_modes(data, video, dbl); 3067 } else if (cea_db_is_hdmi_vsdb(db)) { 3068 hdmi = db; 3069 hdmi_len = dbl; 3070 } else if (cea_db_is_y420vdb(db)) { 3071 const u8 *vdb420 = &db[2]; 3072 3073 /* Add 4:2:0(only) modes present in EDID */ 3074 modes += do_y420vdb_modes(data, vdb420, 3075 dbl - 1); 3076 } 3077 } 3078 } 3079 3080 /* 3081 * We parse the HDMI VSDB after having added the cea modes as we will 3082 * be patching their flags when the sink supports stereo 3D. 3083 */ 3084 if (hdmi) 3085 modes += do_hdmi_vsdb_modes(hdmi, hdmi_len, video, 3086 video_len, data); 3087 3088 return modes; 3089 } 3090 3091 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 3092 3093 static void 3094 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3095 { 3096 int i, n = 0; 3097 u8 d = ext[0x02]; 3098 u8 *det_base = ext + d; 3099 3100 n = (127 - d) / 18; 3101 for (i = 0; i < n; i++) 3102 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3103 } 3104 3105 static void 3106 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3107 { 3108 unsigned int i, n = min((int)ext[0x02], 6); 3109 u8 *det_base = ext + 5; 3110 3111 if (ext[0x01] != 1) 3112 return; /* unknown version */ 3113 3114 for (i = 0; i < n; i++) 3115 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3116 } 3117 3118 static void 3119 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 3120 { 3121 int i; 3122 struct edid *edid = (struct edid *)raw_edid; 3123 3124 if (!edid) 3125 return; 3126 3127 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3128 cb(&edid->detailed_timings[i], closure); 3129 3130 for (i = 1; i <= raw_edid[0x7e]; i++) { 3131 u8 *ext = raw_edid + (i * EDID_SIZE); 3132 3133 switch (*ext) { 3134 case CEA_EXT: 3135 cea_for_each_detailed_block(ext, cb, closure); 3136 break; 3137 case VTB_EXT: 3138 vtb_for_each_detailed_block(ext, cb, closure); 3139 break; 3140 default: 3141 break; 3142 } 3143 } 3144 } 3145 3146 /* 3147 * EDID is delightfully ambiguous about how interlaced modes are to be 3148 * encoded. Our internal representation is of frame height, but some 3149 * HDTV detailed timings are encoded as field height. 3150 * 3151 * The format list here is from CEA, in frame size. Technically we 3152 * should be checking refresh rate too. Whatever. 3153 */ 3154 static void 3155 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3156 struct detailed_pixel_timing *pt) 3157 { 3158 int i; 3159 3160 static const struct { 3161 int w, h; 3162 } cea_interlaced[] = { 3163 { 1920, 1080 }, 3164 { 720, 480 }, 3165 { 1440, 480 }, 3166 { 2880, 480 }, 3167 { 720, 576 }, 3168 { 1440, 576 }, 3169 { 2880, 576 }, 3170 }; 3171 3172 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3173 return; 3174 3175 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3176 if ((mode->hdisplay == cea_interlaced[i].w) && 3177 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3178 mode->vdisplay *= 2; 3179 mode->vsync_start *= 2; 3180 mode->vsync_end *= 2; 3181 mode->vtotal *= 2; 3182 mode->vtotal |= 1; 3183 } 3184 } 3185 3186 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3187 } 3188 3189 /** 3190 * drm_mode_detailed - create a new mode from an EDID detailed timing section 3191 * @edid: EDID block 3192 * @timing: EDID detailed timing info 3193 * @quirks: quirks to apply 3194 * 3195 * An EDID detailed timing block contains enough info for us to create and 3196 * return a new struct drm_display_mode. 3197 */ 3198 static 3199 struct drm_display_mode *drm_mode_detailed(struct edid *edid, 3200 struct detailed_timing *timing, 3201 u32 quirks) 3202 { 3203 struct drm_display_mode *mode; 3204 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3205 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3206 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3207 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3208 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3209 unsigned hsync_offset = 3210 (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | 3211 pt->hsync_offset_lo; 3212 unsigned hsync_pulse_width = 3213 (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | 3214 pt->hsync_pulse_width_lo; 3215 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 3216 2 | pt->vsync_offset_pulse_width_lo >> 4; 3217 unsigned vsync_pulse_width = 3218 (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | 3219 (pt->vsync_offset_pulse_width_lo & 0xf); 3220 3221 /* ignore tiny modes */ 3222 if (hactive < 64 || vactive < 64) 3223 return NULL; 3224 3225 if (pt->misc & DRM_EDID_PT_STEREO) { 3226 debug("stereo mode not supported\n"); 3227 return NULL; 3228 } 3229 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) 3230 debug("composite sync not supported\n"); 3231 3232 /* it is incorrect if hsync/vsync width is zero */ 3233 if (!hsync_pulse_width || !vsync_pulse_width) { 3234 debug("Incorrect Detailed timing. "); 3235 debug("Wrong Hsync/Vsync pulse width\n"); 3236 return NULL; 3237 } 3238 3239 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3240 mode = drm_cvt_mode(hactive, vactive, 60, true, false, false); 3241 if (!mode) 3242 return NULL; 3243 3244 goto set_refresh; 3245 } 3246 3247 mode = drm_mode_create(); 3248 if (!mode) 3249 return NULL; 3250 3251 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3252 timing->pixel_clock = cpu_to_le16(1088); 3253 3254 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3255 3256 mode->hdisplay = hactive; 3257 mode->hsync_start = mode->hdisplay + hsync_offset; 3258 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3259 mode->htotal = mode->hdisplay + hblank; 3260 3261 mode->vdisplay = vactive; 3262 mode->vsync_start = mode->vdisplay + vsync_offset; 3263 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3264 mode->vtotal = mode->vdisplay + vblank; 3265 3266 /* Some EDIDs have bogus h/vtotal values */ 3267 if (mode->hsync_end > mode->htotal) 3268 mode->htotal = mode->hsync_end + 1; 3269 if (mode->vsync_end > mode->vtotal) 3270 mode->vtotal = mode->vsync_end + 1; 3271 3272 drm_mode_do_interlace_quirk(mode, pt); 3273 3274 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) 3275 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | 3276 DRM_EDID_PT_VSYNC_POSITIVE; 3277 3278 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3279 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3280 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3281 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3282 3283 set_refresh: 3284 3285 mode->type = DRM_MODE_TYPE_DRIVER; 3286 mode->vrefresh = drm_get_vrefresh(mode); 3287 3288 return mode; 3289 } 3290 3291 /* 3292 * Calculate the alternate clock for the CEA mode 3293 * (60Hz vs. 59.94Hz etc.) 3294 */ 3295 static unsigned int 3296 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3297 { 3298 unsigned int clock = cea_mode->clock; 3299 3300 if (cea_mode->vrefresh % 6 != 0) 3301 return clock; 3302 3303 /* 3304 * edid_cea_modes contains the 59.94Hz 3305 * variant for 240 and 480 line modes, 3306 * and the 60Hz variant otherwise. 3307 */ 3308 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3309 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3310 else 3311 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3312 3313 return clock; 3314 } 3315 3316 /** 3317 * drm_mode_equal_no_clocks_no_stereo - test modes for equality 3318 * @mode1: first mode 3319 * @mode2: second mode 3320 * 3321 * Check to see if @mode1 and @mode2 are equivalent, but 3322 * don't check the pixel clocks nor the stereo layout. 3323 * 3324 * Returns: 3325 * True if the modes are equal, false otherwise. 3326 */ 3327 3328 static 3329 bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1, 3330 const struct drm_display_mode *mode2) 3331 { 3332 unsigned int flags_mask = 3333 ~(DRM_MODE_FLAG_3D_MASK | DRM_MODE_FLAG_420_MASK); 3334 3335 if (mode1->hdisplay == mode2->hdisplay && 3336 mode1->hsync_start == mode2->hsync_start && 3337 mode1->hsync_end == mode2->hsync_end && 3338 mode1->htotal == mode2->htotal && 3339 mode1->vdisplay == mode2->vdisplay && 3340 mode1->vsync_start == mode2->vsync_start && 3341 mode1->vsync_end == mode2->vsync_end && 3342 mode1->vtotal == mode2->vtotal && 3343 mode1->vscan == mode2->vscan && 3344 (mode1->flags & flags_mask) == (mode2->flags & flags_mask)) 3345 return true; 3346 3347 return false; 3348 } 3349 3350 /** 3351 * drm_mode_equal_no_clocks - test modes for equality 3352 * @mode1: first mode 3353 * @mode2: second mode 3354 * 3355 * Check to see if @mode1 and @mode2 are equivalent, but 3356 * don't check the pixel clocks. 3357 * 3358 * Returns: 3359 * True if the modes are equal, false otherwise. 3360 */ 3361 static bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1, 3362 const struct drm_display_mode *mode2) 3363 { 3364 if ((mode1->flags & DRM_MODE_FLAG_3D_MASK) != 3365 (mode2->flags & DRM_MODE_FLAG_3D_MASK)) 3366 return false; 3367 3368 return drm_mode_equal_no_clocks_no_stereo(mode1, mode2); 3369 } 3370 3371 static 3372 u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3373 unsigned int clock_tolerance) 3374 { 3375 u8 vic; 3376 3377 if (!to_match->clock) 3378 return 0; 3379 3380 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 3381 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 3382 unsigned int clock1, clock2; 3383 3384 /* Check both 60Hz and 59.94Hz */ 3385 clock1 = cea_mode->clock; 3386 clock2 = cea_mode_alternate_clock(cea_mode); 3387 3388 if (abs(to_match->clock - clock1) > clock_tolerance && 3389 abs(to_match->clock - clock2) > clock_tolerance) 3390 continue; 3391 3392 if (drm_mode_equal_no_clocks(to_match, cea_mode)) 3393 return vic; 3394 } 3395 3396 return 0; 3397 } 3398 3399 static unsigned int 3400 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3401 { 3402 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 3403 return hdmi_mode->clock; 3404 3405 return cea_mode_alternate_clock(hdmi_mode); 3406 } 3407 3408 static 3409 u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3410 unsigned int clock_tolerance) 3411 { 3412 u8 vic; 3413 3414 if (!to_match->clock) 3415 return 0; 3416 3417 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3418 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3419 unsigned int clock1, clock2; 3420 3421 /* Make sure to also match alternate clocks */ 3422 clock1 = hdmi_mode->clock; 3423 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3424 3425 if (abs(to_match->clock - clock1) > clock_tolerance && 3426 abs(to_match->clock - clock2) > clock_tolerance) 3427 continue; 3428 3429 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 3430 return vic; 3431 } 3432 3433 return 0; 3434 } 3435 3436 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3437 { 3438 const struct drm_display_mode *cea_mode; 3439 int clock1, clock2, clock; 3440 u8 vic; 3441 const char *type; 3442 3443 /* 3444 * allow 5kHz clock difference either way to account for 3445 * the 10kHz clock resolution limit of detailed timings. 3446 */ 3447 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3448 if (drm_valid_cea_vic(vic)) { 3449 type = "CEA"; 3450 cea_mode = &edid_cea_modes[vic]; 3451 clock1 = cea_mode->clock; 3452 clock2 = cea_mode_alternate_clock(cea_mode); 3453 } else { 3454 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3455 if (drm_valid_hdmi_vic(vic)) { 3456 type = "HDMI"; 3457 cea_mode = &edid_4k_modes[vic]; 3458 clock1 = cea_mode->clock; 3459 clock2 = hdmi_mode_alternate_clock(cea_mode); 3460 } else { 3461 return; 3462 } 3463 } 3464 3465 /* pick whichever is closest */ 3466 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3467 clock = clock1; 3468 else 3469 clock = clock2; 3470 3471 if (mode->clock == clock) 3472 return; 3473 3474 debug("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3475 type, vic, mode->clock, clock); 3476 mode->clock = clock; 3477 } 3478 3479 static void 3480 do_detailed_mode(struct detailed_timing *timing, void *c) 3481 { 3482 struct detailed_mode_closure *closure = c; 3483 struct drm_display_mode *newmode; 3484 3485 if (timing->pixel_clock) { 3486 newmode = drm_mode_detailed( 3487 closure->edid, timing, 3488 closure->quirks); 3489 if (!newmode) 3490 return; 3491 3492 if (closure->preferred) 3493 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3494 3495 /* 3496 * Detailed modes are limited to 10kHz pixel clock resolution, 3497 * so fix up anything that looks like CEA/HDMI mode, 3498 * but the clock is just slightly off. 3499 */ 3500 fixup_detailed_cea_mode_clock(newmode); 3501 drm_add_hdmi_modes(closure->data, newmode); 3502 drm_mode_destroy(newmode); 3503 closure->modes++; 3504 closure->preferred = 0; 3505 } 3506 } 3507 3508 /* 3509 * add_detailed_modes - Add modes from detailed timings 3510 * @data: attached data 3511 * @edid: EDID block to scan 3512 * @quirks: quirks to apply 3513 */ 3514 static int 3515 add_detailed_modes(struct hdmi_edid_data *data, struct edid *edid, 3516 u32 quirks) 3517 { 3518 struct detailed_mode_closure closure = { 3519 .data = data, 3520 .edid = edid, 3521 .preferred = 1, 3522 .quirks = quirks, 3523 }; 3524 3525 if (closure.preferred && !version_greater(edid, 1, 3)) 3526 closure.preferred = 3527 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3528 3529 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 3530 3531 return closure.modes; 3532 } 3533 3534 static int drm_cvt_modes(struct hdmi_edid_data *data, 3535 struct detailed_timing *timing) 3536 { 3537 int i, j, modes = 0; 3538 struct drm_display_mode *newmode; 3539 struct cvt_timing *cvt; 3540 const int rates[] = { 60, 85, 75, 60, 50 }; 3541 const u8 empty[3] = { 0, 0, 0 }; 3542 3543 for (i = 0; i < 4; i++) { 3544 int uninitialized_var(width), height; 3545 3546 cvt = &timing->data.other_data.data.cvt[i]; 3547 3548 if (!memcmp(cvt->code, empty, 3)) 3549 continue; 3550 3551 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3552 switch (cvt->code[1] & 0x0c) { 3553 case 0x00: 3554 width = height * 4 / 3; 3555 break; 3556 case 0x04: 3557 width = height * 16 / 9; 3558 break; 3559 case 0x08: 3560 width = height * 16 / 10; 3561 break; 3562 case 0x0c: 3563 width = height * 15 / 9; 3564 break; 3565 } 3566 3567 for (j = 1; j < 5; j++) { 3568 if (cvt->code[2] & (1 << j)) { 3569 newmode = drm_cvt_mode(width, height, 3570 rates[j], j == 0, 3571 false, false); 3572 if (newmode) { 3573 drm_add_hdmi_modes(data, newmode); 3574 modes++; 3575 drm_mode_destroy(newmode); 3576 } 3577 } 3578 } 3579 } 3580 3581 return modes; 3582 } 3583 3584 static void 3585 do_cvt_mode(struct detailed_timing *timing, void *c) 3586 { 3587 struct detailed_mode_closure *closure = c; 3588 struct detailed_non_pixel *data = &timing->data.other_data; 3589 3590 if (data->type == EDID_DETAIL_CVT_3BYTE) 3591 closure->modes += drm_cvt_modes(closure->data, timing); 3592 } 3593 3594 static int 3595 add_cvt_modes(struct hdmi_edid_data *data, struct edid *edid) 3596 { 3597 struct detailed_mode_closure closure = { 3598 .data = data, 3599 .edid = edid, 3600 }; 3601 3602 if (version_greater(edid, 1, 2)) 3603 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 3604 3605 /* XXX should also look for CVT codes in VTB blocks */ 3606 3607 return closure.modes; 3608 } 3609 3610 static void 3611 find_gtf2(struct detailed_timing *t, void *data) 3612 { 3613 u8 *r = (u8 *)t; 3614 3615 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 3616 *(u8 **)data = r; 3617 } 3618 3619 /* Secondary GTF curve kicks in above some break frequency */ 3620 static int 3621 drm_gtf2_hbreak(struct edid *edid) 3622 { 3623 u8 *r = NULL; 3624 3625 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3626 return r ? (r[12] * 2) : 0; 3627 } 3628 3629 static int 3630 drm_gtf2_2c(struct edid *edid) 3631 { 3632 u8 *r = NULL; 3633 3634 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3635 return r ? r[13] : 0; 3636 } 3637 3638 static int 3639 drm_gtf2_m(struct edid *edid) 3640 { 3641 u8 *r = NULL; 3642 3643 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3644 return r ? (r[15] << 8) + r[14] : 0; 3645 } 3646 3647 static int 3648 drm_gtf2_k(struct edid *edid) 3649 { 3650 u8 *r = NULL; 3651 3652 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3653 return r ? r[16] : 0; 3654 } 3655 3656 static int 3657 drm_gtf2_2j(struct edid *edid) 3658 { 3659 u8 *r = NULL; 3660 3661 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 3662 return r ? r[17] : 0; 3663 } 3664 3665 /** 3666 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 3667 * @edid: EDID block to scan 3668 */ 3669 static int standard_timing_level(struct edid *edid) 3670 { 3671 if (edid->revision >= 2) { 3672 if (edid->revision >= 4 && 3673 (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 3674 return LEVEL_CVT; 3675 if (drm_gtf2_hbreak(edid)) 3676 return LEVEL_GTF2; 3677 return LEVEL_GTF; 3678 } 3679 return LEVEL_DMT; 3680 } 3681 3682 /* 3683 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3684 * monitors fill with ascii space (0x20) instead. 3685 */ 3686 static int 3687 bad_std_timing(u8 a, u8 b) 3688 { 3689 return (a == 0x00 && b == 0x00) || 3690 (a == 0x01 && b == 0x01) || 3691 (a == 0x20 && b == 0x20); 3692 } 3693 3694 static void 3695 is_rb(struct detailed_timing *t, void *data) 3696 { 3697 u8 *r = (u8 *)t; 3698 3699 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 3700 if (r[15] & 0x10) 3701 *(bool *)data = true; 3702 } 3703 3704 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 3705 static bool 3706 drm_monitor_supports_rb(struct edid *edid) 3707 { 3708 if (edid->revision >= 4) { 3709 bool ret = false; 3710 3711 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 3712 return ret; 3713 } 3714 3715 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 3716 } 3717 3718 static bool 3719 mode_is_rb(const struct drm_display_mode *mode) 3720 { 3721 return (mode->htotal - mode->hdisplay == 160) && 3722 (mode->hsync_end - mode->hdisplay == 80) && 3723 (mode->hsync_end - mode->hsync_start == 32) && 3724 (mode->vsync_start - mode->vdisplay == 3); 3725 } 3726 3727 /* 3728 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 3729 * @hsize: Mode width 3730 * @vsize: Mode height 3731 * @fresh: Mode refresh rate 3732 * @rb: Mode reduced-blanking-ness 3733 * 3734 * Walk the DMT mode list looking for a match for the given parameters. 3735 * 3736 * Return: A newly allocated copy of the mode, or NULL if not found. 3737 */ 3738 static struct drm_display_mode *drm_mode_find_dmt( 3739 int hsize, int vsize, int fresh, 3740 bool rb) 3741 { 3742 int i; 3743 struct drm_display_mode *newmode; 3744 3745 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3746 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3747 3748 if (hsize != ptr->hdisplay) 3749 continue; 3750 if (vsize != ptr->vdisplay) 3751 continue; 3752 if (fresh != drm_get_vrefresh(ptr)) 3753 continue; 3754 if (rb != mode_is_rb(ptr)) 3755 continue; 3756 3757 newmode = drm_mode_create(); 3758 *newmode = *ptr; 3759 return newmode; 3760 } 3761 3762 return NULL; 3763 } 3764 3765 static struct drm_display_mode * 3766 drm_gtf_mode_complex(int hdisplay, int vdisplay, 3767 int vrefresh, bool interlaced, int margins, 3768 int GTF_M, int GTF_2C, int GTF_K, int GTF_2J) 3769 { /* 1) top/bottom margin size (% of height) - default: 1.8, */ 3770 #define GTF_MARGIN_PERCENTAGE 18 3771 /* 2) character cell horizontal granularity (pixels) - default 8 */ 3772 #define GTF_CELL_GRAN 8 3773 /* 3) Minimum vertical porch (lines) - default 3 */ 3774 #define GTF_MIN_V_PORCH 1 3775 /* width of vsync in lines */ 3776 #define V_SYNC_RQD 3 3777 /* width of hsync as % of total line */ 3778 #define H_SYNC_PERCENT 8 3779 /* min time of vsync + back porch (microsec) */ 3780 #define MIN_VSYNC_PLUS_BP 550 3781 /* C' and M' are part of the Blanking Duty Cycle computation */ 3782 #define GTF_C_PRIME ((((GTF_2C - GTF_2J) * GTF_K / 256) + GTF_2J) / 2) 3783 #define GTF_M_PRIME (GTF_K * GTF_M / 256) 3784 struct drm_display_mode *drm_mode; 3785 unsigned int hdisplay_rnd, vdisplay_rnd, vfieldrate_rqd; 3786 int top_margin, bottom_margin; 3787 int interlace; 3788 unsigned int hfreq_est; 3789 int vsync_plus_bp; 3790 unsigned int vtotal_lines; 3791 int left_margin, right_margin; 3792 unsigned int total_active_pixels, ideal_duty_cycle; 3793 unsigned int hblank, total_pixels, pixel_freq; 3794 int hsync, hfront_porch, vodd_front_porch_lines; 3795 unsigned int tmp1, tmp2; 3796 3797 drm_mode = drm_mode_create(); 3798 if (!drm_mode) 3799 return NULL; 3800 3801 /* 1. In order to give correct results, the number of horizontal 3802 * pixels requested is first processed to ensure that it is divisible 3803 * by the character size, by rounding it to the nearest character 3804 * cell boundary: 3805 */ 3806 hdisplay_rnd = (hdisplay + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 3807 hdisplay_rnd = hdisplay_rnd * GTF_CELL_GRAN; 3808 3809 /* 2. If interlace is requested, the number of vertical lines assumed 3810 * by the calculation must be halved, as the computation calculates 3811 * the number of vertical lines per field. 3812 */ 3813 if (interlaced) 3814 vdisplay_rnd = vdisplay / 2; 3815 else 3816 vdisplay_rnd = vdisplay; 3817 3818 /* 3. Find the frame rate required: */ 3819 if (interlaced) 3820 vfieldrate_rqd = vrefresh * 2; 3821 else 3822 vfieldrate_rqd = vrefresh; 3823 3824 /* 4. Find number of lines in Top margin: */ 3825 top_margin = 0; 3826 if (margins) 3827 top_margin = (vdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 3828 1000; 3829 /* 5. Find number of lines in bottom margin: */ 3830 bottom_margin = top_margin; 3831 3832 /* 6. If interlace is required, then set variable interlace: */ 3833 if (interlaced) 3834 interlace = 1; 3835 else 3836 interlace = 0; 3837 3838 /* 7. Estimate the Horizontal frequency */ 3839 { 3840 tmp1 = (1000000 - MIN_VSYNC_PLUS_BP * vfieldrate_rqd) / 500; 3841 tmp2 = (vdisplay_rnd + 2 * top_margin + GTF_MIN_V_PORCH) * 3842 2 + interlace; 3843 hfreq_est = (tmp2 * 1000 * vfieldrate_rqd) / tmp1; 3844 } 3845 3846 /* 8. Find the number of lines in V sync + back porch */ 3847 /* [V SYNC+BP] = RINT(([MIN VSYNC+BP] * hfreq_est / 1000000)) */ 3848 vsync_plus_bp = MIN_VSYNC_PLUS_BP * hfreq_est / 1000; 3849 vsync_plus_bp = (vsync_plus_bp + 500) / 1000; 3850 /* 9. Find the number of lines in V back porch alone: 3851 * vback_porch = vsync_plus_bp - V_SYNC_RQD; 3852 */ 3853 /* 10. Find the total number of lines in Vertical field period: */ 3854 vtotal_lines = vdisplay_rnd + top_margin + bottom_margin + 3855 vsync_plus_bp + GTF_MIN_V_PORCH; 3856 /* 11. Estimate the Vertical field frequency: 3857 * vfieldrate_est = hfreq_est / vtotal_lines; 3858 */ 3859 3860 /* 12. Find the actual horizontal period: 3861 * hperiod = 1000000 / (vfieldrate_rqd * vtotal_lines); 3862 */ 3863 /* 13. Find the actual Vertical field frequency: 3864 * vfield_rate = hfreq_est / vtotal_lines; 3865 */ 3866 /* 14. Find the Vertical frame frequency: 3867 * if (interlaced) 3868 * vframe_rate = vfield_rate / 2; 3869 * else 3870 * vframe_rate = vfield_rate; 3871 */ 3872 /* 15. Find number of pixels in left margin: */ 3873 if (margins) 3874 left_margin = (hdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 3875 1000; 3876 else 3877 left_margin = 0; 3878 3879 /* 16.Find number of pixels in right margin: */ 3880 right_margin = left_margin; 3881 /* 17.Find total number of active pixels in image and left and right */ 3882 total_active_pixels = hdisplay_rnd + left_margin + right_margin; 3883 /* 18.Find the ideal blanking duty cycle from blanking duty cycle */ 3884 ideal_duty_cycle = GTF_C_PRIME * 1000 - 3885 (GTF_M_PRIME * 1000000 / hfreq_est); 3886 /* 19.Find the number of pixels in the blanking time to the nearest 3887 * double character cell: 3888 */ 3889 hblank = total_active_pixels * ideal_duty_cycle / 3890 (100000 - ideal_duty_cycle); 3891 hblank = (hblank + GTF_CELL_GRAN) / (2 * GTF_CELL_GRAN); 3892 hblank = hblank * 2 * GTF_CELL_GRAN; 3893 /* 20.Find total number of pixels: */ 3894 total_pixels = total_active_pixels + hblank; 3895 /* 21.Find pixel clock frequency: */ 3896 pixel_freq = total_pixels * hfreq_est / 1000; 3897 /* Stage 1 computations are now complete; I should really pass 3898 * the results to another function and do the Stage 2 computations, 3899 * but I only need a few more values so I'll just append the 3900 * computations here for now 3901 */ 3902 3903 /* 17. Find the number of pixels in the horizontal sync period: */ 3904 hsync = H_SYNC_PERCENT * total_pixels / 100; 3905 hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 3906 hsync = hsync * GTF_CELL_GRAN; 3907 /* 18. Find the number of pixels in horizontal front porch period */ 3908 hfront_porch = hblank / 2 - hsync; 3909 /* 36. Find the number of lines in the odd front porch period: */ 3910 vodd_front_porch_lines = GTF_MIN_V_PORCH; 3911 3912 /* finally, pack the results in the mode struct */ 3913 drm_mode->hdisplay = hdisplay_rnd; 3914 drm_mode->hsync_start = hdisplay_rnd + hfront_porch; 3915 drm_mode->hsync_end = drm_mode->hsync_start + hsync; 3916 drm_mode->htotal = total_pixels; 3917 drm_mode->vdisplay = vdisplay_rnd; 3918 drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines; 3919 drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD; 3920 drm_mode->vtotal = vtotal_lines; 3921 3922 drm_mode->clock = pixel_freq; 3923 3924 if (interlaced) { 3925 drm_mode->vtotal *= 2; 3926 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 3927 } 3928 3929 if (GTF_M == 600 && GTF_2C == 80 && GTF_K == 128 && GTF_2J == 40) 3930 drm_mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC; 3931 else 3932 drm_mode->flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC; 3933 3934 return drm_mode; 3935 } 3936 3937 /** 3938 * drm_gtf_mode - create the mode based on the GTF algorithm 3939 * @hdisplay: hdisplay size 3940 * @vdisplay: vdisplay size 3941 * @vrefresh: vrefresh rate. 3942 * @interlaced: whether to compute an interlaced mode 3943 * @margins: desired margin (borders) size 3944 * 3945 * return the mode based on GTF algorithm 3946 * 3947 * This function is to create the mode based on the GTF algorithm. 3948 * Generalized Timing Formula is derived from: 3949 * GTF Spreadsheet by Andy Morrish (1/5/97) 3950 * available at http://www.vesa.org 3951 * 3952 * And it is copied from the file of xserver/hw/xfree86/modes/xf86gtf.c. 3953 * What I have done is to translate it by using integer calculation. 3954 * I also refer to the function of fb_get_mode in the file of 3955 * drivers/video/fbmon.c 3956 * 3957 * Standard GTF parameters: 3958 * M = 600 3959 * C = 40 3960 * K = 128 3961 * J = 20 3962 * 3963 * Returns: 3964 * The modeline based on the GTF algorithm stored in a drm_display_mode object. 3965 * The display mode object is allocated with drm_mode_create(). Returns NULL 3966 * when no mode could be allocated. 3967 */ 3968 static struct drm_display_mode * 3969 drm_gtf_mode(int hdisplay, int vdisplay, int vrefresh, 3970 bool interlaced, int margins) 3971 { 3972 return drm_gtf_mode_complex(hdisplay, vdisplay, vrefresh, 3973 interlaced, margins, 3974 600, 40 * 2, 128, 20 * 2); 3975 } 3976 3977 /** drm_mode_hsync - get the hsync of a mode 3978 * @mode: mode 3979 * 3980 * Returns: 3981 * @modes's hsync rate in kHz, rounded to the nearest integer. Calculates the 3982 * value first if it is not yet set. 3983 */ 3984 static int drm_mode_hsync(const struct drm_display_mode *mode) 3985 { 3986 unsigned int calc_val; 3987 3988 if (mode->htotal < 0) 3989 return 0; 3990 3991 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */ 3992 calc_val += 500; /* round to 1000Hz */ 3993 calc_val /= 1000; /* truncate to kHz */ 3994 3995 return calc_val; 3996 } 3997 3998 /** 3999 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 4000 * @data: the structure that save parsed hdmi edid data 4001 * @edid: EDID block to scan 4002 * @t: standard timing params 4003 * 4004 * Take the standard timing params (in this case width, aspect, and refresh) 4005 * and convert them into a real mode using CVT/GTF/DMT. 4006 */ 4007 static struct drm_display_mode * 4008 drm_mode_std(struct hdmi_edid_data *data, struct edid *edid, 4009 struct std_timing *t) 4010 { 4011 struct drm_display_mode *mode = NULL; 4012 int i, hsize, vsize; 4013 int vrefresh_rate; 4014 int num = data->modes; 4015 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 4016 >> EDID_TIMING_ASPECT_SHIFT; 4017 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 4018 >> EDID_TIMING_VFREQ_SHIFT; 4019 int timing_level = standard_timing_level(edid); 4020 4021 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 4022 return NULL; 4023 4024 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 4025 hsize = t->hsize * 8 + 248; 4026 /* vrefresh_rate = vfreq + 60 */ 4027 vrefresh_rate = vfreq + 60; 4028 /* the vdisplay is calculated based on the aspect ratio */ 4029 if (aspect_ratio == 0) { 4030 if (edid->revision < 3) 4031 vsize = hsize; 4032 else 4033 vsize = (hsize * 10) / 16; 4034 } else if (aspect_ratio == 1) { 4035 vsize = (hsize * 3) / 4; 4036 } else if (aspect_ratio == 2) { 4037 vsize = (hsize * 4) / 5; 4038 } else { 4039 vsize = (hsize * 9) / 16; 4040 } 4041 4042 /* HDTV hack, part 1 */ 4043 if (vrefresh_rate == 60 && 4044 ((hsize == 1360 && vsize == 765) || 4045 (hsize == 1368 && vsize == 769))) { 4046 hsize = 1366; 4047 vsize = 768; 4048 } 4049 4050 /* 4051 * If we already has a mode for this size and refresh 4052 * rate (because it came from detailed or CVT info), use that 4053 * instead. This way we don't have to guess at interlace or 4054 * reduced blanking. 4055 */ 4056 for (i = 0; i < num; i++) 4057 if (data->mode_buf[i].hdisplay == hsize && 4058 data->mode_buf[i].vdisplay == vsize && 4059 drm_get_vrefresh(&data->mode_buf[i]) == vrefresh_rate) 4060 return NULL; 4061 4062 /* HDTV hack, part 2 */ 4063 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 4064 mode = drm_cvt_mode(1366, 768, vrefresh_rate, 0, 0, 4065 false); 4066 mode->hdisplay = 1366; 4067 mode->hsync_start = mode->hsync_start - 1; 4068 mode->hsync_end = mode->hsync_end - 1; 4069 return mode; 4070 } 4071 4072 /* check whether it can be found in default mode table */ 4073 if (drm_monitor_supports_rb(edid)) { 4074 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, 4075 true); 4076 if (mode) 4077 return mode; 4078 } 4079 4080 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, false); 4081 if (mode) 4082 return mode; 4083 4084 /* okay, generate it */ 4085 switch (timing_level) { 4086 case LEVEL_DMT: 4087 break; 4088 case LEVEL_GTF: 4089 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4090 break; 4091 case LEVEL_GTF2: 4092 /* 4093 * This is potentially wrong if there's ever a monitor with 4094 * more than one ranges section, each claiming a different 4095 * secondary GTF curve. Please don't do that. 4096 */ 4097 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4098 if (!mode) 4099 return NULL; 4100 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 4101 drm_mode_destroy(mode); 4102 mode = drm_gtf_mode_complex(hsize, vsize, 4103 vrefresh_rate, 0, 0, 4104 drm_gtf2_m(edid), 4105 drm_gtf2_2c(edid), 4106 drm_gtf2_k(edid), 4107 drm_gtf2_2j(edid)); 4108 } 4109 break; 4110 case LEVEL_CVT: 4111 mode = drm_cvt_mode(hsize, vsize, vrefresh_rate, 0, 0, 4112 false); 4113 break; 4114 } 4115 4116 return mode; 4117 } 4118 4119 static void 4120 do_standard_modes(struct detailed_timing *timing, void *c) 4121 { 4122 struct detailed_mode_closure *closure = c; 4123 struct detailed_non_pixel *data = &timing->data.other_data; 4124 struct edid *edid = closure->edid; 4125 4126 if (data->type == EDID_DETAIL_STD_MODES) { 4127 int i; 4128 4129 for (i = 0; i < 6; i++) { 4130 struct std_timing *std; 4131 struct drm_display_mode *newmode; 4132 4133 std = &data->data.timings[i]; 4134 newmode = drm_mode_std(closure->data, edid, std); 4135 if (newmode) { 4136 drm_add_hdmi_modes(closure->data, newmode); 4137 closure->modes++; 4138 drm_mode_destroy(newmode); 4139 } 4140 } 4141 } 4142 } 4143 4144 /** 4145 * add_standard_modes - get std. modes from EDID and add them 4146 * @data: data to add mode(s) to 4147 * @edid: EDID block to scan 4148 * 4149 * Standard modes can be calculated using the appropriate standard (DMT, 4150 * GTF or CVT. Grab them from @edid and add them to the list. 4151 */ 4152 static int 4153 add_standard_modes(struct hdmi_edid_data *data, struct edid *edid) 4154 { 4155 int i, modes = 0; 4156 struct detailed_mode_closure closure = { 4157 .data = data, 4158 .edid = edid, 4159 }; 4160 4161 for (i = 0; i < EDID_STD_TIMINGS; i++) { 4162 struct drm_display_mode *newmode; 4163 4164 newmode = drm_mode_std(data, edid, 4165 &edid->standard_timings[i]); 4166 if (newmode) { 4167 drm_add_hdmi_modes(data, newmode); 4168 modes++; 4169 drm_mode_destroy(newmode); 4170 } 4171 } 4172 4173 if (version_greater(edid, 1, 0)) 4174 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 4175 &closure); 4176 4177 /* XXX should also look for standard codes in VTB blocks */ 4178 4179 return modes + closure.modes; 4180 } 4181 4182 static int 4183 drm_est3_modes(struct hdmi_edid_data *data, struct detailed_timing *timing) 4184 { 4185 int i, j, m, modes = 0; 4186 struct drm_display_mode *mode; 4187 u8 *est = ((u8 *)timing) + 6; 4188 4189 for (i = 0; i < 6; i++) { 4190 for (j = 7; j >= 0; j--) { 4191 m = (i * 8) + (7 - j); 4192 if (m >= ARRAY_SIZE(est3_modes)) 4193 break; 4194 if (est[i] & (1 << j)) { 4195 mode = drm_mode_find_dmt( 4196 est3_modes[m].w, 4197 est3_modes[m].h, 4198 est3_modes[m].r, 4199 est3_modes[m].rb); 4200 if (mode) { 4201 drm_add_hdmi_modes(data, mode); 4202 modes++; 4203 drm_mode_destroy(mode); 4204 } 4205 } 4206 } 4207 } 4208 4209 return modes; 4210 } 4211 4212 static void 4213 do_established_modes(struct detailed_timing *timing, void *c) 4214 { 4215 struct detailed_mode_closure *closure = c; 4216 struct detailed_non_pixel *data = &timing->data.other_data; 4217 4218 if (data->type == EDID_DETAIL_EST_TIMINGS) 4219 closure->modes += drm_est3_modes(closure->data, timing); 4220 } 4221 4222 /** 4223 * add_established_modes - get est. modes from EDID and add them 4224 * @data: data to add mode(s) to 4225 * @edid: EDID block to scan 4226 * 4227 * Each EDID block contains a bitmap of the supported "established modes" list 4228 * (defined above). Tease them out and add them to the modes list. 4229 */ 4230 static int 4231 add_established_modes(struct hdmi_edid_data *data, struct edid *edid) 4232 { 4233 unsigned long est_bits = edid->established_timings.t1 | 4234 (edid->established_timings.t2 << 8) | 4235 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 4236 int i, modes = 0; 4237 struct detailed_mode_closure closure = { 4238 .data = data, 4239 .edid = edid, 4240 }; 4241 4242 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 4243 if (est_bits & (1 << i)) { 4244 struct drm_display_mode *newmode = drm_mode_create(); 4245 *newmode = edid_est_modes[i]; 4246 if (newmode) { 4247 drm_add_hdmi_modes(data, newmode); 4248 modes++; 4249 drm_mode_destroy(newmode); 4250 } 4251 } 4252 } 4253 4254 if (version_greater(edid, 1, 0)) 4255 drm_for_each_detailed_block((u8 *)edid, 4256 do_established_modes, &closure); 4257 4258 return modes + closure.modes; 4259 } 4260 4261 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4262 { 4263 u8 vic; 4264 4265 if (!to_match->clock) 4266 return 0; 4267 4268 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4269 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4270 unsigned int clock1, clock2; 4271 4272 /* Make sure to also match alternate clocks */ 4273 clock1 = hdmi_mode->clock; 4274 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4275 4276 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4277 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4278 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 4279 return vic; 4280 } 4281 return 0; 4282 } 4283 4284 static int 4285 add_alternate_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 4286 { 4287 struct drm_display_mode *mode; 4288 int i, num, modes = 0; 4289 4290 /* Don't add CEA modes if the CEA extension block is missing */ 4291 if (!drm_find_cea_extension(edid)) 4292 return 0; 4293 4294 /* 4295 * Go through all probed modes and create a new mode 4296 * with the alternate clock for certain CEA modes. 4297 */ 4298 num = data->modes; 4299 4300 for (i = 0; i < num; i++) { 4301 const struct drm_display_mode *cea_mode = NULL; 4302 struct drm_display_mode *newmode; 4303 u8 vic; 4304 unsigned int clock1, clock2; 4305 4306 mode = &data->mode_buf[i]; 4307 vic = drm_match_cea_mode(mode); 4308 4309 if (drm_valid_cea_vic(vic)) { 4310 cea_mode = &edid_cea_modes[vic]; 4311 clock2 = cea_mode_alternate_clock(cea_mode); 4312 } else { 4313 vic = drm_match_hdmi_mode(mode); 4314 if (drm_valid_hdmi_vic(vic)) { 4315 cea_mode = &edid_4k_modes[vic]; 4316 clock2 = hdmi_mode_alternate_clock(cea_mode); 4317 } 4318 } 4319 4320 if (!cea_mode) 4321 continue; 4322 4323 clock1 = cea_mode->clock; 4324 4325 if (clock1 == clock2) 4326 continue; 4327 4328 if (mode->clock != clock1 && mode->clock != clock2) 4329 continue; 4330 4331 newmode = drm_mode_create(); 4332 *newmode = *cea_mode; 4333 if (!newmode) 4334 continue; 4335 4336 /* Carry over the stereo flags */ 4337 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4338 4339 /* 4340 * The current mode could be either variant. Make 4341 * sure to pick the "other" clock for the new mode. 4342 */ 4343 if (mode->clock != clock1) 4344 newmode->clock = clock1; 4345 else 4346 newmode->clock = clock2; 4347 4348 drm_add_hdmi_modes(data, newmode); 4349 modes++; 4350 drm_mode_destroy(newmode); 4351 } 4352 4353 return modes; 4354 } 4355 4356 static u8 *drm_find_displayid_extension(struct edid *edid) 4357 { 4358 return drm_find_edid_extension(edid, DISPLAYID_EXT); 4359 } 4360 4361 static int validate_displayid(u8 *displayid, int length, int idx) 4362 { 4363 int i; 4364 u8 csum = 0; 4365 struct displayid_hdr *base; 4366 4367 base = (struct displayid_hdr *)&displayid[idx]; 4368 4369 debug("base revision 0x%x, length %d, %d %d\n", 4370 base->rev, base->bytes, base->prod_id, base->ext_count); 4371 4372 if (base->bytes + 5 > length - idx) 4373 return -EINVAL; 4374 for (i = idx; i <= base->bytes + 5; i++) 4375 csum += displayid[i]; 4376 if (csum) { 4377 debug("DisplayID checksum invalid, remainder is %d\n", csum); 4378 return -EINVAL; 4379 } 4380 return 0; 4381 } 4382 4383 static struct 4384 drm_display_mode *drm_displayid_detailed(struct displayid_detailed_timings_1 4385 *timings) 4386 { 4387 struct drm_display_mode *mode; 4388 unsigned pixel_clock = (timings->pixel_clock[0] | 4389 (timings->pixel_clock[1] << 8) | 4390 (timings->pixel_clock[2] << 16)); 4391 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4392 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4393 unsigned hsync = (timings->hsync[0] | 4394 (timings->hsync[1] & 0x7f) << 8) + 1; 4395 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4396 unsigned vactive = (timings->vactive[0] | 4397 timings->vactive[1] << 8) + 1; 4398 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4399 unsigned vsync = (timings->vsync[0] | 4400 (timings->vsync[1] & 0x7f) << 8) + 1; 4401 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4402 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4403 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4404 4405 mode = drm_mode_create(); 4406 if (!mode) 4407 return NULL; 4408 4409 mode->clock = pixel_clock * 10; 4410 mode->hdisplay = hactive; 4411 mode->hsync_start = mode->hdisplay + hsync; 4412 mode->hsync_end = mode->hsync_start + hsync_width; 4413 mode->htotal = mode->hdisplay + hblank; 4414 4415 mode->vdisplay = vactive; 4416 mode->vsync_start = mode->vdisplay + vsync; 4417 mode->vsync_end = mode->vsync_start + vsync_width; 4418 mode->vtotal = mode->vdisplay + vblank; 4419 4420 mode->flags = 0; 4421 mode->flags |= 4422 hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4423 mode->flags |= 4424 vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4425 mode->type = DRM_MODE_TYPE_DRIVER; 4426 4427 if (timings->flags & 0x80) 4428 mode->type |= DRM_MODE_TYPE_PREFERRED; 4429 mode->vrefresh = drm_get_vrefresh(mode); 4430 4431 return mode; 4432 } 4433 4434 static int add_displayid_detailed_1_modes(struct hdmi_edid_data *data, 4435 struct displayid_block *block) 4436 { 4437 struct displayid_detailed_timing_block *det; 4438 int i; 4439 int num_timings; 4440 struct drm_display_mode *newmode; 4441 int num_modes = 0; 4442 4443 det = (struct displayid_detailed_timing_block *)block; 4444 /* blocks must be multiple of 20 bytes length */ 4445 if (block->num_bytes % 20) 4446 return 0; 4447 4448 num_timings = block->num_bytes / 20; 4449 for (i = 0; i < num_timings; i++) { 4450 struct displayid_detailed_timings_1 *timings = 4451 &det->timings[i]; 4452 4453 newmode = drm_displayid_detailed(timings); 4454 if (!newmode) 4455 continue; 4456 4457 drm_add_hdmi_modes(data, newmode); 4458 num_modes++; 4459 drm_mode_destroy(newmode); 4460 } 4461 return num_modes; 4462 } 4463 4464 static int add_displayid_detailed_modes(struct hdmi_edid_data *data, 4465 struct edid *edid) 4466 { 4467 u8 *displayid; 4468 int ret; 4469 int idx = 1; 4470 int length = EDID_SIZE; 4471 struct displayid_block *block; 4472 int num_modes = 0; 4473 4474 displayid = drm_find_displayid_extension(edid); 4475 if (!displayid) 4476 return 0; 4477 4478 ret = validate_displayid(displayid, length, idx); 4479 if (ret) 4480 return 0; 4481 4482 idx += sizeof(struct displayid_hdr); 4483 while (block = (struct displayid_block *)&displayid[idx], 4484 idx + sizeof(struct displayid_block) <= length && 4485 idx + sizeof(struct displayid_block) + block->num_bytes <= 4486 length && block->num_bytes > 0) { 4487 idx += block->num_bytes + sizeof(struct displayid_block); 4488 switch (block->tag) { 4489 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4490 num_modes += 4491 add_displayid_detailed_1_modes(data, block); 4492 break; 4493 } 4494 } 4495 return num_modes; 4496 } 4497 4498 static bool 4499 mode_in_hsync_range(const struct drm_display_mode *mode, 4500 struct edid *edid, u8 *t) 4501 { 4502 int hsync, hmin, hmax; 4503 4504 hmin = t[7]; 4505 if (edid->revision >= 4) 4506 hmin += ((t[4] & 0x04) ? 255 : 0); 4507 hmax = t[8]; 4508 if (edid->revision >= 4) 4509 hmax += ((t[4] & 0x08) ? 255 : 0); 4510 hsync = drm_mode_hsync(mode); 4511 4512 return (hsync <= hmax && hsync >= hmin); 4513 } 4514 4515 static bool 4516 mode_in_vsync_range(const struct drm_display_mode *mode, 4517 struct edid *edid, u8 *t) 4518 { 4519 int vsync, vmin, vmax; 4520 4521 vmin = t[5]; 4522 if (edid->revision >= 4) 4523 vmin += ((t[4] & 0x01) ? 255 : 0); 4524 vmax = t[6]; 4525 if (edid->revision >= 4) 4526 vmax += ((t[4] & 0x02) ? 255 : 0); 4527 vsync = drm_get_vrefresh(mode); 4528 4529 return (vsync <= vmax && vsync >= vmin); 4530 } 4531 4532 static u32 4533 range_pixel_clock(struct edid *edid, u8 *t) 4534 { 4535 /* unspecified */ 4536 if (t[9] == 0 || t[9] == 255) 4537 return 0; 4538 4539 /* 1.4 with CVT support gives us real precision, yay */ 4540 if (edid->revision >= 4 && t[10] == 0x04) 4541 return (t[9] * 10000) - ((t[12] >> 2) * 250); 4542 4543 /* 1.3 is pathetic, so fuzz up a bit */ 4544 return t[9] * 10000 + 5001; 4545 } 4546 4547 static bool 4548 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 4549 struct detailed_timing *timing) 4550 { 4551 u32 max_clock; 4552 u8 *t = (u8 *)timing; 4553 4554 if (!mode_in_hsync_range(mode, edid, t)) 4555 return false; 4556 4557 if (!mode_in_vsync_range(mode, edid, t)) 4558 return false; 4559 4560 max_clock = range_pixel_clock(edid, t); 4561 if (max_clock) 4562 if (mode->clock > max_clock) 4563 return false; 4564 4565 /* 1.4 max horizontal check */ 4566 if (edid->revision >= 4 && t[10] == 0x04) 4567 if (t[13] && mode->hdisplay > 8 * 4568 (t[13] + (256 * (t[12] & 0x3)))) 4569 return false; 4570 4571 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 4572 return false; 4573 4574 return true; 4575 } 4576 4577 static bool valid_inferred_mode(struct hdmi_edid_data *data, 4578 const struct drm_display_mode *mode) 4579 { 4580 const struct drm_display_mode *m; 4581 bool ok = false; 4582 int i; 4583 4584 for (i = 0; i < data->modes; i++) { 4585 m = &data->mode_buf[i]; 4586 if (mode->hdisplay == m->hdisplay && 4587 mode->vdisplay == m->vdisplay && 4588 drm_get_vrefresh(mode) == drm_get_vrefresh(m)) 4589 return false; /* duplicated */ 4590 if (mode->hdisplay <= m->hdisplay && 4591 mode->vdisplay <= m->vdisplay) 4592 ok = true; 4593 } 4594 return ok; 4595 } 4596 4597 static int 4598 drm_dmt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 4599 struct detailed_timing *timing) 4600 { 4601 int i, modes = 0; 4602 4603 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 4604 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 4605 valid_inferred_mode(data, drm_dmt_modes + i)) { 4606 drm_add_hdmi_modes(data, &drm_dmt_modes[i]); 4607 modes++; 4608 } 4609 } 4610 4611 return modes; 4612 } 4613 4614 /* fix up 1366x768 mode from 1368x768; 4615 * GFT/CVT can't express 1366 width which isn't dividable by 8 4616 */ 4617 static void fixup_mode_1366x768(struct drm_display_mode *mode) 4618 { 4619 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 4620 mode->hdisplay = 1366; 4621 mode->hsync_start--; 4622 mode->hsync_end--; 4623 } 4624 } 4625 4626 static int 4627 drm_gtf_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 4628 struct detailed_timing *timing) 4629 { 4630 int i, modes = 0; 4631 struct drm_display_mode *newmode; 4632 4633 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 4634 const struct minimode *m = &extra_modes[i]; 4635 4636 newmode = drm_gtf_mode(m->w, m->h, m->r, 0, 0); 4637 if (!newmode) 4638 return modes; 4639 4640 fixup_mode_1366x768(newmode); 4641 if (!mode_in_range(newmode, edid, timing) || 4642 !valid_inferred_mode(data, newmode)) { 4643 drm_mode_destroy(newmode); 4644 continue; 4645 } 4646 4647 drm_add_hdmi_modes(data, newmode); 4648 modes++; 4649 drm_mode_destroy(newmode); 4650 } 4651 4652 return modes; 4653 } 4654 4655 static int 4656 drm_cvt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 4657 struct detailed_timing *timing) 4658 { 4659 int i, modes = 0; 4660 struct drm_display_mode *newmode; 4661 bool rb = drm_monitor_supports_rb(edid); 4662 4663 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 4664 const struct minimode *m = &extra_modes[i]; 4665 4666 newmode = drm_cvt_mode(m->w, m->h, m->r, rb, 0, 0); 4667 if (!newmode) 4668 return modes; 4669 4670 fixup_mode_1366x768(newmode); 4671 if (!mode_in_range(newmode, edid, timing) || 4672 !valid_inferred_mode(data, newmode)) { 4673 drm_mode_destroy(newmode); 4674 continue; 4675 } 4676 4677 drm_add_hdmi_modes(data, newmode); 4678 modes++; 4679 drm_mode_destroy(newmode); 4680 } 4681 4682 return modes; 4683 } 4684 4685 static void 4686 do_inferred_modes(struct detailed_timing *timing, void *c) 4687 { 4688 struct detailed_mode_closure *closure = c; 4689 struct detailed_non_pixel *data = &timing->data.other_data; 4690 struct detailed_data_monitor_range *range = &data->data.range; 4691 4692 if (data->type != EDID_DETAIL_MONITOR_RANGE) 4693 return; 4694 4695 closure->modes += drm_dmt_modes_for_range(closure->data, 4696 closure->edid, 4697 timing); 4698 4699 if (!version_greater(closure->edid, 1, 1)) 4700 return; /* GTF not defined yet */ 4701 4702 switch (range->flags) { 4703 case 0x02: /* secondary gtf, XXX could do more */ 4704 case 0x00: /* default gtf */ 4705 closure->modes += drm_gtf_modes_for_range(closure->data, 4706 closure->edid, 4707 timing); 4708 break; 4709 case 0x04: /* cvt, only in 1.4+ */ 4710 if (!version_greater(closure->edid, 1, 3)) 4711 break; 4712 4713 closure->modes += drm_cvt_modes_for_range(closure->data, 4714 closure->edid, 4715 timing); 4716 break; 4717 case 0x01: /* just the ranges, no formula */ 4718 default: 4719 break; 4720 } 4721 } 4722 4723 static int 4724 add_inferred_modes(struct hdmi_edid_data *data, struct edid *edid) 4725 { 4726 struct detailed_mode_closure closure = { 4727 .data = data, 4728 .edid = edid, 4729 }; 4730 4731 if (version_greater(edid, 1, 0)) 4732 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 4733 &closure); 4734 4735 return closure.modes; 4736 } 4737 4738 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 4739 #define MODE_REFRESH_DIFF(c, t) (abs((c) - (t))) 4740 4741 /** 4742 * edid_fixup_preferred - set preferred modes based on quirk list 4743 * @data: the structure that save parsed hdmi edid data 4744 * @quirks: quirks list 4745 * 4746 * Walk the mode list, clearing the preferred status 4747 * on existing modes and setting it anew for the right mode ala @quirks. 4748 */ 4749 static void edid_fixup_preferred(struct hdmi_edid_data *data, 4750 u32 quirks) 4751 { 4752 struct drm_display_mode *cur_mode, *preferred_mode; 4753 int i, target_refresh = 0; 4754 int num = data->modes; 4755 int cur_vrefresh, preferred_vrefresh; 4756 4757 if (!num) 4758 return; 4759 4760 preferred_mode = data->preferred_mode; 4761 4762 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 4763 target_refresh = 60; 4764 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 4765 target_refresh = 75; 4766 4767 for (i = 0; i < num; i++) { 4768 cur_mode = &data->mode_buf[i]; 4769 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 4770 4771 if (cur_mode == preferred_mode) 4772 continue; 4773 4774 /* Largest mode is preferred */ 4775 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 4776 preferred_mode = cur_mode; 4777 4778 cur_vrefresh = cur_mode->vrefresh ? 4779 cur_mode->vrefresh : drm_get_vrefresh(cur_mode); 4780 preferred_vrefresh = preferred_mode->vrefresh ? 4781 preferred_mode->vrefresh : drm_get_vrefresh(preferred_mode); 4782 /* At a given size, try to get closest to target refresh */ 4783 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 4784 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 4785 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 4786 preferred_mode = cur_mode; 4787 } 4788 } 4789 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 4790 data->preferred_mode = preferred_mode; 4791 } 4792 4793 static const u8 edid_header[] = { 4794 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 4795 }; 4796 4797 /** 4798 * drm_edid_header_is_valid - sanity check the header of the base EDID block 4799 * @raw_edid: pointer to raw base EDID block 4800 * 4801 * Sanity check the header of the base EDID block. 4802 * 4803 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 4804 */ 4805 static int drm_edid_header_is_valid(const u8 *raw_edid) 4806 { 4807 int i, score = 0; 4808 4809 for (i = 0; i < sizeof(edid_header); i++) 4810 if (raw_edid[i] == edid_header[i]) 4811 score++; 4812 4813 return score; 4814 } 4815 4816 static int drm_edid_block_checksum(const u8 *raw_edid) 4817 { 4818 int i; 4819 u8 csum = 0; 4820 4821 for (i = 0; i < EDID_SIZE; i++) 4822 csum += raw_edid[i]; 4823 4824 return csum; 4825 } 4826 4827 static bool drm_edid_is_zero(const u8 *in_edid, int length) 4828 { 4829 if (memchr_inv(in_edid, 0, length)) 4830 return false; 4831 4832 return true; 4833 } 4834 4835 /** 4836 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 4837 * @raw_edid: pointer to raw EDID block 4838 * @block: type of block to validate (0 for base, extension otherwise) 4839 * @print_bad_edid: if true, dump bad EDID blocks to the console 4840 * @edid_corrupt: if true, the header or checksum is invalid 4841 * 4842 * Validate a base or extension EDID block and optionally dump bad blocks to 4843 * the console. 4844 * 4845 * Return: True if the block is valid, false otherwise. 4846 */ 4847 static 4848 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 4849 bool *edid_corrupt) 4850 { 4851 u8 csum; 4852 int edid_fixup = 6; 4853 struct edid *edid = (struct edid *)raw_edid; 4854 4855 if ((!raw_edid)) 4856 return false; 4857 4858 if (block == 0) { 4859 int score = drm_edid_header_is_valid(raw_edid); 4860 4861 if (score == 8) { 4862 if (edid_corrupt) 4863 *edid_corrupt = false; 4864 } else if (score >= edid_fixup) { 4865 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 4866 * The corrupt flag needs to be set here otherwise, the 4867 * fix-up code here will correct the problem, the 4868 * checksum is correct and the test fails 4869 */ 4870 if (edid_corrupt) 4871 *edid_corrupt = true; 4872 debug("Fixing header, your hardware may be failing\n"); 4873 memcpy(raw_edid, edid_header, sizeof(edid_header)); 4874 } else { 4875 if (edid_corrupt) 4876 *edid_corrupt = true; 4877 goto bad; 4878 } 4879 } 4880 4881 csum = drm_edid_block_checksum(raw_edid); 4882 if (csum) { 4883 if (print_bad_edid) { 4884 debug("EDID checksum is invalid, remainder is %d\n", 4885 csum); 4886 } 4887 4888 if (edid_corrupt) 4889 *edid_corrupt = true; 4890 4891 /* allow CEA to slide through, switches mangle this */ 4892 if (raw_edid[0] != 0x02) 4893 goto bad; 4894 } 4895 4896 /* per-block-type checks */ 4897 switch (raw_edid[0]) { 4898 case 0: /* base */ 4899 if (edid->version != 1) { 4900 debug("EDID has major version %d, instead of 1\n", 4901 edid->version); 4902 goto bad; 4903 } 4904 4905 if (edid->revision > 4) 4906 debug("minor > 4, assuming backward compatibility\n"); 4907 break; 4908 4909 default: 4910 break; 4911 } 4912 4913 return true; 4914 4915 bad: 4916 if (print_bad_edid) { 4917 if (drm_edid_is_zero(raw_edid, EDID_SIZE)) { 4918 debug("EDID block is all zeroes\n"); 4919 } else { 4920 debug("Raw EDID:\n"); 4921 print_hex_dump("", DUMP_PREFIX_NONE, 16, 1, 4922 raw_edid, EDID_SIZE, false); 4923 } 4924 } 4925 return false; 4926 } 4927 4928 /** 4929 * drm_edid_is_valid - sanity check EDID data 4930 * @edid: EDID data 4931 * 4932 * Sanity-check an entire EDID record (including extensions) 4933 * 4934 * Return: True if the EDID data is valid, false otherwise. 4935 */ 4936 static bool drm_edid_is_valid(struct edid *edid) 4937 { 4938 int i; 4939 u8 *raw = (u8 *)edid; 4940 4941 if (!edid) 4942 return false; 4943 4944 for (i = 0; i <= edid->extensions; i++) 4945 if (!drm_edid_block_valid(raw + i * EDID_SIZE, i, true, NULL)) 4946 return false; 4947 4948 return true; 4949 } 4950 4951 /** 4952 * drm_add_edid_modes - add modes from EDID data, if available 4953 * @data: data we're probing 4954 * @edid: EDID data 4955 * 4956 * Add the specified modes to the data's mode list. 4957 * 4958 * Return: The number of modes added or 0 if we couldn't find any. 4959 */ 4960 int drm_add_edid_modes(struct hdmi_edid_data *data, u8 *raw_edid) 4961 { 4962 int num_modes = 0; 4963 u32 quirks; 4964 struct edid *edid = (struct edid *)raw_edid; 4965 4966 if (!edid) { 4967 debug("no edid\n"); 4968 return 0; 4969 } 4970 4971 if (!drm_edid_is_valid(edid)) { 4972 debug("EDID invalid\n"); 4973 return 0; 4974 } 4975 4976 if (!data->mode_buf) { 4977 debug("mode buff is null\n"); 4978 return 0; 4979 } 4980 4981 quirks = edid_get_quirks(edid); 4982 /* 4983 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 4984 * To avoid multiple parsing of same block, lets parse that map 4985 * from sink info, before parsing CEA modes. 4986 */ 4987 drm_add_display_info(data, edid); 4988 4989 /* 4990 * EDID spec says modes should be preferred in this order: 4991 * - preferred detailed mode 4992 * - other detailed modes from base block 4993 * - detailed modes from extension blocks 4994 * - CVT 3-byte code modes 4995 * - standard timing codes 4996 * - established timing codes 4997 * - modes inferred from GTF or CVT range information 4998 * 4999 * We get this pretty much right. 5000 * 5001 * XXX order for additional mode types in extension blocks? 5002 */ 5003 num_modes += add_detailed_modes(data, edid, quirks); 5004 num_modes += add_cvt_modes(data, edid); 5005 num_modes += add_standard_modes(data, edid); 5006 num_modes += add_established_modes(data, edid); 5007 num_modes += add_cea_modes(data, edid); 5008 num_modes += add_alternate_cea_modes(data, edid); 5009 num_modes += add_displayid_detailed_modes(data, edid); 5010 5011 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5012 num_modes += add_inferred_modes(data, edid); 5013 5014 if (num_modes > 0) 5015 data->preferred_mode = &data->mode_buf[0]; 5016 5017 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5018 edid_fixup_preferred(data, quirks); 5019 5020 if (quirks & EDID_QUIRK_FORCE_6BPC) 5021 data->display_info.bpc = 6; 5022 5023 if (quirks & EDID_QUIRK_FORCE_8BPC) 5024 data->display_info.bpc = 8; 5025 5026 if (quirks & EDID_QUIRK_FORCE_10BPC) 5027 data->display_info.bpc = 10; 5028 5029 if (quirks & EDID_QUIRK_FORCE_12BPC) 5030 data->display_info.bpc = 12; 5031 5032 return num_modes; 5033 } 5034 5035 static int hdmi_avi_infoframe_init(struct hdmi_avi_infoframe *frame) 5036 { 5037 memset(frame, 0, sizeof(*frame)); 5038 5039 frame->type = HDMI_INFOFRAME_TYPE_AVI; 5040 frame->version = 2; 5041 frame->length = HDMI_AVI_INFOFRAME_SIZE; 5042 5043 return 0; 5044 } 5045 5046 u8 drm_match_cea_mode(struct drm_display_mode *to_match) 5047 { 5048 u8 vic; 5049 5050 if (!to_match->clock) { 5051 printf("can't find to match\n"); 5052 return 0; 5053 } 5054 5055 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 5056 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 5057 unsigned int clock1, clock2; 5058 5059 /* Check both 60Hz and 59.94Hz */ 5060 clock1 = cea_mode->clock; 5061 clock2 = cea_mode_alternate_clock(cea_mode); 5062 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 5063 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 5064 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 5065 return vic; 5066 } 5067 5068 return 0; 5069 } 5070 5071 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 5072 { 5073 return edid_cea_modes[video_code].picture_aspect_ratio; 5074 } 5075 5076 int 5077 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5078 struct drm_display_mode *mode, 5079 bool is_hdmi2_sink) 5080 { 5081 int err; 5082 5083 if (!frame || !mode) 5084 return -EINVAL; 5085 5086 err = hdmi_avi_infoframe_init(frame); 5087 if (err < 0) 5088 return err; 5089 5090 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5091 frame->pixel_repeat = 1; 5092 5093 frame->video_code = drm_match_cea_mode(mode); 5094 5095 /* 5096 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5097 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5098 * have to make sure we dont break HDMI 1.4 sinks. 5099 */ 5100 if (!is_hdmi2_sink && frame->video_code > 64) 5101 frame->video_code = 0; 5102 5103 /* 5104 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5105 * we should send its VIC in vendor infoframes, else send the 5106 * VIC in AVI infoframes. Lets check if this mode is present in 5107 * HDMI 1.4b 4K modes 5108 */ 5109 if (frame->video_code) { 5110 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 5111 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 5112 5113 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 5114 frame->video_code = 0; 5115 } 5116 5117 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5118 5119 /* 5120 * Populate picture aspect ratio from either 5121 * user input (if specified) or from the CEA mode list. 5122 */ 5123 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 5124 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 5125 frame->picture_aspect = mode->picture_aspect_ratio; 5126 else if (frame->video_code > 0) 5127 frame->picture_aspect = drm_get_cea_aspect_ratio( 5128 frame->video_code); 5129 5130 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5131 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5132 5133 return 0; 5134 } 5135 5136 /** 5137 * hdmi_vendor_infoframe_init() - initialize an HDMI vendor infoframe 5138 * @frame: HDMI vendor infoframe 5139 * 5140 * Returns 0 on success or a negative error code on failure. 5141 */ 5142 static int hdmi_vendor_infoframe_init(struct hdmi_vendor_infoframe *frame) 5143 { 5144 memset(frame, 0, sizeof(*frame)); 5145 5146 frame->type = HDMI_INFOFRAME_TYPE_VENDOR; 5147 frame->version = 1; 5148 5149 frame->oui = HDMI_IEEE_OUI; 5150 5151 /* 5152 * 0 is a valid value for s3d_struct, so we use a special "not set" 5153 * value 5154 */ 5155 frame->s3d_struct = HDMI_3D_STRUCTURE_INVALID; 5156 5157 return 0; 5158 } 5159 5160 static enum hdmi_3d_structure 5161 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5162 { 5163 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5164 5165 switch (layout) { 5166 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5167 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5168 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5169 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5170 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5171 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5172 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5173 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5174 case DRM_MODE_FLAG_3D_L_DEPTH: 5175 return HDMI_3D_STRUCTURE_L_DEPTH; 5176 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5177 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5178 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5179 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5180 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5181 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5182 default: 5183 return HDMI_3D_STRUCTURE_INVALID; 5184 } 5185 } 5186 5187 int 5188 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5189 struct drm_display_mode *mode) 5190 { 5191 int err; 5192 u32 s3d_flags; 5193 u8 vic; 5194 5195 if (!frame || !mode) 5196 return -EINVAL; 5197 5198 vic = drm_match_hdmi_mode(mode); 5199 5200 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 5201 5202 if (!vic && !s3d_flags) 5203 return -EINVAL; 5204 5205 if (vic && s3d_flags) 5206 return -EINVAL; 5207 5208 err = hdmi_vendor_infoframe_init(frame); 5209 if (err < 0) 5210 return err; 5211 5212 if (vic) 5213 frame->vic = vic; 5214 else 5215 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5216 5217 return 0; 5218 } 5219 5220 static u8 hdmi_infoframe_checksum(u8 *ptr, size_t size) 5221 { 5222 u8 csum = 0; 5223 size_t i; 5224 5225 /* compute checksum */ 5226 for (i = 0; i < size; i++) 5227 csum += ptr[i]; 5228 5229 return 256 - csum; 5230 } 5231 5232 static void hdmi_infoframe_set_checksum(void *buffer, size_t size) 5233 { 5234 u8 *ptr = buffer; 5235 5236 ptr[3] = hdmi_infoframe_checksum(buffer, size); 5237 } 5238 5239 /** 5240 * hdmi_vendor_infoframe_pack() - write a HDMI vendor infoframe to binary buffer 5241 * @frame: HDMI infoframe 5242 * @buffer: destination buffer 5243 * @size: size of buffer 5244 * 5245 * Packs the information contained in the @frame structure into a binary 5246 * representation that can be written into the corresponding controller 5247 * registers. Also computes the checksum as required by section 5.3.5 of 5248 * the HDMI 1.4 specification. 5249 * 5250 * Returns the number of bytes packed into the binary buffer or a negative 5251 * error code on failure. 5252 */ 5253 ssize_t hdmi_vendor_infoframe_pack(struct hdmi_vendor_infoframe *frame, 5254 void *buffer, size_t size) 5255 { 5256 u8 *ptr = buffer; 5257 size_t length; 5258 5259 /* empty info frame */ 5260 if (frame->vic == 0 && frame->s3d_struct == HDMI_3D_STRUCTURE_INVALID) 5261 return -EINVAL; 5262 5263 /* only one of those can be supplied */ 5264 if (frame->vic != 0 && frame->s3d_struct != HDMI_3D_STRUCTURE_INVALID) 5265 return -EINVAL; 5266 5267 /* for side by side (half) we also need to provide 3D_Ext_Data */ 5268 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 5269 frame->length = 6; 5270 else 5271 frame->length = 5; 5272 5273 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5274 5275 if (size < length) 5276 return -ENOSPC; 5277 5278 memset(buffer, 0, size); 5279 5280 ptr[0] = frame->type; 5281 ptr[1] = frame->version; 5282 ptr[2] = frame->length; 5283 ptr[3] = 0; /* checksum */ 5284 5285 /* HDMI OUI */ 5286 ptr[4] = 0x03; 5287 ptr[5] = 0x0c; 5288 ptr[6] = 0x00; 5289 5290 if (frame->vic) { 5291 ptr[7] = 0x1 << 5; /* video format */ 5292 ptr[8] = frame->vic; 5293 } else { 5294 ptr[7] = 0x2 << 5; /* video format */ 5295 ptr[8] = (frame->s3d_struct & 0xf) << 4; 5296 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 5297 ptr[9] = (frame->s3d_ext_data & 0xf) << 4; 5298 } 5299 5300 hdmi_infoframe_set_checksum(buffer, length); 5301 5302 return length; 5303 } 5304 5305 /** 5306 * drm_do_probe_ddc_edid() - get EDID information via I2C 5307 * @adap: ddc adapter 5308 * @buf: EDID data buffer to be filled 5309 * @block: 128 byte EDID block to start fetching from 5310 * @len: EDID data buffer length to fetch 5311 * 5312 * Try to fetch EDID information by calling I2C driver functions. 5313 * 5314 * Return: 0 on success or -1 on failure. 5315 */ 5316 static int 5317 drm_do_probe_ddc_edid(struct ddc_adapter *adap, u8 *buf, unsigned int block, 5318 size_t len) 5319 { 5320 unsigned char start = block * HDMI_EDID_BLOCK_SIZE; 5321 unsigned char segment = block >> 1; 5322 unsigned char xfers = segment ? 3 : 2; 5323 int ret, retries = 5; 5324 5325 do { 5326 struct i2c_msg msgs[] = { 5327 { 5328 .addr = DDC_SEGMENT_ADDR, 5329 .flags = 0, 5330 .len = 1, 5331 .buf = &segment, 5332 }, { 5333 .addr = DDC_ADDR, 5334 .flags = 0, 5335 .len = 1, 5336 .buf = &start, 5337 }, { 5338 .addr = DDC_ADDR, 5339 .flags = I2C_M_RD, 5340 .len = len, 5341 .buf = buf, 5342 } 5343 }; 5344 5345 ret = adap->ddc_xfer(adap, &msgs[3 - xfers], xfers); 5346 5347 } while (ret != xfers && --retries); 5348 5349 /* All msg transfer successfully. */ 5350 return ret == xfers ? 0 : -1; 5351 } 5352 5353 int drm_do_get_edid(struct ddc_adapter *adap, u8 *edid) 5354 { 5355 int i, j, block_num, block = 0; 5356 bool edid_corrupt; 5357 #ifdef DEBUG 5358 u8 *buff; 5359 #endif 5360 5361 /* base block fetch */ 5362 for (i = 0; i < 4; i++) { 5363 if (drm_do_probe_ddc_edid(adap, edid, 0, HDMI_EDID_BLOCK_SIZE)) 5364 goto err; 5365 if (drm_edid_block_valid(edid, 0, true, 5366 &edid_corrupt)) 5367 break; 5368 if (i == 0 && drm_edid_is_zero(edid, HDMI_EDID_BLOCK_SIZE)) { 5369 printf("edid base block is 0, get edid failed\n"); 5370 goto err; 5371 } 5372 } 5373 5374 if (i == 4) 5375 goto err; 5376 5377 block++; 5378 /* get the number of extensions */ 5379 block_num = edid[0x7e]; 5380 5381 for (j = 1; j <= block_num; j++) { 5382 for (i = 0; i < 4; i++) { 5383 if (drm_do_probe_ddc_edid(adap, &edid[0x80 * j], j, 5384 HDMI_EDID_BLOCK_SIZE)) 5385 goto err; 5386 if (drm_edid_block_valid(&edid[0x80 * j], j, 5387 true, NULL)) 5388 break; 5389 } 5390 5391 if (i == 4) 5392 goto err; 5393 block++; 5394 } 5395 5396 #ifdef DEBUG 5397 printf("RAW EDID:\n"); 5398 for (i = 0; i < block_num + 1; i++) { 5399 buff = &edid[0x80 * i]; 5400 for (j = 0; j < HDMI_EDID_BLOCK_SIZE; j++) { 5401 if (j % 16 == 0) 5402 printf("\n"); 5403 printf("0x%02x, ", buff[j]); 5404 } 5405 printf("\n"); 5406 } 5407 #endif 5408 5409 return 0; 5410 5411 err: 5412 printf("can't get edid block:%d\n", block); 5413 /* clear all read edid block, include invalid block */ 5414 memset(edid, 0, HDMI_EDID_BLOCK_SIZE * (block + 1)); 5415 return -EFAULT; 5416 } 5417 5418 static ssize_t hdmi_ddc_read(struct ddc_adapter *adap, u16 addr, u8 offset, 5419 void *buffer, size_t size) 5420 { 5421 struct i2c_msg msgs[2] = { 5422 { 5423 .addr = addr, 5424 .flags = 0, 5425 .len = 1, 5426 .buf = &offset, 5427 }, { 5428 .addr = addr, 5429 .flags = I2C_M_RD, 5430 .len = size, 5431 .buf = buffer, 5432 } 5433 }; 5434 5435 return adap->ddc_xfer(adap, msgs, ARRAY_SIZE(msgs)); 5436 } 5437 5438 static ssize_t hdmi_ddc_write(struct ddc_adapter *adap, u16 addr, u8 offset, 5439 const void *buffer, size_t size) 5440 { 5441 struct i2c_msg msg = { 5442 .addr = addr, 5443 .flags = 0, 5444 .len = 1 + size, 5445 .buf = NULL, 5446 }; 5447 void *data; 5448 int err; 5449 5450 data = malloc(1 + size); 5451 if (!data) 5452 return -ENOMEM; 5453 5454 msg.buf = data; 5455 5456 memcpy(data, &offset, sizeof(offset)); 5457 memcpy(data + 1, buffer, size); 5458 5459 err = adap->ddc_xfer(adap, &msg, 1); 5460 5461 free(data); 5462 5463 return err; 5464 } 5465 5466 /** 5467 * drm_scdc_readb - read a single byte from SCDC 5468 * @adap: ddc adapter 5469 * @offset: offset of register to read 5470 * @value: return location for the register value 5471 * 5472 * Reads a single byte from SCDC. This is a convenience wrapper around the 5473 * drm_scdc_read() function. 5474 * 5475 * Returns: 5476 * 0 on success or a negative error code on failure. 5477 */ 5478 u8 drm_scdc_readb(struct ddc_adapter *adap, u8 offset, 5479 u8 *value) 5480 { 5481 return hdmi_ddc_read(adap, SCDC_I2C_SLAVE_ADDRESS, offset, value, 5482 sizeof(*value)); 5483 } 5484 5485 /** 5486 * drm_scdc_writeb - write a single byte to SCDC 5487 * @adap: ddc adapter 5488 * @offset: offset of register to read 5489 * @value: return location for the register value 5490 * 5491 * Writes a single byte to SCDC. This is a convenience wrapper around the 5492 * drm_scdc_write() function. 5493 * 5494 * Returns: 5495 * 0 on success or a negative error code on failure. 5496 */ 5497 u8 drm_scdc_writeb(struct ddc_adapter *adap, u8 offset, 5498 u8 value) 5499 { 5500 return hdmi_ddc_write(adap, SCDC_I2C_SLAVE_ADDRESS, offset, &value, 5501 sizeof(value)); 5502 } 5503 5504