1 /* 2 * Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/lists.h> 10 #include <generic-phy.h> 11 #include <syscon.h> 12 #include <asm/io.h> 13 #include <asm/arch/clock.h> 14 15 #include "../usb/gadget/dwc2_udc_otg_priv.h" 16 17 #define U2PHY_BIT_WRITEABLE_SHIFT 16 18 #define CHG_DCD_MAX_RETRIES 6 19 #define CHG_PRI_MAX_RETRIES 2 20 #define CHG_DCD_POLL_TIME 100 /* millisecond */ 21 #define CHG_PRIMARY_DET_TIME 40 /* millisecond */ 22 #define CHG_SECONDARY_DET_TIME 40 /* millisecond */ 23 24 struct rockchip_usb2phy; 25 26 enum power_supply_type { 27 POWER_SUPPLY_TYPE_UNKNOWN = 0, 28 POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */ 29 POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */ 30 POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */ 31 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */ 32 }; 33 34 enum rockchip_usb2phy_port_id { 35 USB2PHY_PORT_OTG, 36 USB2PHY_PORT_HOST, 37 USB2PHY_NUM_PORTS, 38 }; 39 40 struct usb2phy_reg { 41 u32 offset; 42 u32 bitend; 43 u32 bitstart; 44 u32 disable; 45 u32 enable; 46 }; 47 48 /** 49 * struct rockchip_chg_det_reg: usb charger detect registers 50 * @cp_det: charging port detected successfully. 51 * @dcp_det: dedicated charging port detected successfully. 52 * @dp_det: assert data pin connect successfully. 53 * @idm_sink_en: open dm sink curren. 54 * @idp_sink_en: open dp sink current. 55 * @idp_src_en: open dm source current. 56 * @rdm_pdwn_en: open dm pull down resistor. 57 * @vdm_src_en: open dm voltage source. 58 * @vdp_src_en: open dp voltage source. 59 * @opmode: utmi operational mode. 60 */ 61 struct rockchip_chg_det_reg { 62 struct usb2phy_reg cp_det; 63 struct usb2phy_reg dcp_det; 64 struct usb2phy_reg dp_det; 65 struct usb2phy_reg idm_sink_en; 66 struct usb2phy_reg idp_sink_en; 67 struct usb2phy_reg idp_src_en; 68 struct usb2phy_reg rdm_pdwn_en; 69 struct usb2phy_reg vdm_src_en; 70 struct usb2phy_reg vdp_src_en; 71 struct usb2phy_reg opmode; 72 }; 73 74 /** 75 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration. 76 * @phy_sus: phy suspend register. 77 * @bvalid_det_en: vbus valid rise detection enable register. 78 * @bvalid_det_st: vbus valid rise detection status register. 79 * @bvalid_det_clr: vbus valid rise detection clear register. 80 * @ls_det_en: linestate detection enable register. 81 * @ls_det_st: linestate detection state register. 82 * @ls_det_clr: linestate detection clear register. 83 * @iddig_output: iddig output from grf. 84 * @iddig_en: utmi iddig select between grf and phy, 85 * 0: from phy; 1: from grf 86 * @idfall_det_en: id fall detection enable register. 87 * @idfall_det_st: id fall detection state register. 88 * @idfall_det_clr: id fall detection clear register. 89 * @idrise_det_en: id rise detection enable register. 90 * @idrise_det_st: id rise detection state register. 91 * @idrise_det_clr: id rise detection clear register. 92 * @utmi_avalid: utmi vbus avalid status register. 93 * @utmi_bvalid: utmi vbus bvalid status register. 94 * @utmi_iddig: otg port id pin status register. 95 * @utmi_ls: utmi linestate state register. 96 * @utmi_hstdet: utmi host disconnect register. 97 * @vbus_det_en: vbus detect function power down register. 98 */ 99 struct rockchip_usb2phy_port_cfg { 100 struct usb2phy_reg phy_sus; 101 struct usb2phy_reg bvalid_det_en; 102 struct usb2phy_reg bvalid_det_st; 103 struct usb2phy_reg bvalid_det_clr; 104 struct usb2phy_reg ls_det_en; 105 struct usb2phy_reg ls_det_st; 106 struct usb2phy_reg ls_det_clr; 107 struct usb2phy_reg iddig_output; 108 struct usb2phy_reg iddig_en; 109 struct usb2phy_reg idfall_det_en; 110 struct usb2phy_reg idfall_det_st; 111 struct usb2phy_reg idfall_det_clr; 112 struct usb2phy_reg idrise_det_en; 113 struct usb2phy_reg idrise_det_st; 114 struct usb2phy_reg idrise_det_clr; 115 struct usb2phy_reg utmi_avalid; 116 struct usb2phy_reg utmi_bvalid; 117 struct usb2phy_reg utmi_iddig; 118 struct usb2phy_reg utmi_ls; 119 struct usb2phy_reg utmi_hstdet; 120 struct usb2phy_reg vbus_det_en; 121 }; 122 123 /** 124 * struct rockchip_usb2phy_cfg: usb-phy configuration. 125 * @reg: the address offset of grf for usb-phy config. 126 * @num_ports: specify how many ports that the phy has. 127 * @phy_tuning: phy default parameters tunning. 128 * @clkout_ctl: keep on/turn off output clk of phy. 129 * @chg_det: charger detection registers. 130 */ 131 struct rockchip_usb2phy_cfg { 132 u32 reg; 133 u32 num_ports; 134 int (*phy_tuning)(struct rockchip_usb2phy *); 135 struct usb2phy_reg clkout_ctl; 136 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 137 const struct rockchip_chg_det_reg chg_det; 138 }; 139 140 /** 141 * @dcd_retries: The retry count used to track Data contact 142 * detection process. 143 * @primary_retries: The retry count used to do usb bc detection 144 * primary stage. 145 * @grf: General Register Files register base. 146 * @usbgrf_base : USB General Register Files register base. 147 * @phy_cfg: phy register configuration, assigned by driver data. 148 */ 149 struct rockchip_usb2phy { 150 u8 dcd_retries; 151 u8 primary_retries; 152 void __iomem *grf_base; 153 void __iomem *usbgrf_base; 154 const struct rockchip_usb2phy_cfg *phy_cfg; 155 }; 156 157 static inline void __iomem *get_reg_base(struct rockchip_usb2phy *rphy) 158 { 159 return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base; 160 } 161 162 static inline int property_enable(void __iomem *base, 163 const struct usb2phy_reg *reg, bool en) 164 { 165 u32 val, mask, tmp; 166 167 tmp = en ? reg->enable : reg->disable; 168 mask = GENMASK(reg->bitend, reg->bitstart); 169 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT); 170 171 return writel(val, base + reg->offset); 172 } 173 174 static inline bool property_enabled(void __iomem *base, 175 const struct usb2phy_reg *reg) 176 { 177 u32 tmp, orig; 178 u32 mask = GENMASK(reg->bitend, reg->bitstart); 179 180 orig = readl(base + reg->offset); 181 182 tmp = (orig & mask) >> reg->bitstart; 183 184 return tmp == reg->enable; 185 } 186 187 static const char *chg_to_string(enum power_supply_type chg_type) 188 { 189 switch (chg_type) { 190 case POWER_SUPPLY_TYPE_USB: 191 return "USB_SDP_CHARGER"; 192 case POWER_SUPPLY_TYPE_USB_DCP: 193 return "USB_DCP_CHARGER"; 194 case POWER_SUPPLY_TYPE_USB_CDP: 195 return "USB_CDP_CHARGER"; 196 case POWER_SUPPLY_TYPE_USB_FLOATING: 197 return "USB_FLOATING_CHARGER"; 198 default: 199 return "INVALID_CHARGER"; 200 } 201 } 202 203 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, 204 bool en) 205 { 206 void __iomem *base = get_reg_base(rphy); 207 208 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); 209 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); 210 } 211 212 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, 213 bool en) 214 { 215 void __iomem *base = get_reg_base(rphy); 216 217 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); 218 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); 219 } 220 221 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, 222 bool en) 223 { 224 void __iomem *base = get_reg_base(rphy); 225 226 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); 227 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); 228 } 229 230 static bool rockchip_chg_primary_det_retry(struct rockchip_usb2phy *rphy) 231 { 232 bool vout = false; 233 234 while (rphy->primary_retries--) { 235 /* voltage source on DP, probe on DM */ 236 rockchip_chg_enable_primary_det(rphy, true); 237 mdelay(CHG_PRIMARY_DET_TIME); 238 vout = property_enabled(rphy->grf_base, 239 &rphy->phy_cfg->chg_det.cp_det); 240 if (vout) 241 break; 242 } 243 244 rockchip_chg_enable_primary_det(rphy, false); 245 return vout; 246 } 247 248 int rockchip_chg_get_type(void) 249 { 250 const struct rockchip_usb2phy_port_cfg *port_cfg; 251 enum power_supply_type chg_type; 252 struct rockchip_usb2phy *rphy; 253 struct udevice *udev; 254 void __iomem *base; 255 bool is_dcd, vout; 256 int ret; 257 258 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 259 if (ret == -ENODEV) { 260 pr_err("%s: get u2phy node failed: %d\n", __func__, ret); 261 return ret; 262 } 263 264 rphy = dev_get_priv(udev); 265 base = get_reg_base(rphy); 266 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 267 268 /* Check USB-Vbus status first */ 269 if (!property_enabled(base, &port_cfg->utmi_bvalid)) { 270 pr_info("%s: no charger found\n", __func__); 271 return POWER_SUPPLY_TYPE_UNKNOWN; 272 } 273 274 /* Suspend USB-PHY and put the controller in non-driving mode */ 275 property_enable(base, &port_cfg->phy_sus, true); 276 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); 277 278 rphy->dcd_retries = CHG_DCD_MAX_RETRIES; 279 rphy->primary_retries = CHG_PRI_MAX_RETRIES; 280 281 /* stage 1, start DCD processing stage */ 282 rockchip_chg_enable_dcd(rphy, true); 283 284 while (rphy->dcd_retries--) { 285 mdelay(CHG_DCD_POLL_TIME); 286 287 /* get data contact detection status */ 288 is_dcd = property_enabled(rphy->grf_base, 289 &rphy->phy_cfg->chg_det.dp_det); 290 291 if (is_dcd || !rphy->dcd_retries) { 292 /* 293 * stage 2, turn off DCD circuitry, then 294 * voltage source on DP, probe on DM. 295 */ 296 rockchip_chg_enable_dcd(rphy, false); 297 rockchip_chg_enable_primary_det(rphy, true); 298 break; 299 } 300 } 301 302 mdelay(CHG_PRIMARY_DET_TIME); 303 vout = property_enabled(rphy->grf_base, 304 &rphy->phy_cfg->chg_det.cp_det); 305 rockchip_chg_enable_primary_det(rphy, false); 306 if (vout) { 307 /* stage 3, voltage source on DM, probe on DP */ 308 rockchip_chg_enable_secondary_det(rphy, true); 309 } else { 310 if (!rphy->dcd_retries) { 311 /* floating charger found */ 312 chg_type = POWER_SUPPLY_TYPE_USB_FLOATING; 313 goto out; 314 } else { 315 /* 316 * Retry some times to make sure that it's 317 * really a USB SDP charger. 318 */ 319 vout = rockchip_chg_primary_det_retry(rphy); 320 if (vout) { 321 /* stage 3, voltage source on DM, probe on DP */ 322 rockchip_chg_enable_secondary_det(rphy, true); 323 } else { 324 /* USB SDP charger found */ 325 chg_type = POWER_SUPPLY_TYPE_USB; 326 goto out; 327 } 328 } 329 } 330 331 mdelay(CHG_SECONDARY_DET_TIME); 332 vout = property_enabled(rphy->grf_base, 333 &rphy->phy_cfg->chg_det.dcp_det); 334 /* stage 4, turn off voltage source */ 335 rockchip_chg_enable_secondary_det(rphy, false); 336 if (vout) 337 chg_type = POWER_SUPPLY_TYPE_USB_DCP; 338 else 339 chg_type = POWER_SUPPLY_TYPE_USB_CDP; 340 341 out: 342 /* Resume USB-PHY and put the controller in normal mode */ 343 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); 344 property_enable(base, &port_cfg->phy_sus, false); 345 346 debug("charger is %s\n", chg_to_string(chg_type)); 347 348 return chg_type; 349 } 350 351 int rockchip_u2phy_vbus_detect(void) 352 { 353 int chg_type; 354 355 chg_type = rockchip_chg_get_type(); 356 357 return (chg_type == POWER_SUPPLY_TYPE_USB || 358 chg_type == POWER_SUPPLY_TYPE_USB_CDP) ? 1 : 0; 359 } 360 361 void otg_phy_init(struct dwc2_udc *dev) 362 { 363 const struct rockchip_usb2phy_port_cfg *port_cfg; 364 struct rockchip_usb2phy *rphy; 365 struct udevice *udev; 366 void __iomem *base; 367 int ret; 368 369 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev); 370 if (ret == -ENODEV) { 371 pr_err("%s: get u2phy node failed: %d\n", __func__, ret); 372 return; 373 } 374 375 rphy = dev_get_priv(udev); 376 base = get_reg_base(rphy); 377 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 378 379 /* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */ 380 property_enable(base, &rphy->phy_cfg->clkout_ctl, false); 381 382 /* Reset USB-PHY */ 383 property_enable(base, &port_cfg->phy_sus, true); 384 udelay(20); 385 property_enable(base, &port_cfg->phy_sus, false); 386 mdelay(2); 387 } 388 389 static int rockchip_usb2phy_init(struct phy *phy) 390 { 391 struct udevice *parent = phy->dev->parent; 392 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 393 const struct rockchip_usb2phy_port_cfg *port_cfg; 394 void __iomem *base = get_reg_base(rphy); 395 396 if (phy->id == USB2PHY_PORT_OTG) { 397 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 398 } else if (phy->id == USB2PHY_PORT_HOST) { 399 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 400 } else { 401 dev_err(phy->dev, "phy id %lu not support", phy->id); 402 return -EINVAL; 403 } 404 405 property_enable(base, &port_cfg->phy_sus, false); 406 407 /* waiting for the utmi_clk to become stable */ 408 udelay(2000); 409 410 return 0; 411 } 412 413 static int rockchip_usb2phy_exit(struct phy *phy) 414 { 415 struct udevice *parent = phy->dev->parent; 416 struct rockchip_usb2phy *rphy = dev_get_priv(parent); 417 const struct rockchip_usb2phy_port_cfg *port_cfg; 418 void __iomem *base = get_reg_base(rphy); 419 420 if (phy->id == USB2PHY_PORT_OTG) { 421 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 422 } else if (phy->id == USB2PHY_PORT_HOST) { 423 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 424 } else { 425 dev_err(phy->dev, "phy id %lu not support", phy->id); 426 return -EINVAL; 427 } 428 429 property_enable(base, &port_cfg->phy_sus, true); 430 431 return 0; 432 } 433 434 static int rockchip_usb2phy_of_xlate(struct phy *phy, 435 struct ofnode_phandle_args *args) 436 { 437 const char *dev_name = phy->dev->name; 438 439 if (!strcasecmp(dev_name, "host-port")) { 440 phy->id = USB2PHY_PORT_HOST; 441 } else if (!strcasecmp(dev_name, "otg-port")) { 442 phy->id = USB2PHY_PORT_OTG; 443 } else { 444 pr_err("%s: invalid dev name\n", __func__); 445 return -EINVAL; 446 } 447 448 return 0; 449 } 450 451 static int rockchip_usb2phy_bind(struct udevice *dev) 452 { 453 struct udevice *child; 454 ofnode subnode; 455 const char *node_name; 456 int ret; 457 458 dev_for_each_subnode(subnode, dev) { 459 if (!ofnode_valid(subnode)) { 460 debug("%s: %s subnode not found", __func__, dev->name); 461 return -ENXIO; 462 } 463 464 node_name = ofnode_get_name(subnode); 465 debug("%s: subnode %s\n", __func__, node_name); 466 467 ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port", 468 node_name, subnode, &child); 469 if (ret) { 470 pr_err("%s: '%s' cannot bind 'rockchip_usb2phy_port'\n", 471 __func__, node_name); 472 return ret; 473 } 474 } 475 476 return 0; 477 } 478 479 static int rockchip_usb2phy_probe(struct udevice *dev) 480 { 481 const struct rockchip_usb2phy_cfg *phy_cfgs; 482 struct rockchip_usb2phy *rphy = dev_get_priv(dev); 483 struct udevice *parent = dev->parent; 484 u32 reg, index; 485 486 if (!strncmp(parent->name, "root_driver", 11) && 487 dev_read_bool(dev, "rockchip,grf")) 488 rphy->grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 489 else 490 rphy->grf_base = (void __iomem *)dev_read_addr(parent); 491 492 if (rphy->grf_base <= 0) { 493 dev_err(dev, "get syscon grf failed\n"); 494 return -EINVAL; 495 } 496 497 if (dev_read_bool(dev, "rockchip,usbgrf")) { 498 rphy->usbgrf_base = 499 syscon_get_first_range(ROCKCHIP_SYSCON_USBGRF); 500 if (rphy->usbgrf_base <= 0) { 501 dev_err(dev, "get syscon usbgrf failed\n"); 502 return -EINVAL; 503 } 504 } else { 505 rphy->usbgrf_base = NULL; 506 } 507 508 if (ofnode_read_u32(dev_ofnode(dev), "reg", ®)) { 509 dev_err(dev, "could not read reg\n"); 510 return -EINVAL; 511 } 512 513 phy_cfgs = 514 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev); 515 if (!phy_cfgs) { 516 dev_err(dev, "unable to get phy_cfgs\n"); 517 return -EINVAL; 518 } 519 520 /* find out a proper config which can be matched with dt. */ 521 index = 0; 522 while (phy_cfgs[index].reg) { 523 if (phy_cfgs[index].reg == reg) { 524 rphy->phy_cfg = &phy_cfgs[index]; 525 break; 526 } 527 ++index; 528 } 529 530 if (!rphy->phy_cfg) { 531 dev_err(dev, "no phy-config can be matched\n"); 532 return -EINVAL; 533 } 534 535 if (rphy->phy_cfg->phy_tuning) 536 rphy->phy_cfg->phy_tuning(rphy); 537 538 return 0; 539 } 540 541 static int rk322x_usb2phy_tuning(struct rockchip_usb2phy *rphy) 542 { 543 void __iomem *base = get_reg_base(rphy); 544 int ret = 0; 545 546 /* Open pre-emphasize in non-chirp state for PHY0 otg port */ 547 if (rphy->phy_cfg->reg == 0x760) 548 ret = writel(0x00070004, base + 0x76c); 549 550 return ret; 551 } 552 553 static struct phy_ops rockchip_usb2phy_ops = { 554 .init = rockchip_usb2phy_init, 555 .exit = rockchip_usb2phy_exit, 556 .of_xlate = rockchip_usb2phy_of_xlate, 557 }; 558 559 static const struct rockchip_usb2phy_cfg rk1808_phy_cfgs[] = { 560 { 561 .reg = 0x100, 562 .num_ports = 2, 563 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 564 .port_cfgs = { 565 [USB2PHY_PORT_OTG] = { 566 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 567 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 568 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 569 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 570 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 571 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 572 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 573 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 574 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 575 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 576 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 577 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 578 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 579 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 580 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 581 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 582 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 583 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 584 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 585 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 586 }, 587 [USB2PHY_PORT_HOST] = { 588 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 589 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 590 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 591 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 592 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 593 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 594 } 595 }, 596 .chg_det = { 597 .opmode = { 0x0100, 3, 0, 5, 1 }, 598 .cp_det = { 0x0120, 24, 24, 0, 1 }, 599 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 600 .dp_det = { 0x0120, 25, 25, 0, 1 }, 601 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 602 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 603 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 604 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 605 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 606 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 607 }, 608 }, 609 { /* sentinel */ } 610 }; 611 612 static const struct rockchip_usb2phy_cfg rk312x_phy_cfgs[] = { 613 { 614 .reg = 0x17c, 615 .num_ports = 2, 616 .clkout_ctl = { 0x0190, 15, 15, 1, 0 }, 617 .port_cfgs = { 618 [USB2PHY_PORT_OTG] = { 619 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 }, 620 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 }, 621 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 }, 622 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 }, 623 .iddig_output = { 0x017c, 10, 10, 0, 1 }, 624 .iddig_en = { 0x017c, 9, 9, 0, 1 }, 625 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 }, 626 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 }, 627 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 }, 628 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 }, 629 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 }, 630 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 }, 631 .ls_det_en = { 0x017c, 12, 12, 0, 1 }, 632 .ls_det_st = { 0x017c, 13, 13, 0, 1 }, 633 .ls_det_clr = { 0x017c, 13, 13, 0, 1 }, 634 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 }, 635 .utmi_iddig = { 0x014c, 8, 8, 0, 1 }, 636 .utmi_ls = { 0x014c, 7, 6, 0, 1 }, 637 }, 638 [USB2PHY_PORT_HOST] = { 639 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 }, 640 .ls_det_en = { 0x0194, 14, 14, 0, 1 }, 641 .ls_det_st = { 0x0194, 15, 15, 0, 1 }, 642 .ls_det_clr = { 0x0194, 15, 15, 0, 1 } 643 } 644 }, 645 .chg_det = { 646 .opmode = { 0x017c, 3, 0, 5, 1 }, 647 .cp_det = { 0x02c0, 6, 6, 0, 1 }, 648 .dcp_det = { 0x02c0, 5, 5, 0, 1 }, 649 .dp_det = { 0x02c0, 7, 7, 0, 1 }, 650 .idm_sink_en = { 0x0184, 8, 8, 0, 1 }, 651 .idp_sink_en = { 0x0184, 7, 7, 0, 1 }, 652 .idp_src_en = { 0x0184, 9, 9, 0, 1 }, 653 .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 }, 654 .vdm_src_en = { 0x0184, 12, 12, 0, 1 }, 655 .vdp_src_en = { 0x0184, 11, 11, 0, 1 }, 656 }, 657 }, 658 { /* sentinel */ } 659 }; 660 661 static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = { 662 { 663 .reg = 0x760, 664 .num_ports = 2, 665 .phy_tuning = rk322x_usb2phy_tuning, 666 .clkout_ctl = { 0x0768, 4, 4, 1, 0 }, 667 .port_cfgs = { 668 [USB2PHY_PORT_OTG] = { 669 .phy_sus = { 0x0760, 8, 0, 0, 0x1d1 }, 670 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 671 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 672 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 673 .iddig_output = { 0x0760, 10, 10, 0, 1 }, 674 .iddig_en = { 0x0760, 9, 9, 0, 1 }, 675 .idfall_det_en = { 0x0680, 6, 6, 0, 1 }, 676 .idfall_det_st = { 0x0690, 6, 6, 0, 1 }, 677 .idfall_det_clr = { 0x06a0, 6, 6, 0, 1 }, 678 .idrise_det_en = { 0x0680, 5, 5, 0, 1 }, 679 .idrise_det_st = { 0x0690, 5, 5, 0, 1 }, 680 .idrise_det_clr = { 0x06a0, 5, 5, 0, 1 }, 681 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 682 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 683 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 684 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, 685 .utmi_iddig = { 0x0480, 1, 1, 0, 1 }, 686 .utmi_ls = { 0x0480, 3, 2, 0, 1 }, 687 .vbus_det_en = { 0x0788, 15, 15, 1, 0 }, 688 }, 689 [USB2PHY_PORT_HOST] = { 690 .phy_sus = { 0x0764, 8, 0, 0, 0x1d1 }, 691 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 692 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 693 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 694 } 695 }, 696 .chg_det = { 697 .opmode = { 0x0760, 3, 0, 5, 1 }, 698 .cp_det = { 0x0884, 4, 4, 0, 1 }, 699 .dcp_det = { 0x0884, 3, 3, 0, 1 }, 700 .dp_det = { 0x0884, 5, 5, 0, 1 }, 701 .idm_sink_en = { 0x0768, 8, 8, 0, 1 }, 702 .idp_sink_en = { 0x0768, 7, 7, 0, 1 }, 703 .idp_src_en = { 0x0768, 9, 9, 0, 1 }, 704 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 }, 705 .vdm_src_en = { 0x0768, 12, 12, 0, 1 }, 706 .vdp_src_en = { 0x0768, 11, 11, 0, 1 }, 707 }, 708 }, 709 { 710 .reg = 0x800, 711 .num_ports = 2, 712 .clkout_ctl = { 0x0808, 4, 4, 1, 0 }, 713 .port_cfgs = { 714 [USB2PHY_PORT_OTG] = { 715 .phy_sus = { 0x804, 8, 0, 0, 0x1d1 }, 716 .ls_det_en = { 0x0684, 1, 1, 0, 1 }, 717 .ls_det_st = { 0x0694, 1, 1, 0, 1 }, 718 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 } 719 }, 720 [USB2PHY_PORT_HOST] = { 721 .phy_sus = { 0x800, 8, 0, 0, 0x1d1 }, 722 .ls_det_en = { 0x0684, 0, 0, 0, 1 }, 723 .ls_det_st = { 0x0694, 0, 0, 0, 1 }, 724 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 } 725 } 726 }, 727 }, 728 { /* sentinel */ } 729 }; 730 731 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { 732 { 733 .reg = 0x100, 734 .num_ports = 2, 735 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 736 .port_cfgs = { 737 [USB2PHY_PORT_OTG] = { 738 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 739 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 740 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 741 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 742 .iddig_output = { 0x0100, 10, 10, 0, 1 }, 743 .iddig_en = { 0x0100, 9, 9, 0, 1 }, 744 .idfall_det_en = { 0x0110, 5, 5, 0, 1 }, 745 .idfall_det_st = { 0x0114, 5, 5, 0, 1 }, 746 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 }, 747 .idrise_det_en = { 0x0110, 4, 4, 0, 1 }, 748 .idrise_det_st = { 0x0114, 4, 4, 0, 1 }, 749 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 }, 750 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 751 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 752 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 753 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 754 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 755 .utmi_iddig = { 0x0120, 6, 6, 0, 1 }, 756 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 757 .vbus_det_en = { 0x001c, 15, 15, 1, 0 }, 758 }, 759 [USB2PHY_PORT_HOST] = { 760 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 }, 761 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 762 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 763 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 764 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 765 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 766 } 767 }, 768 .chg_det = { 769 .opmode = { 0x0100, 3, 0, 5, 1 }, 770 .cp_det = { 0x0120, 24, 24, 0, 1 }, 771 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 772 .dp_det = { 0x0120, 25, 25, 0, 1 }, 773 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 774 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 775 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 776 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 777 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 778 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 779 }, 780 }, 781 { /* sentinel */ } 782 }; 783 784 static const struct rockchip_usb2phy_cfg rk3368_phy_cfgs[] = { 785 { 786 .reg = 0x700, 787 .num_ports = 2, 788 .clkout_ctl = { 0x0724, 15, 15, 1, 0 }, 789 .port_cfgs = { 790 [USB2PHY_PORT_OTG] = { 791 .phy_sus = { 0x0700, 8, 0, 0, 0x1d1 }, 792 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 793 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 794 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 795 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 796 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 797 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 798 .utmi_bvalid = { 0x04bc, 23, 23, 0, 1 }, 799 .utmi_ls = { 0x04bc, 25, 24, 0, 1 }, 800 }, 801 [USB2PHY_PORT_HOST] = { 802 .phy_sus = { 0x0728, 8, 0, 0, 0x1d1 }, 803 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 804 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 805 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 806 } 807 }, 808 .chg_det = { 809 .opmode = { 0x0700, 3, 0, 5, 1 }, 810 .cp_det = { 0x04b8, 30, 30, 0, 1 }, 811 .dcp_det = { 0x04b8, 29, 29, 0, 1 }, 812 .dp_det = { 0x04b8, 31, 31, 0, 1 }, 813 .idm_sink_en = { 0x0718, 8, 8, 0, 1 }, 814 .idp_sink_en = { 0x0718, 7, 7, 0, 1 }, 815 .idp_src_en = { 0x0718, 9, 9, 0, 1 }, 816 .rdm_pdwn_en = { 0x0718, 10, 10, 0, 1 }, 817 .vdm_src_en = { 0x0718, 12, 12, 0, 1 }, 818 .vdp_src_en = { 0x0718, 11, 11, 0, 1 }, 819 }, 820 }, 821 { /* sentinel */ } 822 }; 823 824 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { 825 { 826 .reg = 0xe450, 827 .num_ports = 2, 828 .clkout_ctl = { 0xe450, 4, 4, 1, 0 }, 829 .port_cfgs = { 830 [USB2PHY_PORT_OTG] = { 831 .phy_sus = { 0xe454, 8, 0, 0x052, 0x1d1 }, 832 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, 833 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, 834 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, 835 .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 }, 836 .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 }, 837 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 }, 838 .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 }, 839 .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 }, 840 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 }, 841 .ls_det_en = { 0xe3c0, 2, 2, 0, 1 }, 842 .ls_det_st = { 0xe3e0, 2, 2, 0, 1 }, 843 .ls_det_clr = { 0xe3d0, 2, 2, 0, 1 }, 844 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, 845 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, 846 .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 }, 847 .utmi_ls = { 0xe2ac, 14, 13, 0, 1 }, 848 .vbus_det_en = { 0x449c, 15, 15, 1, 0 }, 849 }, 850 [USB2PHY_PORT_HOST] = { 851 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, 852 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 }, 853 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 }, 854 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 }, 855 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 }, 856 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 } 857 } 858 }, 859 .chg_det = { 860 .opmode = { 0xe454, 3, 0, 5, 1 }, 861 .cp_det = { 0xe2ac, 2, 2, 0, 1 }, 862 .dcp_det = { 0xe2ac, 1, 1, 0, 1 }, 863 .dp_det = { 0xe2ac, 0, 0, 0, 1 }, 864 .idm_sink_en = { 0xe450, 8, 8, 0, 1 }, 865 .idp_sink_en = { 0xe450, 7, 7, 0, 1 }, 866 .idp_src_en = { 0xe450, 9, 9, 0, 1 }, 867 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 }, 868 .vdm_src_en = { 0xe450, 12, 12, 0, 1 }, 869 .vdp_src_en = { 0xe450, 11, 11, 0, 1 }, 870 }, 871 }, 872 { 873 .reg = 0xe460, 874 .num_ports = 2, 875 .clkout_ctl = { 0xe460, 4, 4, 1, 0 }, 876 .port_cfgs = { 877 [USB2PHY_PORT_OTG] = { 878 .phy_sus = { 0xe464, 8, 0, 0x052, 0x1d1 }, 879 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, 880 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, 881 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, 882 .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 }, 883 .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 }, 884 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 }, 885 .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 }, 886 .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 }, 887 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 }, 888 .ls_det_en = { 0xe3c0, 7, 7, 0, 1 }, 889 .ls_det_st = { 0xe3e0, 7, 7, 0, 1 }, 890 .ls_det_clr = { 0xe3d0, 7, 7, 0, 1 }, 891 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, 892 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, 893 .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 }, 894 .utmi_ls = { 0xe2ac, 18, 17, 0, 1 }, 895 .vbus_det_en = { 0x451c, 15, 15, 1, 0 }, 896 }, 897 [USB2PHY_PORT_HOST] = { 898 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, 899 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 }, 900 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 }, 901 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 }, 902 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 }, 903 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 } 904 } 905 }, 906 .chg_det = { 907 .opmode = { 0xe464, 3, 0, 5, 1 }, 908 .cp_det = { 0xe2ac, 5, 5, 0, 1 }, 909 .dcp_det = { 0xe2ac, 4, 4, 0, 1 }, 910 .dp_det = { 0xe2ac, 3, 3, 0, 1 }, 911 .idm_sink_en = { 0xe460, 8, 8, 0, 1 }, 912 .idp_sink_en = { 0xe460, 7, 7, 0, 1 }, 913 .idp_src_en = { 0xe460, 9, 9, 0, 1 }, 914 .rdm_pdwn_en = { 0xe460, 10, 10, 0, 1 }, 915 .vdm_src_en = { 0xe460, 12, 12, 0, 1 }, 916 .vdp_src_en = { 0xe460, 11, 11, 0, 1 }, 917 }, 918 }, 919 { /* sentinel */ } 920 }; 921 922 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { 923 { 924 .reg = 0x100, 925 .num_ports = 2, 926 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 927 .port_cfgs = { 928 [USB2PHY_PORT_OTG] = { 929 .phy_sus = { 0x0ffa0100, 8, 0, 0, 0x1d1 }, 930 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 931 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 932 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 933 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 934 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 935 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 936 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, 937 .utmi_ls = { 0x0804, 13, 12, 0, 1 }, 938 }, 939 [USB2PHY_PORT_HOST] = { 940 .phy_sus = { 0x0ffa0104, 8, 0, 0, 0x1d1 }, 941 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 942 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 943 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 944 .utmi_ls = { 0x0804, 9, 8, 0, 1 }, 945 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } 946 } 947 }, 948 .chg_det = { 949 .opmode = { 0x0ffa0100, 3, 0, 5, 1 }, 950 .cp_det = { 0x0804, 1, 1, 0, 1 }, 951 .dcp_det = { 0x0804, 0, 0, 0, 1 }, 952 .dp_det = { 0x0804, 2, 2, 0, 1 }, 953 .idm_sink_en = { 0x0ffa0108, 8, 8, 0, 1 }, 954 .idp_sink_en = { 0x0ffa0108, 7, 7, 0, 1 }, 955 .idp_src_en = { 0x0ffa0108, 9, 9, 0, 1 }, 956 .rdm_pdwn_en = { 0x0ffa0108, 10, 10, 0, 1 }, 957 .vdm_src_en = { 0x0ffa0108, 12, 12, 0, 1 }, 958 .vdp_src_en = { 0x0ffa0108, 11, 11, 0, 1 }, 959 }, 960 }, 961 { /* sentinel */ } 962 }; 963 964 static const struct udevice_id rockchip_usb2phy_ids[] = { 965 { .compatible = "rockchip,rk1808-usb2phy", .data = (ulong)&rk1808_phy_cfgs }, 966 { .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs }, 967 { .compatible = "rockchip,rk322x-usb2phy", .data = (ulong)&rk322x_phy_cfgs }, 968 { .compatible = "rockchip,rk3308-usb2phy", .data = (ulong)&rk3328_phy_cfgs }, 969 { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs }, 970 { .compatible = "rockchip,rk3368-usb2phy", .data = (ulong)&rk3368_phy_cfgs }, 971 { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_phy_cfgs }, 972 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs }, 973 { } 974 }; 975 976 U_BOOT_DRIVER(rockchip_usb2phy_port) = { 977 .name = "rockchip_usb2phy_port", 978 .id = UCLASS_PHY, 979 .ops = &rockchip_usb2phy_ops, 980 }; 981 982 U_BOOT_DRIVER(rockchip_usb2phy) = { 983 .name = "rockchip_usb2phy", 984 .id = UCLASS_PHY, 985 .of_match = rockchip_usb2phy_ids, 986 .probe = rockchip_usb2phy_probe, 987 .bind = rockchip_usb2phy_bind, 988 .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy), 989 }; 990