1 /* 2 * (C) Copyright 2013 3 * David Feng <fenghua@phytium.com.cn> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <linux/compiler.h> 10 #include <efi_loader.h> 11 #include <iomem.h> 12 #include <stacktrace.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_IRQ) 16 17 int interrupt_init(void) 18 { 19 return 0; 20 } 21 22 void enable_interrupts(void) 23 { 24 return; 25 } 26 27 int disable_interrupts(void) 28 { 29 return 0; 30 } 31 #endif 32 33 #if (!defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)) 34 #define REG_BITS(val, shift, mask) (((val) >> (shift)) & (mask)) 35 36 void show_regs(struct pt_regs *regs) 37 { 38 int i; 39 int el = current_el(); 40 const char *h_scr_name[] = { 41 [2] = "HCR_EL2", 42 [3] = "SCR_EL3", 43 }; 44 const char *esr_bits_ec[] = { 45 [0] = "EC[31:26] == 000000, Exception with an unknown reason", 46 [1] = "EC[31:26] == 000001, Exception from a WFI or WFE instruction", 47 [3] = "EC[31:26] == 000011, Exception from an MCR or MRC access", 48 [4] = "EC[31:26] == 000100, Exception from an MCRR or MRRC access", 49 [5] = "EC[31:26] == 000101, Exception from an MCR or MRC access", 50 [6] = "EC[31:26] == 000110, Exception from an LDC or STC access to CP14", 51 [7] = "EC[31:26] == 000111, Exception from an access to an Advanced SIMD or floating-point register, resulting from CPACR_EL1.FPEN or CPTR_ELx.TFP", 52 [8] = "EC[31:26] == 001000, Exception from an MCR or MRC access", 53 [12] = "EC[31:26] == 001100, Exception from an MCRR or MRRC access", 54 [14] = "EC[31:26] == 001110, Exception from an Illegal execution state, or a PC or SP alignment fault", 55 [10] = "EC[31:26] == 010001, Exception from HVC or SVC instruction execution", 56 [18] = "EC[31:26] == 010010, Exception from HVC or SVC instruction execution", 57 [19] = "EC[31:26] == 010011, Exception from SMC instruction execution in AArch32 state", 58 [21] = "EC[31:26] == 010101, Exception from HVC or SVC instruction execution", 59 [22] = "EC[31:26] == 010110, Exception from HVC or SVC instruction execution", 60 [23] = "EC[31:26] == 010111, Exception from SMC instruction execution in AArch64 state", 61 [24] = "EC[31:26] == 011000, Exception from MSR, MRS, or System instruction execution in AArch64 state", 62 [31] = "EC[31:26] == 011111, IMPLEMENTATION DEFINED exception to EL3", 63 [32] = "EC[31:26] == 100000, Exception from an Instruction abort", 64 [33] = "EC[31:26] == 100001, Exception from an Instruction abort", 65 [34] = "EC[31:26] == 100010, Exception from an Illegal execution state, or a PC or SP alignment fault", 66 [36] = "EC[31:26] == 100100, Exception from a Data abort, from lower exception level", 67 [37] = "EC[31:26] == 100101, Exception from a Data abort, from current exception level", 68 [38] = "EC[31:26] == 100110, Exception from an Illegal execution state, or a PC or SP alignment fault", 69 [40] = "EC[31:26] == 101000, Exception from a trapped Floating-point exception", 70 [44] = "EC[31:26] == 101100, Exception from a trapped Floating-point exception", 71 [47] = "EC[31:26] == 101111, SError interrupt", 72 [48] = "EC[31:26] == 110000, Exception from a Breakpoint or Vector Catch debug event", 73 [49] = "EC[31:26] == 110001, Exception from a Breakpoint or Vector Catch debug event", 74 [50] = "EC[31:26] == 110010, Exception from a Software Step debug event", 75 [51] = "EC[31:26] == 110011, Exception from a Software Step debug event", 76 [52] = "EC[31:26] == 110100, Exception from a Watchpoint debug event", 77 [53] = "EC[31:26] == 110101, Exception from a Watchpoint debug event", 78 [56] = "EC[31:26] == 111000, Exception from execution of a Software Breakpoint instructio", 79 }; 80 const char *esr_bits_il[] = { 81 "IL[25] == 0, 16-bit instruction trapped", 82 "IL[25] == 1, 32-bit instruction trapped", 83 }; 84 const char *daif_bits_f[] = { 85 "F[6] == 0, FIQ not masked", 86 "F[6] == 1, FIQ masked", 87 }; 88 const char *daif_bits_i[] = { 89 "I[7] == 0, IRQ not masked", 90 "I[7] == 1, IRQ masked", 91 }; 92 const char *daif_bits_a[] = { 93 "A[8] == 0, ABORT not masked", 94 "A[8] == 1, ABORT masked", 95 }; 96 const char *daif_bits_d[] = { 97 "D[9] == 0, DBG not masked", 98 "D[9] == 1, DBG masked", 99 }; 100 const char *spsr_bits_m_aarch32[] = { 101 [0] = "M[3:0] == 0000, User", 102 [1] = "M[3:0] == 0001, FIQ", 103 [2] = "M[3:0] == 0010, IRQ", 104 [3] = "M[3:0] == 0011, Supervisor", 105 [6] = "M[3:0] == 0110, Monitor", 106 [7] = "M[3:0] == 0111, Abort", 107 [10] = "M[3:0] == 1010, Hyp", 108 [11] = "M[3:0] == 1011, Undefined", 109 [15] = "M[3:0] == 1111, System", 110 }; 111 const char *spsr_bits_m_aarch64[] = { 112 [0] = "M[3:0] == 0000, EL0t", 113 [4] = "M[3:0] == 0100, EL1t", 114 [5] = "M[3:0] == 0101, EL1h", 115 [8] = "M[3:0] == 1000, EL2t", 116 [9] = "M[3:0] == 1001, EL2h", 117 [10] = "M[3:0] == 1100, EL3t", 118 [11] = "M[3:0] == 1101, EL3h", 119 }; 120 const char *spsr_bits_m[] = { 121 "M[4] == 0, Exception taken from AArch64", 122 "M[4] == 1, Exception taken from AArch32", 123 }; 124 const char *spsr_bits_f[] = { 125 "F[6] == 0, FIQ not masked", 126 "F[6] == 1, FIQ masked", 127 }; 128 const char *spsr_bits_i[] = { 129 "I[7] == 0, IRQ not masked", 130 "I[7] == 1, IRQ masked", 131 }; 132 const char *spsr_bits_a[] = { 133 "A[8] == 0, ABORT not masked", 134 "A[8] == 1, ABORT masked", 135 }; 136 const char *spsr_bits_d[] = { 137 "D[9] == 0, DBG not masked", 138 "D[9] == 1, DBG masked", 139 }; 140 const char *sctlr_bits_i[] = { 141 "I[12] == 0, Icache disabled", 142 "I[12] == 1, Icaches enabled", 143 }; 144 const char *sctlr_bits_c[] = { 145 "C[2] == 0, Dcache disabled", 146 "C[2] == 1, Dcache enabled", 147 }; 148 const char *sctlr_bits_m[] = { 149 "M[0] == 0, MMU disabled", 150 "M[0] == 1, MMU enabled", 151 }; 152 153 printf("* Relocate offset = %016lx\n", gd->reloc_off); 154 155 if (gd->flags & GD_FLG_RELOC) { 156 printf("* ELR(PC) = %016lx\n", regs->elr - gd->reloc_off); 157 printf("* LR = %016lx\n", regs->regs[30] - gd->reloc_off); 158 } else { 159 printf("* ELR(PC) = %016lx\n", regs->elr); 160 printf("* LR = %016lx\n", regs->regs[30]); 161 } 162 163 printf("* SP = %016lx\n", regs->sp); 164 printf("\n"); 165 166 /* 167 * System registers 168 */ 169 /* ESR_EL2 */ 170 printf("* ESR_EL%d = %016lx\n", el, regs->esr); 171 printf("\t%s\n", esr_bits_ec[REG_BITS(regs->esr, 26, 0x3f)]); 172 printf("\t%s\n", esr_bits_il[REG_BITS(regs->esr, 25, 0x01)]); 173 printf("\n"); 174 /* DAIF */ 175 printf("* DAIF = %016lx\n", regs->daif); 176 printf("\t%s\n", daif_bits_d[REG_BITS(regs->daif, 9, 0x1)]); 177 printf("\t%s\n", daif_bits_a[REG_BITS(regs->daif, 8, 0x1)]); 178 printf("\t%s\n", daif_bits_i[REG_BITS(regs->daif, 7, 0x1)]); 179 printf("\t%s\n", daif_bits_f[REG_BITS(regs->daif, 6, 0x1)]); 180 printf("\n"); 181 /* SPSR_ELx */ 182 printf("* SPSR_EL%d = %016lx\n", el, regs->spsr); 183 printf("\t%s\n", spsr_bits_d[REG_BITS(regs->spsr, 9, 0x1)]); 184 printf("\t%s\n", spsr_bits_a[REG_BITS(regs->spsr, 8, 0x1)]); 185 printf("\t%s\n", spsr_bits_i[REG_BITS(regs->spsr, 7, 0x1)]); 186 printf("\t%s\n", spsr_bits_f[REG_BITS(regs->spsr, 6, 0x1)]); 187 printf("\t%s\n", spsr_bits_m[REG_BITS(regs->spsr, 4, 0x1)]); 188 if (REG_BITS(regs->spsr, 4, 0x1)) 189 printf("\t%s\n", spsr_bits_m_aarch32[REG_BITS(regs->spsr, 0, 0xf)]); 190 else 191 printf("\t%s\n", spsr_bits_m_aarch64[REG_BITS(regs->spsr, 0, 0xf)]); 192 printf("\n"); 193 /* SCTLR_EL2 */ 194 printf("* SCTLR_EL%d = %016lx\n", el, regs->sctlr); 195 printf("\t%s\n", sctlr_bits_i[REG_BITS(regs->sctlr, 12, 0x1)]); 196 printf("\t%s\n", sctlr_bits_c[REG_BITS(regs->sctlr, 2, 0x1)]); 197 printf("\t%s\n", sctlr_bits_m[REG_BITS(regs->sctlr, 0, 0x1)]); 198 printf("\n"); 199 200 /* Other */ 201 if (el >= 2) 202 printf("* %s = %016lx\n", h_scr_name[el], regs->hcr); 203 printf("* VBAR_EL%d = %016lx\n", el, regs->vbar); 204 printf("* TTBR0_EL%d = %016lx\n", el, regs->ttbr0); 205 printf("\n"); 206 207 for (i = 0; i < 29; i += 2) 208 printf("x%-2d: %016lx x%-2d: %016lx\n", 209 i, regs->regs[i], i+1, regs->regs[i+1]); 210 211 printf("\n"); 212 iomem_show("SP", regs->sp, 0x00, 0xfc); 213 214 printf("\n"); 215 216 #ifdef CONFIG_ROCKCHIP_CRASH_DUMP 217 iomem_show_by_compatible("-cru", 0, 0x400); 218 iomem_show_by_compatible("-pmucru", 0, 0x400); 219 iomem_show_by_compatible("-grf", 0, 0x400); 220 iomem_show_by_compatible("-pmugrf", 0, 0x400); 221 /* tobe add here ... */ 222 #endif 223 dump_core_stack(regs); 224 } 225 226 #else 227 void show_regs(struct pt_regs *regs) 228 { 229 int i; 230 231 if (gd->flags & GD_FLG_RELOC) { 232 printf("ELR: %lx\n", regs->elr - gd->reloc_off); 233 printf("LR: %lx\n", regs->regs[30] - gd->reloc_off); 234 } else { 235 printf("ELR: %lx\n", regs->elr); 236 printf("LR: %lx\n", regs->regs[30]); 237 } 238 for (i = 0; i < 29; i += 2) 239 printf("x%-2d: %016lx x%-2d: %016lx\n", 240 i, regs->regs[i], i+1, regs->regs[i+1]); 241 printf("\n"); 242 243 dump_core_stack(regs); 244 } 245 #endif 246 247 /* 248 * do_bad_sync handles the impossible case in the Synchronous Abort vector. 249 */ 250 void do_bad_sync(struct pt_regs *pt_regs, unsigned int esr) 251 { 252 efi_restore_gd(); 253 printf("Bad mode in \"Synchronous Abort\" handler, esr 0x%08x\n", esr); 254 show_regs(pt_regs); 255 panic("Resetting CPU ...\n"); 256 } 257 258 /* 259 * do_bad_irq handles the impossible case in the Irq vector. 260 */ 261 void do_bad_irq(struct pt_regs *pt_regs, unsigned int esr) 262 { 263 efi_restore_gd(); 264 printf("Bad mode in \"Irq\" handler, esr 0x%08x\n", esr); 265 show_regs(pt_regs); 266 panic("Resetting CPU ...\n"); 267 } 268 269 /* 270 * do_bad_fiq handles the impossible case in the Fiq vector. 271 */ 272 void do_bad_fiq(struct pt_regs *pt_regs, unsigned int esr) 273 { 274 efi_restore_gd(); 275 printf("Bad mode in \"Fiq\" handler, esr 0x%08x\n", esr); 276 show_regs(pt_regs); 277 panic("Resetting CPU ...\n"); 278 } 279 280 /* 281 * do_bad_error handles the impossible case in the Error vector. 282 */ 283 void do_bad_error(struct pt_regs *pt_regs, unsigned int esr) 284 { 285 efi_restore_gd(); 286 printf("Bad mode in \"Error\" handler, esr 0x%08x\n", esr); 287 show_regs(pt_regs); 288 panic("Resetting CPU ...\n"); 289 } 290 291 /* 292 * do_sync handles the Synchronous Abort exception. 293 */ 294 void do_sync(struct pt_regs *pt_regs, unsigned int esr) 295 { 296 efi_restore_gd(); 297 printf("\"Synchronous Abort\" handler, esr 0x%08x\n", esr); 298 show_regs(pt_regs); 299 panic("Resetting CPU ...\n"); 300 } 301 302 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_IRQ) 303 /* 304 * do_irq handles the Irq exception. 305 */ 306 void do_irq(struct pt_regs *pt_regs, unsigned int esr) 307 { 308 efi_restore_gd(); 309 printf("\"Irq\" handler, esr 0x%08x\n", esr); 310 show_regs(pt_regs); 311 panic("Resetting CPU ...\n"); 312 } 313 #endif 314 315 /* 316 * do_fiq handles the Fiq exception. 317 */ 318 void do_fiq(struct pt_regs *pt_regs, unsigned int esr) 319 { 320 efi_restore_gd(); 321 printf("\"Fiq\" handler, esr 0x%08x\n", esr); 322 show_regs(pt_regs); 323 panic("Resetting CPU ...\n"); 324 } 325 326 /* 327 * do_error handles the Error exception. 328 * Errors are more likely to be processor specific, 329 * it is defined with weak attribute and can be redefined 330 * in processor specific code. 331 */ 332 void __weak do_error(struct pt_regs *pt_regs, unsigned int esr) 333 { 334 efi_restore_gd(); 335 printf("\"Error\" handler, esr 0x%08x\n", esr); 336 show_regs(pt_regs); 337 panic("Resetting CPU ...\n"); 338 } 339