1# 2# Multifunction miscellaneous devices 3# 4 5menu "Multifunction device drivers" 6 7config MISC 8 bool "Enable Driver Model for Misc drivers" 9 depends on DM 10 help 11 Enable driver model for miscellaneous devices. This class is 12 used only for those do not fit other more general classes. A 13 set of generic read, write and ioctl methods may be used to 14 access the device. 15 16config ALTERA_SYSID 17 bool "Altera Sysid support" 18 depends on MISC 19 help 20 Select this to enable a sysid for Altera devices. Please find 21 details on the "Embedded Peripherals IP User Guide" of Altera. 22 23config ATSHA204A 24 bool "Support for Atmel ATSHA204A module" 25 depends on MISC 26 help 27 Enable support for I2C connected Atmel's ATSHA204A 28 CryptoAuthentication module found for example on the Turris Omnia 29 board. 30 31config ROCKCHIP_EFUSE 32 bool "Rockchip e-fuse support" 33 depends on MISC 34 help 35 Enable (read-only) access for the e-fuse block found in Rockchip 36 SoCs: accesses can either be made using byte addressing and a length 37 or through child-nodes that are generated based on the e-fuse map 38 retrieved from the DTS. 39 40 This driver currently supports the RK3399 only, but can easily be 41 extended (by porting the read function from the Linux kernel sources) 42 to support other recent Rockchip devices. 43 44config ROCKCHIP_OTP 45 bool "Rockchip OTP Support" 46 depends on MISC 47 help 48 This is a simple drive to dump specified values of Rockchip SoC 49 from otp, such as cpu-leakage. 50 51config CMD_CROS_EC 52 bool "Enable crosec command" 53 depends on CROS_EC 54 help 55 Enable command-line access to the Chrome OS EC (Embedded 56 Controller). This provides the 'crosec' command which has 57 a number of sub-commands for performing EC tasks such as 58 updating its flash, accessing a small saved context area 59 and talking to the I2C bus behind the EC (if there is one). 60 61config CROS_EC 62 bool "Enable Chrome OS EC" 63 help 64 Enable access to the Chrome OS EC. This is a separate 65 microcontroller typically available on a SPI bus on Chromebooks. It 66 provides access to the keyboard, some internal storage and may 67 control access to the battery and main PMIC depending on the 68 device. You can use the 'crosec' command to access it. 69 70config CROS_EC_I2C 71 bool "Enable Chrome OS EC I2C driver" 72 depends on CROS_EC 73 help 74 Enable I2C access to the Chrome OS EC. This is used on older 75 ARM Chromebooks such as snow and spring before the standard bus 76 changed to SPI. The EC will accept commands across the I2C using 77 a special message protocol, and provide responses. 78 79config CROS_EC_LPC 80 bool "Enable Chrome OS EC LPC driver" 81 depends on CROS_EC 82 help 83 Enable I2C access to the Chrome OS EC. This is used on x86 84 Chromebooks such as link and falco. The keyboard is provided 85 through a legacy port interface, so on x86 machines the main 86 function of the EC is power and thermal management. 87 88config CROS_EC_SANDBOX 89 bool "Enable Chrome OS EC sandbox driver" 90 depends on CROS_EC && SANDBOX 91 help 92 Enable a sandbox emulation of the Chrome OS EC. This supports 93 keyboard (use the -l flag to enable the LCD), verified boot context, 94 EC flash read/write/erase support and a few other things. It is 95 enough to perform a Chrome OS verified boot on sandbox. 96 97config CROS_EC_SPI 98 bool "Enable Chrome OS EC SPI driver" 99 depends on CROS_EC 100 help 101 Enable SPI access to the Chrome OS EC. This is used on newer 102 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 103 provides a faster and more robust interface than I2C but the bugs 104 are less interesting. 105 106config DS4510 107 bool "Enable support for DS4510 CPU supervisor" 108 help 109 Enable support for the Maxim DS4510 CPU supervisor. It has an 110 integrated 64-byte EEPROM, four programmable non-volatile I/O pins 111 and a configurable timer for the supervisor function. The device is 112 connected over I2C. 113 114config FSL_SEC_MON 115 bool "Enable FSL SEC_MON Driver" 116 help 117 Freescale Security Monitor block is responsible for monitoring 118 system states. 119 Security Monitor can be transitioned on any security failures, 120 like software violations or hardware security violations. 121 122config MXC_OCOTP 123 bool "Enable MXC OCOTP Driver" 124 help 125 If you say Y here, you will get support for the One Time 126 Programmable memory pages that are stored on the some 127 Freescale i.MX processors. 128 129config NUVOTON_NCT6102D 130 bool "Enable Nuvoton NCT6102D Super I/O driver" 131 help 132 If you say Y here, you will get support for the Nuvoton 133 NCT6102D Super I/O driver. This can be used to enable or 134 disable the legacy UART, the watchdog or other devices 135 in the Nuvoton Super IO chips on X86 platforms. 136 137config PWRSEQ 138 bool "Enable power-sequencing drivers" 139 depends on DM 140 help 141 Power-sequencing drivers provide support for controlling power for 142 devices. They are typically referenced by a phandle from another 143 device. When the device is started up, its power sequence can be 144 initiated. 145 146config SPL_PWRSEQ 147 bool "Enable power-sequencing drivers for SPL" 148 depends on PWRSEQ 149 help 150 Power-sequencing drivers provide support for controlling power for 151 devices. They are typically referenced by a phandle from another 152 device. When the device is started up, its power sequence can be 153 initiated. 154 155config PCA9551_LED 156 bool "Enable PCA9551 LED driver" 157 help 158 Enable driver for PCA9551 LED controller. This controller 159 is connected via I2C. So I2C needs to be enabled. 160 161config PCA9551_I2C_ADDR 162 hex "I2C address of PCA9551 LED controller" 163 depends on PCA9551_LED 164 default 0x60 165 help 166 The I2C address of the PCA9551 LED controller. 167 168config TEGRA_CAR 169 bool "Enable support for the Tegra CAR driver" 170 depends on TEGRA_NO_BPMP 171 help 172 The Tegra CAR (Clock and Reset Controller) is a HW module that 173 controls almost all clocks and resets in a Tegra SoC. 174 175config TEGRA186_BPMP 176 bool "Enable support for the Tegra186 BPMP driver" 177 depends on TEGRA186 178 help 179 The Tegra BPMP (Boot and Power Management Processor) is a separate 180 auxiliary CPU embedded into Tegra to perform power management work, 181 and controls related features such as clocks, resets, power domains, 182 PMIC I2C bus, etc. This driver provides the core low-level 183 communication path by which feature-specific drivers (such as clock) 184 can make requests to the BPMP. This driver is similar to an MFD 185 driver in the Linux kernel. 186 187config WINBOND_W83627 188 bool "Enable Winbond Super I/O driver" 189 help 190 If you say Y here, you will get support for the Winbond 191 W83627 Super I/O driver. This can be used to enable the 192 legacy UART or other devices in the Winbond Super IO chips 193 on X86 platforms. 194 195config QFW 196 bool 197 help 198 Hidden option to enable QEMU fw_cfg interface. This will be selected by 199 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 200 201config I2C_EEPROM 202 bool "Enable driver for generic I2C-attached EEPROMs" 203 depends on MISC 204 help 205 Enable a generic driver for EEPROMs attached via I2C. 206 207if I2C_EEPROM 208 209config SYS_I2C_EEPROM_ADDR 210 hex "Chip address of the EEPROM device" 211 default 0 212 213config SYS_I2C_EEPROM_BUS 214 int "I2C bus of the EEPROM device." 215 default 0 216 217config SYS_EEPROM_SIZE 218 int "Size in bytes of the EEPROM device" 219 default 256 220 221config SYS_EEPROM_PAGE_WRITE_BITS 222 int "Number of bits used to address bytes in a single page" 223 default 0 224 help 225 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 226 A 64 byte page, for example would require six bits. 227 228config SYS_EEPROM_PAGE_WRITE_DELAY_MS 229 int "Number of milliseconds to delay between page writes" 230 default 0 231 232config SYS_I2C_EEPROM_ADDR_LEN 233 int "Length in bytes of the EEPROM memory array address" 234 default 1 235 help 236 Note: This is NOT the chip address length! 237 238config SYS_I2C_EEPROM_ADDR_OVERFLOW 239 hex "EEPROM Address Overflow" 240 default 0 241 help 242 EEPROM chips that implement "address overflow" are ones 243 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 244 address and the extra bits end up in the "chip address" bit 245 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 246 byte chips. 247 248endif 249 250 251endmenu 252