refactor(guid-partition): list.entry_count to unsigned int

Change list.entry_count to unsigned int to align with header.list_num,
removing the need for casting.

Change-Id: Id4259d9e841c8d34fe23fb74

refactor(guid-partition): list.entry_count to unsigned int

Change list.entry_count to unsigned int to align with header.list_num,
removing the need for casting.

Change-Id: Id4259d9e841c8d34fe23fb74a7c627f2a643cbf2
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Merge "refactor(mbedtls): remove mbedtls 2.x support" into integration

Merge "refactor(sdei): use common create_spsr() in SDEI library" into integration

refactor(mbedtls): remove mbedtls 2.x support

Deprecation notice was sent to the community and no objection was
raised, so removing mbedtls 2.x support.

Change-Id: Id3eb98b55692df98aabe6a7c5a5ec910

refactor(mbedtls): remove mbedtls 2.x support

Deprecation notice was sent to the community and no objection was
raised, so removing mbedtls 2.x support.

Change-Id: Id3eb98b55692df98aabe6a7c5a5ec910222c8abd
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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feat(rme): build TF-A with ENABLE_RME for Armv9.2

FEAT_RME is OPTIONAL in an Armv9.2 implementation,
so set ARM_ARCH_MAJOR := 9 and ARM_ARCH_MINOR := 2
when TF-A is built with 'ENABLE_RME = 1'.

Cha

feat(rme): build TF-A with ENABLE_RME for Armv9.2

FEAT_RME is OPTIONAL in an Armv9.2 implementation,
so set ARM_ARCH_MAJOR := 9 and ARM_ARCH_MINOR := 2
when TF-A is built with 'ENABLE_RME = 1'.

Change-Id: Ibcdb23bd057983eb846eed0b0da8c4d72ed696ae
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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docs(maintainers): add missing ST files

The files under tools/fiptool/plat_fiptool/st/ directory were not listed
as files maintained by STMicroelectronics.

Signed-off-by: Yann Gautier <yann.gautier

docs(maintainers): add missing ST files

The files under tools/fiptool/plat_fiptool/st/ directory were not listed
as files maintained by STMicroelectronics.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I4120368253447d4dadc4ce4b6957ffbe6310da86

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docs(maintainers): add Maxime as co-maintainer for ST platforms

Add Maxime Méré as a co-maintainer for STMicroelectronics platforms.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I05

docs(maintainers): add Maxime as co-maintainer for ST platforms

Add Maxime Méré as a co-maintainer for STMicroelectronics platforms.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I05dda2049000d99f0e482492ec43d02ad1d5d0c8

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docs(maintainers): update ST platform ports title

STM32MP1 is no more the only product to be supported in TF-A with the
new STM32MP2. Change "STM32MP1 platform port" to "STMicroelectronics
platform

docs(maintainers): update ST platform ports title

STM32MP1 is no more the only product to be supported in TF-A with the
new STM32MP2. Change "STM32MP1 platform port" to "STMicroelectronics
platform ports" to better reflect this.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I30b1fd4310d38092e3e815cb635b474fc84bdc30

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docs(maintainers): sort github aliases

The aliases for github were added either by alphabetical order or at the
end of list. Sort them alphabetically with Linux sort tool, regardless
of uppercase/lo

docs(maintainers): sort github aliases

The aliases for github were added either by alphabetical order or at the
end of list. Sort them alphabetically with Linux sort tool, regardless
of uppercase/lowercase letters.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ia247e102ab5fb0f7b8b6de76f23a869cc3f83d2c

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Merge "fix(cpus): fix a defect in Cortex-A715 erratum 2561034" into integration

feat(rpi5): add PCI SMCCC support

BCM2712 changes:
- support all 3 PCIe RCs / segments.
- don't check for link up: the RC can now be configured to fabricate
all-ones AXI OKAY responses, so no mo

feat(rpi5): add PCI SMCCC support

BCM2712 changes:
- support all 3 PCIe RCs / segments.
- don't check for link up: the RC can now be configured to fabricate
all-ones AXI OKAY responses, so no more Arm SErrors when the link is
down (or other conditions).

Also, limit bus 0 to devfn 0 as accesses beyond that may result in
lock-ups.

Change-Id: Ic64785cd68b22571c6638fc3f771703113bc76f6
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>

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style(imx8m): add parenthesis to CSU_HP_REG

To be inline with CSU_SA_REG and CSU_HPCONTROL_REG.

Change-Id: Ia7332096312df41a8cf994d58fad76a99493dd02
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengu

style(imx8m): add parenthesis to CSU_HP_REG

To be inline with CSU_SA_REG and CSU_HPCONTROL_REG.

Change-Id: Ia7332096312df41a8cf994d58fad76a99493dd02
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>

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feat(imx8mp): restrict peripheral access to secure world

This restricts and locks all security relevant peripherals to only be
changeable by the secure world. Otherwise the normal world can simply
c

feat(imx8mp): restrict peripheral access to secure world

This restricts and locks all security relevant peripherals to only be
changeable by the secure world. Otherwise the normal world can simply
change the access settings and defeat all security measures put in
place.

Change-Id: I248ef8dd67f1de7e528c3da456311bb138b77540
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>

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feat(imx8mp): set and lock almost all peripherals as non-secure

This sets and locks all peripheral type-1 masters, except CAAM, access
as non-secure, so that they can't access secure world resources

feat(imx8mp): set and lock almost all peripherals as non-secure

This sets and locks all peripheral type-1 masters, except CAAM, access
as non-secure, so that they can't access secure world resources from the
normal world.

The CAAM itself is TrustZone aware and handles memory access between the
normal world and the secure world on its own. Pinning it as non-secure
access results in bus aborts if the secure memory region is protected by
the TZASC380.

Change-Id: Iedf3d67481dc35d56aa7b291749b999a56d6e85e
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>

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feat(imx8mm): restrict peripheral access to secure world

This restricts and locks all security relevant peripherals to only be
changeable by the secure world. Otherwise the normal world can simply
c

feat(imx8mm): restrict peripheral access to secure world

This restricts and locks all security relevant peripherals to only be
changeable by the secure world. Otherwise the normal world can simply
change the access settings and defeat all security measures put in
place.

Change-Id: I484a2c8164e58b68256d829470e00d5ec473e266
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>

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feat(imx8mm): set and lock almost all peripherals as non-secure

This sets and locks all peripheral type-1 masters, except CAAM, access
as non-secure, so that they can't access secure world resources

feat(imx8mm): set and lock almost all peripherals as non-secure

This sets and locks all peripheral type-1 masters, except CAAM, access
as non-secure, so that they can't access secure world resources from the
normal world.

The CAAM itself is TrustZone aware and handles memory access between the
normal world and the secure world on its own. Pinning it as non-secure
access results in bus aborts if the secure memory region is protected by
the TZASC380.

Change-Id: Idba4d8a491ccce0491489c61e73545baab1889c4
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>

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Merge "fix(cpus): workaround for Cortex-A715 erratum 2413290" into integration

fix(cpus): fix a defect in Cortex-A715 erratum 2561034

Cortex-A715 erratum 2561034 mitigation needs to be applied
during reset. This patch fixes the current macro usage from runtime
to reset for bot

fix(cpus): fix a defect in Cortex-A715 erratum 2561034

Cortex-A715 erratum 2561034 mitigation needs to be applied
during reset. This patch fixes the current macro usage from runtime
to reset for both start and end macros.

Change-Id: I4f115bbb27c57f16cada2a7eb314af8380f93cb4
Signed-off-by: Bipin Ravi <biprav01@u203721.austin.arm.com>

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fix(cpus): workaround for Cortex-A715 erratum 2413290

Cortex-A715 erratum 2413290 is a Cat B erratum that is present
only in revision r1p0 and is fixed in r1p1. The errata is only
present when SPE(S

fix(cpus): workaround for Cortex-A715 erratum 2413290

Cortex-A715 erratum 2413290 is a Cat B erratum that is present
only in revision r1p0 and is fixed in r1p1. The errata is only
present when SPE(Statistical Profiling Extension) is enabled.

The workaround is to set bits[58:57] of the CPUACTLR_EL1 to 'b11
when SPE is enabled, ENABLE_SPE_FOR_NS=1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2148827/latest

Change-Id: Iaeb258c8b0a92e93d70b7dad6ba59d1056aeb135
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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docs: remove entries of the deleted platforms

Remove the details of the platforms from the 'deprecated
platforms' table those are already deleted.
This is in-sync with other depreaction tables [1] w

docs: remove entries of the deleted platforms

Remove the details of the platforms from the 'deprecated
platforms' table those are already deleted.
This is in-sync with other depreaction tables [1] which
only has deprecation entries and not deleted entries.

[1]: https://trustedfirmware-a.readthedocs.io/en/latest/about/release-information.html#removal-of-deprecated-interfaces

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: If8c8e4ba4e7fa88ea83632202d17c7d35cdc200a

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feat(rpi): add Raspberry Pi 5 support

The Raspberry Pi 5 is a single-board computer based on BCM2712 that
contains four Arm Cortex-A76 cores.

This change introduces minimal BL31 support with PSCI t

feat(rpi): add Raspberry Pi 5 support

The Raspberry Pi 5 is a single-board computer based on BCM2712 that
contains four Arm Cortex-A76 cores.

This change introduces minimal BL31 support with PSCI that has been
validated to boot Linux and a private EDK2 build.

It's a drop-in replacement for the custom TF-A armstub now included in
the EEPROM images.

Change-Id: Id72a0370f54e71ac97c3daa1bacedacb7dec148f
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>

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fix(rpi): consider MT when calculating core index from MPIDR

RPi 5 has newer Armv8.2 cores where the MT bit is set to indicate that
the lowest affinity level represents a thread, but there is only o

fix(rpi): consider MT when calculating core index from MPIDR

RPi 5 has newer Armv8.2 cores where the MT bit is set to indicate that
the lowest affinity level represents a thread, but there is only one
thread per core.

To deal with this, simply right shift MPIDR by one affinity level to get
the cluster and core IDs back into Aff1 and Aff0 as expected.

Change-Id: I2bafba38f82fd9a6ef6f2fdf2c089b754279a6de
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>

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refactor(rpi): move register definitions out of rpi_hw.h

Change-Id: I2bd48441359468efb9e94fd2fffb079683f7a7fd
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>

refactor(rpi): add platform macro for the crash UART base address

Change-Id: I164c579cbf7c26547a47794cd80152e13fd1937b
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>

refactor(rpi): split out console registration logic

Detection of the UART in use and GPIO code only apply to RPi 3 and 4.

RPi 5 has a dedicated PL011 debug port.

Change-Id: Iddf8aea01278e2b79b4e7c

refactor(rpi): split out console registration logic

Detection of the UART in use and GPIO code only apply to RPi 3 and 4.

RPi 5 has a dedicated PL011 debug port.

Change-Id: Iddf8aea01278e2b79b4e7c476740f1add8c419f0
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>

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