1/* 2 * Copyright (c) 2023-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#define STDOUT_PATH "serial0:115200n8" 8#define GIC_CTRL_ADDR 2c010000 9#define GIC_GICR_OFFSET 0x200000 10#define UART_OFFSET 0x1000 11#define VENCODER_TIMING_CLK 25175000 12#define VENCODER_TIMING \ 13 clock-frequency = <VENCODER_TIMING_CLK>; \ 14 hactive = <640>; \ 15 vactive = <480>; \ 16 hfront-porch = <16>; \ 17 hback-porch = <48>; \ 18 hsync-len = <96>; \ 19 vfront-porch = <10>; \ 20 vback-porch = <33>; \ 21 vsync-len = <2> 22#define ETH_COMPATIBLE "smsc,lan91c111" 23#define MMC_REMOVABLE cd-gpios = <&sysreg 0 0> 24 25/ { 26 rtc@1c170000 { 27 compatible = "arm,pl031", "arm,primecell"; 28 reg = <0x0 0x1C170000 0x0 0x1000>; 29 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 30 clocks = <&soc_refclk>; 31 clock-names = "apb_pclk"; 32 }; 33 34 kmi@1c060000 { 35 compatible = "arm,pl050", "arm,primecell"; 36 reg = <0x0 0x001c060000 0x0 0x1000>; 37 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 38 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; 39 clock-names = "KMIREFCLK", "apb_pclk"; 40 }; 41 42 kmi@1c070000 { 43 compatible = "arm,pl050", "arm,primecell"; 44 reg = <0x0 0x001c070000 0x0 0x1000>; 45 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 46 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; 47 clock-names = "KMIREFCLK", "apb_pclk"; 48 }; 49 50 virtio_block@1c130000 { 51 compatible = "virtio,mmio"; 52 reg = <0x0 0x1c130000 0x0 0x200>; 53 /* spec lists this wrong */ 54 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 55 }; 56}; 57