1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/* If SCMI power domain control is enabled */ 8#if TC_SCMI_PD_CTRL_EN 9#define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1) 10#define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2) 11#endif /* TC_SCMI_PD_CTRL_EN */ 12 13/* Use SCMI controlled clocks */ 14#if TC_DPU_USE_SCMI_CLK 15#define DPU_CLK_ATTR1 \ 16 clocks = <&scmi_clk 0>; \ 17 clock-names = "aclk" 18 19#define DPU_CLK_ATTR2 \ 20 clocks = <&scmi_clk 1>; \ 21 clock-names = "pxclk" 22 23#define DPU_CLK_ATTR3 \ 24 clocks = <&scmi_clk 2>; \ 25 clock-names = "pxclk" \ 26/* Use fixed clocks */ 27#else /* !TC_DPU_USE_SCMI_CLK */ 28#define DPU_CLK_ATTR1 \ 29 clocks = <&dpu_aclk>; \ 30 clock-names = "aclk" 31 32#define DPU_CLK_ATTR2 \ 33 clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \ 34 clock-names = "pxclk", "aclk" 35 36#define DPU_CLK_ATTR3 DPU_CLK_ATTR2 37#endif /* !TC_DPU_USE_SCMI_CLK */ 38 39/ { 40 compatible = "arm,tc"; 41 interrupt-parent = <&gic>; 42 #address-cells = <2>; 43 #size-cells = <2>; 44 45 aliases { 46 serial0 = &os_uart; 47 }; 48 49 chosen { 50 stdout-path = STDOUT_PATH; 51 /* 52 * Add some dummy entropy for Linux so it 53 * doesn't delay the boot waiting for it. 54 */ 55 rng-seed = <0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 56 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 57 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 58 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 59 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 60 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 61 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 62 0x01 0x02 0x04 0x05 0x06 0x07 0x08 >; 63 }; 64 65 cpus { 66 #address-cells = <1>; 67 #size-cells = <0>; 68 69 cpu-map { 70 cluster0 { 71 core0 { 72 cpu = <&CPU0>; 73 }; 74 core1 { 75 cpu = <&CPU1>; 76 }; 77 core2 { 78 cpu = <&CPU2>; 79 }; 80 core3 { 81 cpu = <&CPU3>; 82 }; 83 core4 { 84 cpu = <&CPU4>; 85 }; 86 core5 { 87 cpu = <&CPU5>; 88 }; 89 core6 { 90 cpu = <&CPU6>; 91 }; 92 core7 { 93 cpu = <&CPU7>; 94 }; 95 }; 96 }; 97 98 /* 99 * The timings below are just to demonstrate working cpuidle. 100 * These values may be inaccurate. 101 */ 102 idle-states { 103 entry-method = "psci"; 104 105 CPU_SLEEP_0: cpu-sleep-0 { 106 compatible = "arm,idle-state"; 107 arm,psci-suspend-param = <0x0010000>; 108 local-timer-stop; 109 entry-latency-us = <300>; 110 exit-latency-us = <1200>; 111 min-residency-us = <2000>; 112 }; 113 CLUSTER_SLEEP_0: cluster-sleep-0 { 114 compatible = "arm,idle-state"; 115 arm,psci-suspend-param = <0x1010000>; 116 local-timer-stop; 117 entry-latency-us = <400>; 118 exit-latency-us = <1200>; 119 min-residency-us = <2500>; 120 }; 121 }; 122 123 amus { 124 amu: amu-0 { 125 #address-cells = <1>; 126 #size-cells = <0>; 127 128 mpmm_gear0: counter@0 { 129 reg = <0>; 130 enable-at-el3; 131 }; 132 133 mpmm_gear1: counter@1 { 134 reg = <1>; 135 enable-at-el3; 136 }; 137 138 mpmm_gear2: counter@2 { 139 reg = <2>; 140 enable-at-el3; 141 }; 142 }; 143 }; 144 145 CPU0:cpu@0 { 146 device_type = "cpu"; 147 compatible = "arm,armv8"; 148 reg = <0x0>; 149 enable-method = "psci"; 150 clocks = <&scmi_dvfs 0>; 151 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 152 capacity-dmips-mhz = <LIT_CAPACITY>; 153 amu = <&amu>; 154 supports-mpmm; 155 }; 156 157 CPU1:cpu@100 { 158 device_type = "cpu"; 159 compatible = "arm,armv8"; 160 reg = <0x100>; 161 enable-method = "psci"; 162 clocks = <&scmi_dvfs 0>; 163 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 164 capacity-dmips-mhz = <LIT_CAPACITY>; 165 amu = <&amu>; 166 supports-mpmm; 167 }; 168 169 CPU2:cpu@200 { 170 device_type = "cpu"; 171 compatible = "arm,armv8"; 172 reg = <0x200>; 173 enable-method = "psci"; 174 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 175 amu = <&amu>; 176 supports-mpmm; 177 }; 178 179 CPU3:cpu@300 { 180 device_type = "cpu"; 181 compatible = "arm,armv8"; 182 reg = <0x300>; 183 enable-method = "psci"; 184 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 185 amu = <&amu>; 186 supports-mpmm; 187 }; 188 189 CPU4:cpu@400 { 190 device_type = "cpu"; 191 compatible = "arm,armv8"; 192 reg = <0x400>; 193 enable-method = "psci"; 194 clocks = <&scmi_dvfs 1>; 195 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 196 capacity-dmips-mhz = <MID_CAPACITY>; 197 amu = <&amu>; 198 supports-mpmm; 199 }; 200 201 CPU5:cpu@500 { 202 device_type = "cpu"; 203 compatible = "arm,armv8"; 204 reg = <0x500>; 205 enable-method = "psci"; 206 clocks = <&scmi_dvfs 1>; 207 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 208 capacity-dmips-mhz = <MID_CAPACITY>; 209 amu = <&amu>; 210 supports-mpmm; 211 }; 212 213 CPU6:cpu@600 { 214 device_type = "cpu"; 215 compatible = "arm,armv8"; 216 reg = <0x600>; 217 enable-method = "psci"; 218 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 219 amu = <&amu>; 220 supports-mpmm; 221 }; 222 223 CPU7:cpu@700 { 224 device_type = "cpu"; 225 compatible = "arm,armv8"; 226 reg = <0x700>; 227 enable-method = "psci"; 228 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 229 amu = <&amu>; 230 supports-mpmm; 231 }; 232 }; 233 234 reserved-memory { 235 #address-cells = <2>; 236 #size-cells = <2>; 237 ranges; 238 239 linux,cma { 240 compatible = "shared-dma-pool"; 241 reusable; 242 size = <0x0 0x8000000>; 243 linux,cma-default; 244 }; 245 246 optee { 247 compatible = "restricted-dma-pool"; 248 reg = <0x0 TC_NS_OPTEE_BASE 0x0 TC_NS_OPTEE_SIZE>; 249 }; 250 251 fwu_mm { 252 reg = <0x0 TC_NS_FWU_BASE 0x0 TC_NS_FWU_SIZE>; 253 no-map; 254 }; 255 }; 256 257 memory { 258 device_type = "memory"; 259 reg = <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>, 260 <HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE) 261 HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>; 262 }; 263 264 psci { 265 compatible = "arm,psci-1.0", "arm,psci-0.2"; 266 method = "smc"; 267 }; 268 269 cpu-pmu { 270 compatible = "arm,armv8-pmuv3"; 271 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 272 }; 273 274 sram: sram@6000000 { 275 compatible = "mmio-sram"; 276 reg = <0x0 PLAT_ARM_NSRAM_BASE 0x0 PLAT_ARM_NSRAM_SIZE>; 277 278 #address-cells = <1>; 279 #size-cells = <1>; 280 ranges = <0 0x0 PLAT_ARM_NSRAM_BASE PLAT_ARM_NSRAM_SIZE>; 281 282 cpu_scp_scmi_mem: scp-shmem@0 { 283 compatible = "arm,scmi-shmem"; 284 reg = <0x0 0x80>; 285 }; 286 }; 287 288 mbox_db_rx: mhu@MHU_RX_ADDR { 289 compatible = "arm,mhuv2-rx","arm,primecell"; 290 reg = <0x0 ADDRESSIFY(MHU_RX_ADDR) 0x0 0x1000>; 291 clocks = <&soc_refclk>; 292 clock-names = "apb_pclk"; 293 #mbox-cells = <2>; 294 interrupts = <GIC_SPI INT_MBOX_RX IRQ_TYPE_LEVEL_HIGH>; 295 interrupt-names = "mhu_rx"; 296 mhu-protocol = "doorbell"; 297 arm,mhuv2-protocols = <0 1>; 298 }; 299 300 mbox_db_tx: mhu@MHU_TX_ADDR { 301 compatible = "arm,mhuv2-tx","arm,primecell"; 302 reg = <0x0 ADDRESSIFY(MHU_TX_ADDR) 0x0 0x1000>; 303 clocks = <&soc_refclk>; 304 clock-names = "apb_pclk"; 305 #mbox-cells = <2>; 306 interrupt-names = "mhu_tx"; 307 mhu-protocol = "doorbell"; 308 arm,mhuv2-protocols = <0 1>; 309 }; 310 311 scmi { 312 compatible = "arm,scmi"; 313 mbox-names = "tx", "rx"; 314 mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >; 315 shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 319#if TC_SCMI_PD_CTRL_EN 320 scmi_devpd: protocol@11 { 321 reg = <0x11>; 322 #power-domain-cells = <1>; 323 }; 324#endif /* TC_SCMI_PD_CTRL_EN */ 325 326 scmi_dvfs: protocol@13 { 327 reg = <0x13>; 328 #clock-cells = <1>; 329 }; 330 331 scmi_clk: protocol@14 { 332 reg = <0x14>; 333 #clock-cells = <1>; 334 }; 335 }; 336 337 gic: interrupt-controller@GIC_CTRL_ADDR { 338 compatible = "arm,gic-v3"; 339 #address-cells = <2>; 340 #interrupt-cells = <3>; 341 #size-cells = <2>; 342 ranges; 343 interrupt-controller; 344 reg = <0x0 0x30000000 0 0x10000>, /* GICD */ 345 <0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */ 346 interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW>; 347 }; 348 349 timer { 350 compatible = "arm,armv8-timer"; 351 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 352 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 353 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 354 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 355 }; 356 357 soc_refclk: refclk { 358 compatible = "fixed-clock"; 359 #clock-cells = <0>; 360 clock-frequency = <1000000000>; 361 clock-output-names = "apb_pclk"; 362 }; 363 364 soc_refclk60mhz: refclk60mhz { 365 compatible = "fixed-clock"; 366 #clock-cells = <0>; 367 clock-frequency = <60000000>; 368 clock-output-names = "iofpga_clk"; 369 }; 370 371 soc_uartclk: uartclk { 372 compatible = "fixed-clock"; 373 #clock-cells = <0>; 374 clock-frequency = <UARTCLK_FREQ>; 375 clock-output-names = "uartclk"; 376 }; 377 378 /* soc_uart0 on FPGA, ap_ns_uart on FVP */ 379 os_uart: serial@2a400000 { 380 compatible = "arm,pl011", "arm,primecell"; 381 reg = <0x0 0x2A400000 0x0 UART_OFFSET>; 382 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&soc_uartclk>, <&soc_refclk>; 384 clock-names = "uartclk", "apb_pclk"; 385 status = "okay"; 386 }; 387 388#if !TC_DPU_USE_SCMI_CLK 389 dpu_aclk: dpu_aclk { 390 compatible = "fixed-clock"; 391 #clock-cells = <0>; 392 clock-frequency = <VENCODER_TIMING_CLK>; 393 clock-output-names = "fpga:dpu_aclk"; 394 }; 395 396 dpu_pixel_clk: dpu-pixel-clk { 397 compatible = "fixed-clock"; 398 #clock-cells = <0>; 399 clock-frequency = <VENCODER_TIMING_CLK>; 400 clock-output-names = "pxclk"; 401 }; 402#endif /* !TC_DPU_USE_SCMI_CLK */ 403 404 vencoder { 405 compatible = "drm,virtual-encoder"; 406 port { 407 vencoder_in: endpoint { 408 remote-endpoint = <&dp_pl0_out0>; 409 }; 410 }; 411 412 display-timings { 413 timing-panel { 414 VENCODER_TIMING; 415 }; 416 }; 417 418 }; 419 420 ethernet@18000000 { 421 compatible = ETH_COMPATIBLE; 422 reg = <0x0 0x18000000 0x0 0x10000>; 423 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 424 425 /* FPGA only but will work on FVP. Keep for simplicity */ 426 phy-mode = "mii"; 427 reg-io-width = <2>; 428 smsc,irq-push-pull; 429 }; 430 431 bp_clock24mhz: clock24mhz { 432 compatible = "fixed-clock"; 433 #clock-cells = <0>; 434 clock-frequency = <24000000>; 435 clock-output-names = "bp:clock24mhz"; 436 }; 437 438 439 sysreg: sysreg@1c010000 { 440 compatible = "arm,vexpress-sysreg"; 441 reg = <0x0 0x001c010000 0x0 0x1000>; 442 gpio-controller; 443 #gpio-cells = <2>; 444 }; 445 446 fixed_3v3: v2m-3v3 { 447 compatible = "regulator-fixed"; 448 regulator-name = "3V3"; 449 regulator-min-microvolt = <3300000>; 450 regulator-max-microvolt = <3300000>; 451 regulator-always-on; 452 }; 453 454 mmci@1c050000 { 455 compatible = "arm,pl180", "arm,primecell"; 456 reg = <0x0 0x001c050000 0x0 0x1000>; 457 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 459 MMC_REMOVABLE; 460 wp-gpios = <&sysreg 1 0>; 461 bus-width = <4>; 462 max-frequency = <25000000>; 463 vmmc-supply = <&fixed_3v3>; 464 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; 465 clock-names = "mclk", "apb_pclk"; 466 }; 467 468 gpu_clk: gpu_clk { 469 compatible = "fixed-clock"; 470 #clock-cells = <0>; 471 clock-frequency = <1000000000>; 472 }; 473 474 gpu_core_clk: gpu_core_clk { 475 compatible = "fixed-clock"; 476 #clock-cells = <0>; 477 clock-frequency = <1000000000>; 478 }; 479 480 gpu: gpu@2d000000 { 481 compatible = "arm,mali-midgard"; 482 reg = <0x0 0x2d000000 0x0 0x200000>; 483 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 486 interrupt-names = "JOB", "MMU", "GPU"; 487 clocks = <&gpu_core_clk>; 488 clock-names = "shadercores"; 489#if TC_SCMI_PD_CTRL_EN 490 power-domains = <&scmi_devpd GPU_SCMI_PD_IDX>; 491 scmi-perf-domain = <3>; 492#endif /* TC_SCMI_PD_CTRL_EN */ 493 494#if TC_IOMMU_EN 495 iommus = <&smmu_700 0x200>; 496#endif /* TC_IOMMU_EN */ 497 }; 498 499 power_model_simple { 500 /* 501 * Numbers used are irrelevant to Titan, 502 * it helps suppressing the kernel warnings. 503 */ 504 compatible = "arm,mali-simple-power-model"; 505 static-coefficient = <2427750>; 506 dynamic-coefficient = <4687>; 507 ts = <20000 2000 (-20) 2>; 508 thermal-zone = ""; 509 }; 510 511#if TC_IOMMU_EN 512 smmu_700: iommu@3f000000 { 513 #iommu-cells = <1>; 514 compatible = "arm,smmu-v3"; 515 reg = <0x0 0x3f000000 0x0 0x5000000>; 516 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 517 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, 518 <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>; 519 interrupt-names = "eventq", "cmdq-sync", "gerror"; 520 dma-coherent; 521 }; 522#endif /* TC_IOMMU_EN */ 523 524 dp0: display@DPU_ADDR { 525 #address-cells = <1>; 526 #size-cells = <0>; 527 compatible = "arm,mali-d71"; 528 reg = <HI(ADDRESSIFY(DPU_ADDR)) LO(ADDRESSIFY(DPU_ADDR)) 0 0x20000>; 529 interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH>; 530 interrupt-names = "DPU"; 531 DPU_CLK_ATTR1; 532#if TC_IOMMU_EN 533 iommus = <&smmu_700 0x100>; 534#endif /* TC_IOMMU_EN */ 535 536 pl0: pipeline@0 { 537 reg = <0>; 538 DPU_CLK_ATTR2; 539 pl_id = <0>; 540 ports { 541 #address-cells = <1>; 542 #size-cells = <0>; 543 port@0 { 544 reg = <0>; 545 dp_pl0_out0: endpoint { 546 remote-endpoint = <&vencoder_in>; 547 }; 548 }; 549 }; 550 }; 551 552 pl1: pipeline@1 { 553 reg = <1>; 554 DPU_CLK_ATTR3; 555 pl_id = <1>; 556 ports { 557 #address-cells = <1>; 558 #size-cells = <0>; 559 port@0 { 560 reg = <0>; 561 }; 562 }; 563 }; 564 }; 565 566 /* 567 * L3 cache in the DSU is the Memory System Component (MSC) 568 * The MPAM registers are accessed through utility bus in the DSU 569 */ 570 msc0 { 571 compatible = "arm,mpam-msc"; 572 reg = <MPAM_ADDR 0x0 0x2000>; 573 }; 574 575 ete0 { 576 compatible = "arm,embedded-trace-extension"; 577 cpu = <&CPU0>; 578 }; 579 580 ete1 { 581 compatible = "arm,embedded-trace-extension"; 582 cpu = <&CPU1>; 583 }; 584 585 ete2 { 586 compatible = "arm,embedded-trace-extension"; 587 cpu = <&CPU2>; 588 }; 589 590 ete3 { 591 compatible = "arm,embedded-trace-extension"; 592 cpu = <&CPU3>; 593 }; 594 595 ete4 { 596 compatible = "arm,embedded-trace-extension"; 597 cpu = <&CPU4>; 598 }; 599 600 ete5 { 601 compatible = "arm,embedded-trace-extension"; 602 cpu = <&CPU5>; 603 }; 604 605 ete6 { 606 compatible = "arm,embedded-trace-extension"; 607 cpu = <&CPU6>; 608 }; 609 610 ete7 { 611 compatible = "arm,embedded-trace-extension"; 612 cpu = <&CPU7>; 613 }; 614 615 trbe { 616 compatible = "arm,trace-buffer-extension"; 617 interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>; 618 }; 619 620 trusty { 621 #size-cells = <0x02>; 622 #address-cells = <0x02>; 623 ranges = <0x00>; 624 compatible = "android,trusty-v1"; 625 626 virtio { 627 compatible = "android,trusty-virtio-v1"; 628 }; 629 630 test { 631 compatible = "android,trusty-test-v1"; 632 }; 633 634 log { 635 compatible = "android,trusty-log-v1"; 636 }; 637 638 irq { 639 ipi-range = <0x08 0x0f 0x08>; 640 interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0x3f 0x02>; 641 interrupt-templates = <0x01 0x00 0x8001 0x01 0x01 0x04 0x8001 0x01 0x00 0x04>; 642 compatible = "android,trusty-irq-v1"; 643 }; 644 }; 645 646 /* used in U-boot, Linux doesn't care */ 647 arm_ffa { 648 compatible = "arm,ffa"; 649 method = "smc"; 650 }; 651}; 652