1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include "tc_vers.dtsi" 8 9/ { 10 compatible = "arm,tc"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 aliases { 16 serial0 = &os_uart; 17 }; 18 19 chosen { 20 stdout-path = STDOUT_PATH; 21 /* 22 * Add some dummy entropy for Linux so it 23 * doesn't delay the boot waiting for it. 24 */ 25 rng-seed = <0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 26 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 27 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 28 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 29 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 30 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 31 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 32 0x01 0x02 0x04 0x05 0x06 0x07 0x08 >; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu-map { 40 cluster0 { 41 core0 { 42 cpu = <&CPU0>; 43 }; 44 core1 { 45 cpu = <&CPU1>; 46 }; 47 core2 { 48 cpu = <&CPU2>; 49 }; 50 core3 { 51 cpu = <&CPU3>; 52 }; 53 core4 { 54 cpu = <&CPU4>; 55 }; 56 core5 { 57 cpu = <&CPU5>; 58 }; 59 core6 { 60 cpu = <&CPU6>; 61 }; 62 core7 { 63 cpu = <&CPU7>; 64 }; 65 }; 66 }; 67 68 /* 69 * The timings below are just to demonstrate working cpuidle. 70 * These values may be inaccurate. 71 */ 72 idle-states { 73 entry-method = "psci"; 74 75 CPU_SLEEP_0: cpu-sleep-0 { 76 compatible = "arm,idle-state"; 77 arm,psci-suspend-param = <0x0010000>; 78 local-timer-stop; 79 entry-latency-us = <300>; 80 exit-latency-us = <1200>; 81 min-residency-us = <2000>; 82 }; 83 CLUSTER_SLEEP_0: cluster-sleep-0 { 84 compatible = "arm,idle-state"; 85 arm,psci-suspend-param = <0x1010000>; 86 local-timer-stop; 87 entry-latency-us = <400>; 88 exit-latency-us = <1200>; 89 min-residency-us = <2500>; 90 }; 91 }; 92 93 amus { 94 amu: amu-0 { 95 #address-cells = <1>; 96 #size-cells = <0>; 97 98 mpmm_gear0: counter@0 { 99 reg = <0>; 100 enable-at-el3; 101 }; 102 103 mpmm_gear1: counter@1 { 104 reg = <1>; 105 enable-at-el3; 106 }; 107 108 mpmm_gear2: counter@2 { 109 reg = <2>; 110 enable-at-el3; 111 }; 112 }; 113 }; 114 115 CPU0:cpu@0 { 116 device_type = "cpu"; 117 compatible = "arm,armv8"; 118 reg = <0x0>; 119 enable-method = "psci"; 120 clocks = <&scmi_dvfs 0>; 121 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 122 capacity-dmips-mhz = <LIT_CAPACITY>; 123 amu = <&amu>; 124 supports-mpmm; 125 }; 126 127 CPU1:cpu@100 { 128 device_type = "cpu"; 129 compatible = "arm,armv8"; 130 reg = <0x100>; 131 enable-method = "psci"; 132 clocks = <&scmi_dvfs 0>; 133 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 134 capacity-dmips-mhz = <LIT_CAPACITY>; 135 amu = <&amu>; 136 supports-mpmm; 137 }; 138 139 CPU2:cpu@200 { 140 device_type = "cpu"; 141 compatible = "arm,armv8"; 142 reg = <0x200>; 143 enable-method = "psci"; 144 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 145 amu = <&amu>; 146 supports-mpmm; 147 }; 148 149 CPU3:cpu@300 { 150 device_type = "cpu"; 151 compatible = "arm,armv8"; 152 reg = <0x300>; 153 enable-method = "psci"; 154 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 155 amu = <&amu>; 156 supports-mpmm; 157 }; 158 159 CPU4:cpu@400 { 160 device_type = "cpu"; 161 compatible = "arm,armv8"; 162 reg = <0x400>; 163 enable-method = "psci"; 164 clocks = <&scmi_dvfs 1>; 165 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 166 capacity-dmips-mhz = <MID_CAPACITY>; 167 amu = <&amu>; 168 supports-mpmm; 169 }; 170 171 CPU5:cpu@500 { 172 device_type = "cpu"; 173 compatible = "arm,armv8"; 174 reg = <0x500>; 175 enable-method = "psci"; 176 clocks = <&scmi_dvfs 1>; 177 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 178 capacity-dmips-mhz = <MID_CAPACITY>; 179 amu = <&amu>; 180 supports-mpmm; 181 }; 182 183 CPU6:cpu@600 { 184 device_type = "cpu"; 185 compatible = "arm,armv8"; 186 reg = <0x600>; 187 enable-method = "psci"; 188 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 189 amu = <&amu>; 190 supports-mpmm; 191 }; 192 193 CPU7:cpu@700 { 194 device_type = "cpu"; 195 compatible = "arm,armv8"; 196 reg = <0x700>; 197 enable-method = "psci"; 198 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 199 amu = <&amu>; 200 supports-mpmm; 201 }; 202 }; 203 204 reserved-memory { 205 #address-cells = <2>; 206 #size-cells = <2>; 207 ranges; 208 209 linux,cma { 210 compatible = "shared-dma-pool"; 211 reusable; 212 size = <0x0 0x8000000>; 213 linux,cma-default; 214 }; 215 216 optee { 217 compatible = "restricted-dma-pool"; 218 reg = <0x0 TC_NS_OPTEE_BASE 0x0 TC_NS_OPTEE_SIZE>; 219 }; 220 221 fwu_mm { 222 reg = <0x0 TC_NS_FWU_BASE 0x0 TC_NS_FWU_SIZE>; 223 no-map; 224 }; 225 }; 226 227 memory { 228 device_type = "memory"; 229 reg = <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>, 230 <HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE) 231 HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>; 232 }; 233 234 psci { 235 compatible = "arm,psci-1.0", "arm,psci-0.2"; 236 method = "smc"; 237 }; 238 239 cpu-pmu { 240 compatible = "arm,armv8-pmuv3"; 241 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 242 }; 243 244 sram: sram@6000000 { 245 compatible = "mmio-sram"; 246 reg = <0x0 PLAT_ARM_NSRAM_BASE 0x0 PLAT_ARM_NSRAM_SIZE>; 247 248 #address-cells = <1>; 249 #size-cells = <1>; 250 ranges = <0 0x0 PLAT_ARM_NSRAM_BASE PLAT_ARM_NSRAM_SIZE>; 251 252 cpu_scp_scmi_mem: scp-shmem@0 { 253 compatible = "arm,scmi-shmem"; 254 reg = <0x0 0x80>; 255 }; 256 }; 257 258 mbox_db_rx: mhu@MHU_RX_ADDR { 259 compatible = "arm,mhuv2-rx","arm,primecell"; 260 reg = <0x0 ADDRESSIFY(MHU_RX_ADDR) 0x0 0x1000>; 261 clocks = <&soc_refclk>; 262 clock-names = "apb_pclk"; 263 #mbox-cells = <2>; 264 interrupts = <GIC_SPI INT_MBOX_RX IRQ_TYPE_LEVEL_HIGH>; 265 interrupt-names = "mhu_rx"; 266 mhu-protocol = "doorbell"; 267 arm,mhuv2-protocols = <0 1>; 268 }; 269 270 mbox_db_tx: mhu@MHU_TX_ADDR { 271 compatible = "arm,mhuv2-tx","arm,primecell"; 272 reg = <0x0 ADDRESSIFY(MHU_TX_ADDR) 0x0 0x1000>; 273 clocks = <&soc_refclk>; 274 clock-names = "apb_pclk"; 275 #mbox-cells = <2>; 276 interrupt-names = "mhu_tx"; 277 mhu-protocol = "doorbell"; 278 arm,mhuv2-protocols = <0 1>; 279 }; 280 281 scmi { 282 compatible = "arm,scmi"; 283 mbox-names = "tx", "rx"; 284 mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >; 285 shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 289#if TC_SCMI_PD_CTRL_EN 290 scmi_devpd: protocol@11 { 291 reg = <0x11>; 292 #power-domain-cells = <1>; 293 }; 294#endif /* TC_SCMI_PD_CTRL_EN */ 295 296 scmi_dvfs: protocol@13 { 297 reg = <0x13>; 298 #clock-cells = <1>; 299 }; 300 301 scmi_clk: protocol@14 { 302 reg = <0x14>; 303 #clock-cells = <1>; 304 }; 305 }; 306 307 gic: interrupt-controller@GIC_CTRL_ADDR { 308 compatible = "arm,gic-v3"; 309 #address-cells = <2>; 310 #interrupt-cells = <3>; 311 #size-cells = <2>; 312 ranges; 313 interrupt-controller; 314 reg = <0x0 0x30000000 0 0x10000>, /* GICD */ 315 <0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */ 316 interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW>; 317 }; 318 319 timer { 320 compatible = "arm,armv8-timer"; 321 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 322 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 323 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 324 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 325 }; 326 327 soc_refclk: refclk { 328 compatible = "fixed-clock"; 329 #clock-cells = <0>; 330 clock-frequency = <1000000000>; 331 clock-output-names = "apb_pclk"; 332 }; 333 334 soc_refclk60mhz: refclk60mhz { 335 compatible = "fixed-clock"; 336 #clock-cells = <0>; 337 clock-frequency = <60000000>; 338 clock-output-names = "iofpga_clk"; 339 }; 340 341 soc_uartclk: uartclk { 342 compatible = "fixed-clock"; 343 #clock-cells = <0>; 344 clock-frequency = <UARTCLK_FREQ>; 345 clock-output-names = "uartclk"; 346 }; 347 348 /* soc_uart0 on FPGA, ap_ns_uart on FVP */ 349 os_uart: serial@2a400000 { 350 compatible = "arm,pl011", "arm,primecell"; 351 reg = <0x0 0x2A400000 0x0 UART_OFFSET>; 352 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&soc_uartclk>, <&soc_refclk>; 354 clock-names = "uartclk", "apb_pclk"; 355 status = "okay"; 356 }; 357 358 vencoder { 359 compatible = "drm,virtual-encoder"; 360 port { 361 vencoder_in: endpoint { 362 remote-endpoint = <&dp_pl0_out0>; 363 }; 364 }; 365 366 display-timings { 367 timing-panel { 368 VENCODER_TIMING; 369 }; 370 }; 371 372 }; 373 374 ethernet@18000000 { 375 compatible = ETH_COMPATIBLE; 376 reg = <0x0 0x18000000 0x0 0x10000>; 377 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 378 379 /* FPGA only but will work on FVP. Keep for simplicity */ 380 phy-mode = "mii"; 381 reg-io-width = <2>; 382 smsc,irq-push-pull; 383 }; 384 385 bp_clock24mhz: clock24mhz { 386 compatible = "fixed-clock"; 387 #clock-cells = <0>; 388 clock-frequency = <24000000>; 389 clock-output-names = "bp:clock24mhz"; 390 }; 391 392 393 sysreg: sysreg@1c010000 { 394 compatible = "arm,vexpress-sysreg"; 395 reg = <0x0 0x001c010000 0x0 0x1000>; 396 gpio-controller; 397 #gpio-cells = <2>; 398 }; 399 400 fixed_3v3: v2m-3v3 { 401 compatible = "regulator-fixed"; 402 regulator-name = "3V3"; 403 regulator-min-microvolt = <3300000>; 404 regulator-max-microvolt = <3300000>; 405 regulator-always-on; 406 }; 407 408 mmci@1c050000 { 409 compatible = "arm,pl180", "arm,primecell"; 410 reg = <0x0 0x001c050000 0x0 0x1000>; 411 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 413 MMC_REMOVABLE; 414 wp-gpios = <&sysreg 1 0>; 415 bus-width = <4>; 416 max-frequency = <25000000>; 417 vmmc-supply = <&fixed_3v3>; 418 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; 419 clock-names = "mclk", "apb_pclk"; 420 }; 421 422 gpu_clk: gpu_clk { 423 compatible = "fixed-clock"; 424 #clock-cells = <0>; 425 clock-frequency = <1000000000>; 426 }; 427 428 gpu_core_clk: gpu_core_clk { 429 compatible = "fixed-clock"; 430 #clock-cells = <0>; 431 clock-frequency = <1000000000>; 432 }; 433 434 gpu: gpu@2d000000 { 435 compatible = "arm,mali-midgard"; 436 reg = <0x0 0x2d000000 0x0 0x200000>; 437 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 440 interrupt-names = "JOB", "MMU", "GPU"; 441 clocks = <&gpu_core_clk>; 442 clock-names = "shadercores"; 443#if TC_SCMI_PD_CTRL_EN 444 power-domains = <&scmi_devpd GPU_SCMI_PD_IDX>; 445 scmi-perf-domain = <3>; 446#endif /* TC_SCMI_PD_CTRL_EN */ 447 448#if TC_IOMMU_EN 449 iommus = <&smmu_700 0x200>; 450#endif /* TC_IOMMU_EN */ 451 }; 452 453 power_model_simple { 454 /* 455 * Numbers used are irrelevant to Titan, 456 * it helps suppressing the kernel warnings. 457 */ 458 compatible = "arm,mali-simple-power-model"; 459 static-coefficient = <2427750>; 460 dynamic-coefficient = <4687>; 461 ts = <20000 2000 (-20) 2>; 462 thermal-zone = ""; 463 }; 464 465#if TC_IOMMU_EN 466 smmu_700: iommu@3f000000 { 467 #iommu-cells = <1>; 468 compatible = "arm,smmu-v3"; 469 reg = <0x0 0x3f000000 0x0 0x5000000>; 470 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 471 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, 472 <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>; 473 interrupt-names = "eventq", "cmdq-sync", "gerror"; 474 dma-coherent; 475 }; 476#endif /* TC_IOMMU_EN */ 477 478 dp0: display@DPU_ADDR { 479 #address-cells = <1>; 480 #size-cells = <0>; 481 compatible = "arm,mali-d71"; 482 reg = <HI(ADDRESSIFY(DPU_ADDR)) LO(ADDRESSIFY(DPU_ADDR)) 0 0x20000>; 483 interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH>; 484 interrupt-names = "DPU"; 485 DPU_CLK_ATTR1; 486#if TC_IOMMU_EN 487 iommus = <&smmu_700 0x100>; 488#endif /* TC_IOMMU_EN */ 489 490 pl0: pipeline@0 { 491 reg = <0>; 492 DPU_CLK_ATTR2; 493 pl_id = <0>; 494 ports { 495 #address-cells = <1>; 496 #size-cells = <0>; 497 port@0 { 498 reg = <0>; 499 dp_pl0_out0: endpoint { 500 remote-endpoint = <&vencoder_in>; 501 }; 502 }; 503 }; 504 }; 505 506 pl1: pipeline@1 { 507 reg = <1>; 508 DPU_CLK_ATTR3; 509 pl_id = <1>; 510 ports { 511 #address-cells = <1>; 512 #size-cells = <0>; 513 port@0 { 514 reg = <0>; 515 }; 516 }; 517 }; 518 }; 519 520 /* 521 * L3 cache in the DSU is the Memory System Component (MSC) 522 * The MPAM registers are accessed through utility bus in the DSU 523 */ 524 msc0 { 525 compatible = "arm,mpam-msc"; 526 reg = <MPAM_ADDR 0x0 0x2000>; 527 }; 528 529 ete0 { 530 compatible = "arm,embedded-trace-extension"; 531 cpu = <&CPU0>; 532 }; 533 534 ete1 { 535 compatible = "arm,embedded-trace-extension"; 536 cpu = <&CPU1>; 537 }; 538 539 ete2 { 540 compatible = "arm,embedded-trace-extension"; 541 cpu = <&CPU2>; 542 }; 543 544 ete3 { 545 compatible = "arm,embedded-trace-extension"; 546 cpu = <&CPU3>; 547 }; 548 549 ete4 { 550 compatible = "arm,embedded-trace-extension"; 551 cpu = <&CPU4>; 552 }; 553 554 ete5 { 555 compatible = "arm,embedded-trace-extension"; 556 cpu = <&CPU5>; 557 }; 558 559 ete6 { 560 compatible = "arm,embedded-trace-extension"; 561 cpu = <&CPU6>; 562 }; 563 564 ete7 { 565 compatible = "arm,embedded-trace-extension"; 566 cpu = <&CPU7>; 567 }; 568 569 trbe { 570 compatible = "arm,trace-buffer-extension"; 571 interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>; 572 }; 573 574 trusty { 575 #size-cells = <0x02>; 576 #address-cells = <0x02>; 577 ranges = <0x00>; 578 compatible = "android,trusty-v1"; 579 580 virtio { 581 compatible = "android,trusty-virtio-v1"; 582 }; 583 584 test { 585 compatible = "android,trusty-test-v1"; 586 }; 587 588 log { 589 compatible = "android,trusty-log-v1"; 590 }; 591 592 irq { 593 ipi-range = <0x08 0x0f 0x08>; 594 interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0x3f 0x02>; 595 interrupt-templates = <0x01 0x00 0x8001 0x01 0x01 0x04 0x8001 0x01 0x00 0x04>; 596 compatible = "android,trusty-irq-v1"; 597 }; 598 }; 599 600 /* used in U-boot, Linux doesn't care */ 601 arm_ffa { 602 compatible = "arm,ffa"; 603 method = "smc"; 604 }; 605}; 606