1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include "tc_vers.dtsi" 8 9/ { 10 compatible = "arm,tc"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 aliases { 16 serial0 = &os_uart; 17 }; 18 19 chosen { 20 stdout-path = STDOUT_PATH; 21 /* 22 * Add some dummy entropy for Linux so it 23 * doesn't delay the boot waiting for it. 24 */ 25 rng-seed = <0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 26 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 27 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 28 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 29 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 30 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 31 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 32 0x01 0x02 0x04 0x05 0x06 0x07 0x08 >; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu-map { 40 cluster0 { 41 core0 { 42 cpu = <&CPU0>; 43 }; 44 core1 { 45 cpu = <&CPU1>; 46 }; 47 core2 { 48 cpu = <&CPU2>; 49 }; 50 core3 { 51 cpu = <&CPU3>; 52 }; 53 core4 { 54 cpu = <&CPU4>; 55 }; 56 core5 { 57 cpu = <&CPU5>; 58 }; 59 core6 { 60 cpu = <&CPU6>; 61 }; 62 core7 { 63 cpu = <&CPU7>; 64 }; 65#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 66 core8 { 67 cpu = <&CPU8>; 68 }; 69 core9 { 70 cpu = <&CPU9>; 71 }; 72 core10 { 73 cpu = <&CPU10>; 74 }; 75 core11 { 76 cpu = <&CPU11>; 77 }; 78 core12 { 79 cpu = <&CPU12>; 80 }; 81 core13 { 82 cpu = <&CPU13>; 83 }; 84#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ 85 }; 86 }; 87 88 /* 89 * The timings below are just to demonstrate working cpuidle. 90 * These values may be inaccurate. 91 */ 92 idle-states { 93 entry-method = "psci"; 94 95 CPU_SLEEP_0: cpu-sleep-0 { 96 compatible = "arm,idle-state"; 97 arm,psci-suspend-param = <0x0010000>; 98 local-timer-stop; 99 entry-latency-us = <300>; 100 exit-latency-us = <1200>; 101 min-residency-us = <2000>; 102 }; 103 CLUSTER_SLEEP_0: cluster-sleep-0 { 104 compatible = "arm,idle-state"; 105 arm,psci-suspend-param = <0x1010000>; 106 local-timer-stop; 107 entry-latency-us = <400>; 108 exit-latency-us = <1200>; 109 min-residency-us = <2500>; 110 }; 111 }; 112 113 amus { 114 amu: amu-0 { 115 #address-cells = <1>; 116 #size-cells = <0>; 117 118 mpmm_gear0: counter@0 { 119 reg = <0>; 120 enable-at-el3; 121 }; 122 123 mpmm_gear1: counter@1 { 124 reg = <1>; 125 enable-at-el3; 126 }; 127 128 mpmm_gear2: counter@2 { 129 reg = <2>; 130 enable-at-el3; 131 }; 132 }; 133 }; 134 135 CPU0:cpu@0 { 136 device_type = "cpu"; 137 compatible = "arm,armv8"; 138 reg = <0x0>; 139 enable-method = "psci"; 140 clocks = <&scmi_dvfs 0>; 141 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 142 capacity-dmips-mhz = <LIT_CAPACITY>; 143 amu = <&amu>; 144 supports-mpmm; 145 }; 146 147 CPU1:cpu@100 { 148 device_type = "cpu"; 149 compatible = "arm,armv8"; 150 reg = <0x100>; 151 enable-method = "psci"; 152 clocks = <&scmi_dvfs 0>; 153 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 154 capacity-dmips-mhz = <LIT_CAPACITY>; 155 amu = <&amu>; 156 supports-mpmm; 157 }; 158 159 CPU2:cpu@200 { 160 device_type = "cpu"; 161 compatible = "arm,armv8"; 162 reg = <0x200>; 163 enable-method = "psci"; 164 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 165#if TARGET_PLATFORM <= 2 166 clocks = <&scmi_dvfs 0>; 167 capacity-dmips-mhz = <LIT_CAPACITY>; 168#elif TARGET_PLATFORM == 3 169 clocks = <&scmi_dvfs 1>; 170 capacity-dmips-mhz = <MID_CAPACITY>; 171#endif /* TARGET_PLATFORM == 3 */ 172 amu = <&amu>; 173 supports-mpmm; 174 }; 175 176 CPU3:cpu@300 { 177 device_type = "cpu"; 178 compatible = "arm,armv8"; 179 reg = <0x300>; 180 enable-method = "psci"; 181 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 182#if TARGET_PLATFORM <= 2 183 clocks = <&scmi_dvfs 0>; 184 capacity-dmips-mhz = <LIT_CAPACITY>; 185#elif TARGET_PLATFORM == 3 186 clocks = <&scmi_dvfs 1>; 187 capacity-dmips-mhz = <MID_CAPACITY>; 188#endif /* TARGET_PLATFORM == 3 */ 189 amu = <&amu>; 190 supports-mpmm; 191 }; 192 193 CPU4:cpu@400 { 194 device_type = "cpu"; 195 compatible = "arm,armv8"; 196 reg = <0x400>; 197 enable-method = "psci"; 198 clocks = <&scmi_dvfs 1>; 199 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 200 capacity-dmips-mhz = <MID_CAPACITY>; 201 amu = <&amu>; 202 supports-mpmm; 203 }; 204 205 CPU5:cpu@500 { 206 device_type = "cpu"; 207 compatible = "arm,armv8"; 208 reg = <0x500>; 209 enable-method = "psci"; 210 clocks = <&scmi_dvfs 1>; 211 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 212 capacity-dmips-mhz = <MID_CAPACITY>; 213 amu = <&amu>; 214 supports-mpmm; 215 }; 216 217 CPU6:cpu@600 { 218 device_type = "cpu"; 219 compatible = "arm,armv8"; 220 reg = <0x600>; 221 enable-method = "psci"; 222 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 223#if TARGET_PLATFORM <= 2 224 clocks = <&scmi_dvfs 1>; 225 capacity-dmips-mhz = <MID_CAPACITY>; 226#elif TARGET_PLATFORM == 3 227 clocks = <&scmi_dvfs 2>; 228 capacity-dmips-mhz = <BIG_CAPACITY>; 229#endif /* TARGET_PLATFORM == 3 */ 230 amu = <&amu>; 231 supports-mpmm; 232 }; 233 234 CPU7:cpu@700 { 235 device_type = "cpu"; 236 compatible = "arm,armv8"; 237 reg = <0x700>; 238 enable-method = "psci"; 239 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 240#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 241 clocks = <&scmi_dvfs 1>; 242 capacity-dmips-mhz = <MID_CAPACITY>; 243#else 244 clocks = <&scmi_dvfs 2>; 245 capacity-dmips-mhz = <BIG_CAPACITY>; 246#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ 247 amu = <&amu>; 248 supports-mpmm; 249 }; 250 251#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 252 CPU8:cpu@800 { 253 device_type = "cpu"; 254 compatible = "arm,armv8"; 255 reg = <0x800>; 256 enable-method = "psci"; 257 clocks = <&scmi_dvfs 1>; 258 capacity-dmips-mhz = <MID_CAPACITY>; 259 amu = <&amu>; 260 supports-mpmm; 261 }; 262 263 CPU9:cpu@900 { 264 device_type = "cpu"; 265 compatible = "arm,armv8"; 266 reg = <0x900>; 267 enable-method = "psci"; 268 clocks = <&scmi_dvfs 2>; 269 capacity-dmips-mhz = <BIG2_CAPACITY>; 270 amu = <&amu>; 271 supports-mpmm; 272 }; 273 274 CPU10:cpu@A00 { 275 device_type = "cpu"; 276 compatible = "arm,armv8"; 277 reg = <0xA00>; 278 enable-method = "psci"; 279 clocks = <&scmi_dvfs 2>; 280 capacity-dmips-mhz = <BIG2_CAPACITY>; 281 amu = <&amu>; 282 supports-mpmm; 283 }; 284 285 CPU11:cpu@B00 { 286 device_type = "cpu"; 287 compatible = "arm,armv8"; 288 reg = <0xB00>; 289 enable-method = "psci"; 290 clocks = <&scmi_dvfs 2>; 291 capacity-dmips-mhz = <BIG2_CAPACITY>; 292 amu = <&amu>; 293 supports-mpmm; 294 }; 295 296 CPU12:cpu@C00 { 297 device_type = "cpu"; 298 compatible = "arm,armv8"; 299 reg = <0xC00>; 300 enable-method = "psci"; 301 clocks = <&scmi_dvfs 3>; 302 capacity-dmips-mhz = <BIG_CAPACITY>; 303 amu = <&amu>; 304 supports-mpmm; 305 }; 306 307 CPU13:cpu@D00 { 308 device_type = "cpu"; 309 compatible = "arm,armv8"; 310 reg = <0xD00>; 311 enable-method = "psci"; 312 clocks = <&scmi_dvfs 3>; 313 capacity-dmips-mhz = <BIG_CAPACITY>; 314 amu = <&amu>; 315 supports-mpmm; 316 }; 317#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ 318 }; 319 320 reserved-memory { 321 #address-cells = <2>; 322 #size-cells = <2>; 323 ranges; 324 325 linux,cma { 326 compatible = "shared-dma-pool"; 327 reusable; 328 size = <0x0 0x8000000>; 329 linux,cma-default; 330 }; 331 332 optee { 333 compatible = "restricted-dma-pool"; 334 reg = <0x0 TC_NS_OPTEE_BASE 0x0 TC_NS_OPTEE_SIZE>; 335 }; 336 337 fwu_mm { 338 reg = <0x0 TC_NS_FWU_BASE 0x0 TC_NS_FWU_SIZE>; 339 no-map; 340 }; 341 }; 342 343 memory { 344 device_type = "memory"; 345 reg = <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>, 346 <HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE) 347 HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>; 348 }; 349 350 psci { 351 compatible = "arm,psci-1.0", "arm,psci-0.2"; 352 method = "smc"; 353 }; 354 355 cpu-pmu { 356 compatible = "arm,armv8-pmuv3"; 357 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 358 interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, 359 <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7> 360#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 361 ,<&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>, 362 <&CPU12>, <&CPU13> 363#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ 364 ; 365 }; 366 367 sram: sram@6000000 { 368 compatible = "mmio-sram"; 369 reg = <0x0 PLAT_ARM_NSRAM_BASE 0x0 PLAT_ARM_NSRAM_SIZE>; 370 371 #address-cells = <1>; 372 #size-cells = <1>; 373 ranges = <0 0x0 PLAT_ARM_NSRAM_BASE PLAT_ARM_NSRAM_SIZE>; 374 375 cpu_scp_scmi_mem: scp-shmem@0 { 376 compatible = "arm,scmi-shmem"; 377 reg = <0x0 0x80>; 378 }; 379 }; 380 381 mbox_db_rx: mhu@MHU_RX_ADDR { 382 compatible = "arm,mhuv2-rx","arm,primecell"; 383 reg = <0x0 ADDRESSIFY(MHU_RX_ADDR) 0x0 0x1000>; 384 clocks = <&soc_refclk>; 385 clock-names = "apb_pclk"; 386 #mbox-cells = <2>; 387 interrupts = <GIC_SPI INT_MBOX_RX IRQ_TYPE_LEVEL_HIGH>; 388 interrupt-names = "mhu_rx"; 389 mhu-protocol = "doorbell"; 390 arm,mhuv2-protocols = <0 1>; 391 }; 392 393 mbox_db_tx: mhu@MHU_TX_ADDR { 394 compatible = "arm,mhuv2-tx","arm,primecell"; 395 reg = <0x0 ADDRESSIFY(MHU_TX_ADDR) 0x0 0x1000>; 396 clocks = <&soc_refclk>; 397 clock-names = "apb_pclk"; 398 #mbox-cells = <2>; 399 interrupt-names = "mhu_tx"; 400 mhu-protocol = "doorbell"; 401 arm,mhuv2-protocols = <0 1>; 402 }; 403 404 scmi { 405 compatible = "arm,scmi"; 406 mbox-names = "tx", "rx"; 407 mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >; 408 shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 412#if TC_SCMI_PD_CTRL_EN 413 scmi_devpd: protocol@11 { 414 reg = <0x11>; 415 #power-domain-cells = <1>; 416 }; 417#endif /* TC_SCMI_PD_CTRL_EN */ 418 419 scmi_dvfs: protocol@13 { 420 reg = <0x13>; 421 #clock-cells = <1>; 422 }; 423 424 scmi_clk: protocol@14 { 425 reg = <0x14>; 426 #clock-cells = <1>; 427 }; 428 }; 429 430 gic: interrupt-controller@GIC_CTRL_ADDR { 431 compatible = "arm,gic-v3"; 432 #address-cells = <2>; 433 #interrupt-cells = <3>; 434 #size-cells = <2>; 435 ranges; 436 interrupt-controller; 437 reg = <0x0 0x30000000 0 0x10000>, /* GICD */ 438 <0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */ 439 interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW>; 440 }; 441 442 timer { 443 compatible = "arm,armv8-timer"; 444 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 445 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 446 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 447 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 448 }; 449 450 soc_refclk: refclk { 451 compatible = "fixed-clock"; 452 #clock-cells = <0>; 453 clock-frequency = <1000000000>; 454 clock-output-names = "apb_pclk"; 455 }; 456 457 soc_refclk60mhz: refclk60mhz { 458 compatible = "fixed-clock"; 459 #clock-cells = <0>; 460 clock-frequency = <60000000>; 461 clock-output-names = "iofpga_clk"; 462 }; 463 464 soc_uartclk: uartclk { 465 compatible = "fixed-clock"; 466 #clock-cells = <0>; 467 clock-frequency = <UARTCLK_FREQ>; 468 clock-output-names = "uartclk"; 469 }; 470 471 /* soc_uart0 on FPGA, ap_ns_uart on FVP */ 472 os_uart: serial@2a400000 { 473 compatible = "arm,pl011", "arm,primecell"; 474 reg = <0x0 0x2A400000 0x0 UART_OFFSET>; 475 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&soc_uartclk>, <&soc_refclk>; 477 clock-names = "uartclk", "apb_pclk"; 478 status = "okay"; 479 }; 480 481 vencoder { 482 compatible = "drm,virtual-encoder"; 483 port { 484 vencoder_in: endpoint { 485 remote-endpoint = <&dp_pl0_out0>; 486 }; 487 }; 488 489 display-timings { 490 timing-panel { 491 VENCODER_TIMING; 492 }; 493 }; 494 495 }; 496 497 ethernet@18000000 { 498 compatible = ETH_COMPATIBLE; 499 reg = <0x0 0x18000000 0x0 0x10000>; 500 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 501 502 /* FPGA only but will work on FVP. Keep for simplicity */ 503 phy-mode = "mii"; 504 reg-io-width = <2>; 505 smsc,irq-push-pull; 506 }; 507 508 bp_clock24mhz: clock24mhz { 509 compatible = "fixed-clock"; 510 #clock-cells = <0>; 511 clock-frequency = <24000000>; 512 clock-output-names = "bp:clock24mhz"; 513 }; 514 515 516 sysreg: sysreg@1c010000 { 517 compatible = "arm,vexpress-sysreg"; 518 reg = <0x0 0x001c010000 0x0 0x1000>; 519 gpio-controller; 520 #gpio-cells = <2>; 521 }; 522 523 fixed_3v3: v2m-3v3 { 524 compatible = "regulator-fixed"; 525 regulator-name = "3V3"; 526 regulator-min-microvolt = <3300000>; 527 regulator-max-microvolt = <3300000>; 528 regulator-always-on; 529 }; 530 531 mmci@1c050000 { 532 compatible = "arm,pl180", "arm,primecell"; 533 reg = <0x0 0x001c050000 0x0 0x1000>; 534 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 536 MMC_REMOVABLE; 537 wp-gpios = <&sysreg 1 0>; 538 bus-width = <4>; 539 max-frequency = <25000000>; 540 vmmc-supply = <&fixed_3v3>; 541 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; 542 clock-names = "mclk", "apb_pclk"; 543 }; 544 545 gpu_clk: gpu_clk { 546 compatible = "fixed-clock"; 547 #clock-cells = <0>; 548 clock-frequency = <1000000000>; 549 }; 550 551 gpu_core_clk: gpu_core_clk { 552 compatible = "fixed-clock"; 553 #clock-cells = <0>; 554 clock-frequency = <1000000000>; 555 }; 556 557 gpu: gpu@2d000000 { 558 compatible = "arm,mali-midgard"; 559 reg = <0x0 0x2d000000 0x0 0x200000>; 560 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 563 interrupt-names = "JOB", "MMU", "GPU"; 564 clocks = <&gpu_core_clk>; 565 clock-names = "shadercores"; 566#if TC_SCMI_PD_CTRL_EN 567 power-domains = <&scmi_devpd GPU_SCMI_PD_IDX>; 568 scmi-perf-domain = <3>; 569#endif /* TC_SCMI_PD_CTRL_EN */ 570 571#if TC_IOMMU_EN 572 iommus = <&smmu_700 0x200>; 573#endif /* TC_IOMMU_EN */ 574 }; 575 576 power_model_simple { 577 /* 578 * Numbers used are irrelevant to Titan, 579 * it helps suppressing the kernel warnings. 580 */ 581 compatible = "arm,mali-simple-power-model"; 582 static-coefficient = <2427750>; 583 dynamic-coefficient = <4687>; 584 ts = <20000 2000 (-20) 2>; 585 thermal-zone = ""; 586 }; 587 588#if TC_IOMMU_EN 589 smmu_700: iommu@3f000000 { 590 #iommu-cells = <1>; 591 compatible = "arm,smmu-v3"; 592 reg = <0x0 0x3f000000 0x0 0x5000000>; 593 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 594 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, 595 <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>; 596 interrupt-names = "eventq", "cmdq-sync", "gerror"; 597 dma-coherent; 598 }; 599#endif /* TC_IOMMU_EN */ 600 601 dp0: display@DPU_ADDR { 602 #address-cells = <1>; 603 #size-cells = <0>; 604 compatible = "arm,mali-d71"; 605 reg = <HI(ADDRESSIFY(DPU_ADDR)) LO(ADDRESSIFY(DPU_ADDR)) 0 0x20000>; 606 interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH>; 607 interrupt-names = "DPU"; 608 DPU_CLK_ATTR1; 609#if TC_IOMMU_EN 610 iommus = <&smmu_700 0x100>; 611#endif /* TC_IOMMU_EN */ 612#if TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3) 613 power-domains = <&scmi_devpd DPU_SCMI_PD_IDX>; 614#endif /* TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3) */ 615 616 pl0: pipeline@0 { 617 reg = <0>; 618 DPU_CLK_ATTR2; 619 pl_id = <0>; 620 ports { 621 #address-cells = <1>; 622 #size-cells = <0>; 623 port@0 { 624 reg = <0>; 625 dp_pl0_out0: endpoint { 626 remote-endpoint = <&vencoder_in>; 627 }; 628 }; 629 }; 630 }; 631 632 pl1: pipeline@1 { 633 reg = <1>; 634 DPU_CLK_ATTR3; 635 pl_id = <1>; 636 ports { 637 #address-cells = <1>; 638 #size-cells = <0>; 639 port@0 { 640 reg = <0>; 641 }; 642 }; 643 }; 644 }; 645 646 /* 647 * L3 cache in the DSU is the Memory System Component (MSC) 648 * The MPAM registers are accessed through utility bus in the DSU 649 */ 650 msc0 { 651 compatible = "arm,mpam-msc"; 652 reg = <MPAM_ADDR 0x0 0x2000>; 653 }; 654 655 ete0 { 656 compatible = "arm,embedded-trace-extension"; 657 cpu = <&CPU0>; 658 }; 659 660 ete1 { 661 compatible = "arm,embedded-trace-extension"; 662 cpu = <&CPU1>; 663 }; 664 665 ete2 { 666 compatible = "arm,embedded-trace-extension"; 667 cpu = <&CPU2>; 668 }; 669 670 ete3 { 671 compatible = "arm,embedded-trace-extension"; 672 cpu = <&CPU3>; 673 }; 674 675 ete4 { 676 compatible = "arm,embedded-trace-extension"; 677 cpu = <&CPU4>; 678 }; 679 680 ete5 { 681 compatible = "arm,embedded-trace-extension"; 682 cpu = <&CPU5>; 683 }; 684 685 ete6 { 686 compatible = "arm,embedded-trace-extension"; 687 cpu = <&CPU6>; 688 }; 689 690 ete7 { 691 compatible = "arm,embedded-trace-extension"; 692 cpu = <&CPU7>; 693 }; 694 695#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 696 ete8 { 697 compatible = "arm,embedded-trace-extension"; 698 cpu = <&CPU8>; 699 }; 700 701 ete9 { 702 compatible = "arm,embedded-trace-extension"; 703 cpu = <&CPU9>; 704 }; 705 706 ete10 { 707 compatible = "arm,embedded-trace-extension"; 708 cpu = <&CPU10>; 709 }; 710 711 ete11 { 712 compatible = "arm,embedded-trace-extension"; 713 cpu = <&CPU11>; 714 }; 715 716 ete12 { 717 compatible = "arm,embedded-trace-extension"; 718 cpu = <&CPU12>; 719 }; 720 721 ete13 { 722 compatible = "arm,embedded-trace-extension"; 723 cpu = <&CPU13>; 724 }; 725#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */ 726 727 trbe { 728 compatible = "arm,trace-buffer-extension"; 729 interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>; 730 }; 731 732 trusty { 733 #size-cells = <0x02>; 734 #address-cells = <0x02>; 735 ranges = <0x00>; 736 compatible = "android,trusty-v1"; 737 738 virtio { 739 compatible = "android,trusty-virtio-v1"; 740 }; 741 742 test { 743 compatible = "android,trusty-test-v1"; 744 }; 745 746 log { 747 compatible = "android,trusty-log-v1"; 748 }; 749 750 irq { 751 ipi-range = <0x08 0x0f 0x08>; 752 interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0x3f 0x02>; 753 interrupt-templates = <0x01 0x00 0x8001 0x01 0x01 0x04 0x8001 0x01 0x00 0x04>; 754 compatible = "android,trusty-irq-v1"; 755 }; 756 }; 757 758 /* used in U-boot, Linux doesn't care */ 759 arm_ffa { 760 compatible = "arm,ffa"; 761 method = "smc"; 762 }; 763}; 764