1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <platform_def.h> 12 13#define LIT_CAPACITY 239 14#define MID_CAPACITY 686 15#define BIG_CAPACITY 1024 16 17#define INT_MBOX_RX 300 18#define MHU_TX_ADDR 46040000 /* hex */ 19#define MHU_RX_ADDR 46140000 /* hex */ 20#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */ 21#define UARTCLK_FREQ 3750000 22 23#if TARGET_FLAVOUR_FVP 24#define DPU_ADDR 4000000000 25#define DPU_IRQ 579 26#elif TARGET_FLAVOUR_FPGA 27#define DPU_ADDR 2cc00000 28#define DPU_IRQ 69 29#endif 30 31#include "tc-common.dtsi" 32#if TARGET_FLAVOUR_FVP 33#include "tc-fvp.dtsi" 34#endif /* TARGET_FLAVOUR_FVP */ 35#include "tc-base.dtsi" 36