1/* 2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/* If SCMI power domain control is enabled */ 8#if TC_SCMI_PD_CTRL_EN 9#define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1) 10#define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2) 11#endif /* TC_SCMI_PD_CTRL_EN */ 12 13/* Use SCMI controlled clocks */ 14#if TC_DPU_USE_SCMI_CLK 15#define DPU_CLK_ATTR1 \ 16 clocks = <&scmi_clk 0>; \ 17 clock-names = "aclk" 18 19#define DPU_CLK_ATTR2 \ 20 clocks = <&scmi_clk 1>; \ 21 clock-names = "pxclk" 22 23#define DPU_CLK_ATTR3 \ 24 clocks = <&scmi_clk 2>; \ 25 clock-names = "pxclk" \ 26/* Use fixed clocks */ 27#else /* !TC_DPU_USE_SCMI_CLK */ 28#define DPU_CLK_ATTR1 \ 29 clocks = <&dpu_aclk>; \ 30 clock-names = "aclk" 31 32#define DPU_CLK_ATTR2 \ 33 clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \ 34 clock-names = "pxclk", "aclk" 35 36#define DPU_CLK_ATTR3 DPU_CLK_ATTR2 37#endif /* !TC_DPU_USE_SCMI_CLK */ 38 39/ { 40 compatible = "arm,tc"; 41 interrupt-parent = <&gic>; 42 #address-cells = <2>; 43 #size-cells = <2>; 44 45 aliases { 46 serial0 = &os_uart; 47 }; 48 49 chosen { 50 /* 51 * Add some dummy entropy for Linux so it 52 * doesn't delay the boot waiting for it. 53 */ 54 rng-seed = <0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 55 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 56 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 57 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 58 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 59 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 60 0x01 0x02 0x04 0x05 0x06 0x07 0x08 \ 61 0x01 0x02 0x04 0x05 0x06 0x07 0x08 >; 62 }; 63 64 cpus { 65 #address-cells = <1>; 66 #size-cells = <0>; 67 68 cpu-map { 69 cluster0 { 70 core0 { 71 cpu = <&CPU0>; 72 }; 73 core1 { 74 cpu = <&CPU1>; 75 }; 76 core2 { 77 cpu = <&CPU2>; 78 }; 79 core3 { 80 cpu = <&CPU3>; 81 }; 82 core4 { 83 cpu = <&CPU4>; 84 }; 85 core5 { 86 cpu = <&CPU5>; 87 }; 88 core6 { 89 cpu = <&CPU6>; 90 }; 91 core7 { 92 cpu = <&CPU7>; 93 }; 94 }; 95 }; 96 97 /* 98 * The timings below are just to demonstrate working cpuidle. 99 * These values may be inaccurate. 100 */ 101 idle-states { 102 entry-method = "psci"; 103 104 CPU_SLEEP_0: cpu-sleep-0 { 105 compatible = "arm,idle-state"; 106 arm,psci-suspend-param = <0x0010000>; 107 local-timer-stop; 108 entry-latency-us = <300>; 109 exit-latency-us = <1200>; 110 min-residency-us = <2000>; 111 }; 112 CLUSTER_SLEEP_0: cluster-sleep-0 { 113 compatible = "arm,idle-state"; 114 arm,psci-suspend-param = <0x1010000>; 115 local-timer-stop; 116 entry-latency-us = <400>; 117 exit-latency-us = <1200>; 118 min-residency-us = <2500>; 119 }; 120 }; 121 122 amus { 123 amu: amu-0 { 124 #address-cells = <1>; 125 #size-cells = <0>; 126 127 mpmm_gear0: counter@0 { 128 reg = <0>; 129 enable-at-el3; 130 }; 131 132 mpmm_gear1: counter@1 { 133 reg = <1>; 134 enable-at-el3; 135 }; 136 137 mpmm_gear2: counter@2 { 138 reg = <2>; 139 enable-at-el3; 140 }; 141 }; 142 }; 143 144 CPU0:cpu@0 { 145 device_type = "cpu"; 146 compatible = "arm,armv8"; 147 reg = <0x0>; 148 enable-method = "psci"; 149 clocks = <&scmi_dvfs 0>; 150 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 151 capacity-dmips-mhz = <LIT_CAPACITY>; 152 amu = <&amu>; 153 supports-mpmm; 154 }; 155 156 CPU1:cpu@100 { 157 device_type = "cpu"; 158 compatible = "arm,armv8"; 159 reg = <0x100>; 160 enable-method = "psci"; 161 clocks = <&scmi_dvfs 0>; 162 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 163 capacity-dmips-mhz = <LIT_CAPACITY>; 164 amu = <&amu>; 165 supports-mpmm; 166 }; 167 168 CPU2:cpu@200 { 169 device_type = "cpu"; 170 compatible = "arm,armv8"; 171 reg = <0x200>; 172 enable-method = "psci"; 173 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 174 amu = <&amu>; 175 supports-mpmm; 176 }; 177 178 CPU3:cpu@300 { 179 device_type = "cpu"; 180 compatible = "arm,armv8"; 181 reg = <0x300>; 182 enable-method = "psci"; 183 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 184 amu = <&amu>; 185 supports-mpmm; 186 }; 187 188 CPU4:cpu@400 { 189 device_type = "cpu"; 190 compatible = "arm,armv8"; 191 reg = <0x400>; 192 enable-method = "psci"; 193 clocks = <&scmi_dvfs 1>; 194 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 195 capacity-dmips-mhz = <MID_CAPACITY>; 196 amu = <&amu>; 197 supports-mpmm; 198 }; 199 200 CPU5:cpu@500 { 201 device_type = "cpu"; 202 compatible = "arm,armv8"; 203 reg = <0x500>; 204 enable-method = "psci"; 205 clocks = <&scmi_dvfs 1>; 206 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 207 capacity-dmips-mhz = <MID_CAPACITY>; 208 amu = <&amu>; 209 supports-mpmm; 210 }; 211 212 CPU6:cpu@600 { 213 device_type = "cpu"; 214 compatible = "arm,armv8"; 215 reg = <0x600>; 216 enable-method = "psci"; 217 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 218 amu = <&amu>; 219 supports-mpmm; 220 }; 221 222 CPU7:cpu@700 { 223 device_type = "cpu"; 224 compatible = "arm,armv8"; 225 reg = <0x700>; 226 enable-method = "psci"; 227 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 228 amu = <&amu>; 229 supports-mpmm; 230 }; 231 }; 232 233 reserved-memory { 234 #address-cells = <2>; 235 #size-cells = <2>; 236 ranges; 237 238 linux,cma { 239 compatible = "shared-dma-pool"; 240 reusable; 241 size = <0x0 0x8000000>; 242 linux,cma-default; 243 }; 244 245 optee { 246 compatible = "restricted-dma-pool"; 247 reg = <0x0 TC_NS_OPTEE_BASE 0x0 TC_NS_OPTEE_SIZE>; 248 }; 249 250 fwu_mm { 251 reg = <0x0 TC_NS_FWU_BASE 0x0 TC_NS_FWU_SIZE>; 252 no-map; 253 }; 254 }; 255 256 memory { 257 device_type = "memory"; 258 reg = <0x0 TC_NS_DRAM1_BASE 0x0 TC_NS_DRAM1_SIZE>, 259 <HI(PLAT_ARM_DRAM2_BASE) LO(PLAT_ARM_DRAM2_BASE) 260 HI(TC_NS_DRAM2_SIZE) LO(TC_NS_DRAM2_SIZE)>; 261 }; 262 263 psci { 264 compatible = "arm,psci-1.0", "arm,psci-0.2"; 265 method = "smc"; 266 }; 267 268 cpu-pmu { 269 compatible = "arm,armv8-pmuv3"; 270 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 271 }; 272 273 sram: sram@6000000 { 274 compatible = "mmio-sram"; 275 reg = <0x0 PLAT_ARM_NSRAM_BASE 0x0 PLAT_ARM_NSRAM_SIZE>; 276 277 #address-cells = <1>; 278 #size-cells = <1>; 279 ranges = <0 0x0 PLAT_ARM_NSRAM_BASE PLAT_ARM_NSRAM_SIZE>; 280 281 cpu_scp_scmi_mem: scp-shmem@0 { 282 compatible = "arm,scmi-shmem"; 283 reg = <0x0 0x80>; 284 }; 285 }; 286 287 mbox_db_rx: mhu@MHU_RX_ADDR { 288 compatible = "arm,mhuv2-rx","arm,primecell"; 289 reg = <0x0 ADDRESSIFY(MHU_RX_ADDR) 0x0 0x1000>; 290 clocks = <&soc_refclk>; 291 clock-names = "apb_pclk"; 292 #mbox-cells = <2>; 293 interrupts = <GIC_SPI INT_MBOX_RX IRQ_TYPE_LEVEL_HIGH>; 294 interrupt-names = "mhu_rx"; 295 mhu-protocol = "doorbell"; 296 arm,mhuv2-protocols = <0 1>; 297 }; 298 299 mbox_db_tx: mhu@MHU_TX_ADDR { 300 compatible = "arm,mhuv2-tx","arm,primecell"; 301 reg = <0x0 ADDRESSIFY(MHU_TX_ADDR) 0x0 0x1000>; 302 clocks = <&soc_refclk>; 303 clock-names = "apb_pclk"; 304 #mbox-cells = <2>; 305 interrupt-names = "mhu_tx"; 306 mhu-protocol = "doorbell"; 307 arm,mhuv2-protocols = <0 1>; 308 }; 309 310 scmi { 311 compatible = "arm,scmi"; 312 mbox-names = "tx", "rx"; 313 mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >; 314 shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>; 315 #address-cells = <1>; 316 #size-cells = <0>; 317 318#if TC_SCMI_PD_CTRL_EN 319 scmi_devpd: protocol@11 { 320 reg = <0x11>; 321 #power-domain-cells = <1>; 322 }; 323#endif /* TC_SCMI_PD_CTRL_EN */ 324 325 scmi_dvfs: protocol@13 { 326 reg = <0x13>; 327 #clock-cells = <1>; 328 }; 329 330 scmi_clk: protocol@14 { 331 reg = <0x14>; 332 #clock-cells = <1>; 333 }; 334 }; 335 336 gic: interrupt-controller@GIC_CTRL_ADDR { 337 compatible = "arm,gic-v3"; 338 #address-cells = <2>; 339 #interrupt-cells = <3>; 340 #size-cells = <2>; 341 ranges; 342 interrupt-controller; 343 reg = <0x0 0x30000000 0 0x10000>, /* GICD */ 344 <0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */ 345 interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW>; 346 }; 347 348 timer { 349 compatible = "arm,armv8-timer"; 350 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 351 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 352 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 353 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 354 }; 355 356 soc_refclk: refclk { 357 compatible = "fixed-clock"; 358 #clock-cells = <0>; 359 clock-frequency = <1000000000>; 360 clock-output-names = "apb_pclk"; 361 }; 362 363 soc_refclk60mhz: refclk60mhz { 364 compatible = "fixed-clock"; 365 #clock-cells = <0>; 366 clock-frequency = <60000000>; 367 clock-output-names = "iofpga_clk"; 368 }; 369 370 soc_uartclk: uartclk { 371 compatible = "fixed-clock"; 372 #clock-cells = <0>; 373 clock-frequency = <UARTCLK_FREQ>; 374 clock-output-names = "uartclk"; 375 }; 376 377 /* soc_uart0 on FPGA, ap_ns_uart on FVP */ 378 os_uart: serial@2a400000 { 379 compatible = "arm,pl011", "arm,primecell"; 380 reg = <0x0 0x2A400000 0x0 UART_OFFSET>; 381 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&soc_uartclk>, <&soc_refclk>; 383 clock-names = "uartclk", "apb_pclk"; 384 status = "okay"; 385 }; 386 387#if !TC_DPU_USE_SCMI_CLK 388 dpu_aclk: dpu_aclk { 389 compatible = "fixed-clock"; 390 #clock-cells = <0>; 391 clock-frequency = <VENCODER_TIMING_CLK>; 392 clock-output-names = "fpga:dpu_aclk"; 393 }; 394 395 dpu_pixel_clk: dpu-pixel-clk { 396 compatible = "fixed-clock"; 397 #clock-cells = <0>; 398 clock-frequency = <VENCODER_TIMING_CLK>; 399 clock-output-names = "pxclk"; 400 }; 401#endif /* !TC_DPU_USE_SCMI_CLK */ 402 403 vencoder { 404 compatible = "drm,virtual-encoder"; 405 port { 406 vencoder_in: endpoint { 407 remote-endpoint = <&dp_pl0_out0>; 408 }; 409 }; 410 411 display-timings { 412 timing-panel { 413 VENCODER_TIMING; 414 }; 415 }; 416 417 }; 418 419 ethernet: ethernet@18000000 { 420 reg = <0x0 0x18000000 0x0 0x10000>; 421 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 422 423 reg-io-width = <2>; 424 smsc,irq-push-pull; 425 }; 426 427 bp_clock24mhz: clock24mhz { 428 compatible = "fixed-clock"; 429 #clock-cells = <0>; 430 clock-frequency = <24000000>; 431 clock-output-names = "bp:clock24mhz"; 432 }; 433 434 435 sysreg: sysreg@1c010000 { 436 compatible = "arm,vexpress-sysreg"; 437 reg = <0x0 0x001c010000 0x0 0x1000>; 438 gpio-controller; 439 #gpio-cells = <2>; 440 }; 441 442 fixed_3v3: v2m-3v3 { 443 compatible = "regulator-fixed"; 444 regulator-name = "3V3"; 445 regulator-min-microvolt = <3300000>; 446 regulator-max-microvolt = <3300000>; 447 regulator-always-on; 448 }; 449 450 mmci: mmci@1c050000 { 451 compatible = "arm,pl180", "arm,primecell"; 452 reg = <0x0 0x001c050000 0x0 0x1000>; 453 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 455 wp-gpios = <&sysreg 1 0>; 456 bus-width = <4>; 457 max-frequency = <25000000>; 458 vmmc-supply = <&fixed_3v3>; 459 clocks = <&bp_clock24mhz>, <&bp_clock24mhz>; 460 clock-names = "mclk", "apb_pclk"; 461 }; 462 463 gpu_clk: gpu_clk { 464 compatible = "fixed-clock"; 465 #clock-cells = <0>; 466 clock-frequency = <1000000000>; 467 }; 468 469 gpu_core_clk: gpu_core_clk { 470 compatible = "fixed-clock"; 471 #clock-cells = <0>; 472 clock-frequency = <1000000000>; 473 }; 474 475 gpu: gpu@2d000000 { 476 compatible = "arm,mali-midgard"; 477 reg = <0x0 0x2d000000 0x0 0x200000>; 478 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 481 interrupt-names = "JOB", "MMU", "GPU"; 482 clocks = <&gpu_core_clk>; 483 clock-names = "shadercores"; 484#if TC_SCMI_PD_CTRL_EN 485 power-domains = <&scmi_devpd GPU_SCMI_PD_IDX>; 486 scmi-perf-domain = <3>; 487#endif /* TC_SCMI_PD_CTRL_EN */ 488 489#if TC_IOMMU_EN 490 iommus = <&smmu_700 0x200>; 491#endif /* TC_IOMMU_EN */ 492 }; 493 494 power_model_simple { 495 /* 496 * Numbers used are irrelevant to Titan, 497 * it helps suppressing the kernel warnings. 498 */ 499 compatible = "arm,mali-simple-power-model"; 500 static-coefficient = <2427750>; 501 dynamic-coefficient = <4687>; 502 ts = <20000 2000 (-20) 2>; 503 thermal-zone = ""; 504 }; 505 506#if TC_IOMMU_EN 507 smmu_700: iommu@3f000000 { 508 #iommu-cells = <1>; 509 compatible = "arm,smmu-v3"; 510 reg = <0x0 0x3f000000 0x0 0x5000000>; 511 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 512 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, 513 <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>; 514 interrupt-names = "eventq", "cmdq-sync", "gerror"; 515 dma-coherent; 516 }; 517#endif /* TC_IOMMU_EN */ 518 519 dp0: display@DPU_ADDR { 520 #address-cells = <1>; 521 #size-cells = <0>; 522 compatible = "arm,mali-d71"; 523 reg = <HI(ADDRESSIFY(DPU_ADDR)) LO(ADDRESSIFY(DPU_ADDR)) 0 0x20000>; 524 interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH>; 525 interrupt-names = "DPU"; 526 DPU_CLK_ATTR1; 527#if TC_IOMMU_EN 528 iommus = <&smmu_700 0x100>; 529#endif /* TC_IOMMU_EN */ 530 531 pl0: pipeline@0 { 532 reg = <0>; 533 DPU_CLK_ATTR2; 534 pl_id = <0>; 535 ports { 536 #address-cells = <1>; 537 #size-cells = <0>; 538 port@0 { 539 reg = <0>; 540 dp_pl0_out0: endpoint { 541 remote-endpoint = <&vencoder_in>; 542 }; 543 }; 544 }; 545 }; 546 547 pl1: pipeline@1 { 548 reg = <1>; 549 DPU_CLK_ATTR3; 550 pl_id = <1>; 551 ports { 552 #address-cells = <1>; 553 #size-cells = <0>; 554 port@0 { 555 reg = <0>; 556 }; 557 }; 558 }; 559 }; 560 561 /* 562 * L3 cache in the DSU is the Memory System Component (MSC) 563 * The MPAM registers are accessed through utility bus in the DSU 564 */ 565 msc0 { 566 compatible = "arm,mpam-msc"; 567 reg = <MPAM_ADDR 0x0 0x2000>; 568 }; 569 570 ete0 { 571 compatible = "arm,embedded-trace-extension"; 572 cpu = <&CPU0>; 573 }; 574 575 ete1 { 576 compatible = "arm,embedded-trace-extension"; 577 cpu = <&CPU1>; 578 }; 579 580 ete2 { 581 compatible = "arm,embedded-trace-extension"; 582 cpu = <&CPU2>; 583 }; 584 585 ete3 { 586 compatible = "arm,embedded-trace-extension"; 587 cpu = <&CPU3>; 588 }; 589 590 ete4 { 591 compatible = "arm,embedded-trace-extension"; 592 cpu = <&CPU4>; 593 }; 594 595 ete5 { 596 compatible = "arm,embedded-trace-extension"; 597 cpu = <&CPU5>; 598 }; 599 600 ete6 { 601 compatible = "arm,embedded-trace-extension"; 602 cpu = <&CPU6>; 603 }; 604 605 ete7 { 606 compatible = "arm,embedded-trace-extension"; 607 cpu = <&CPU7>; 608 }; 609 610 trbe { 611 compatible = "arm,trace-buffer-extension"; 612 interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>; 613 }; 614 615 trusty { 616 #size-cells = <0x02>; 617 #address-cells = <0x02>; 618 ranges = <0x00>; 619 compatible = "android,trusty-v1"; 620 621 virtio { 622 compatible = "android,trusty-virtio-v1"; 623 }; 624 625 test { 626 compatible = "android,trusty-test-v1"; 627 }; 628 629 log { 630 compatible = "android,trusty-log-v1"; 631 }; 632 633 irq { 634 ipi-range = <0x08 0x0f 0x08>; 635 interrupt-ranges = <0x00 0x0f 0x00 0x10 0x1f 0x01 0x20 0x3f 0x02>; 636 interrupt-templates = <0x01 0x00 0x8001 0x01 0x01 0x04 0x8001 0x01 0x00 0x04>; 637 compatible = "android,trusty-irq-v1"; 638 }; 639 }; 640 641 /* used in U-boot, Linux doesn't care */ 642 arm_ffa { 643 compatible = "arm,ffa"; 644 method = "smc"; 645 }; 646}; 647