Merge "intel: Enable EMAC PHY in Intel FPGA platform" into integration

Merge "mt8173: Add support for new watchdog SMC" into integration

Merge "intel: Fix argument type for mailbox driver" into integration

Merge "fconf: Fix misra issues" into integration

Merge "Add Cortex-A65/AE to the supported FVP list" into integration

Merge "intel: Update RSU driver return code" into integration

fconf: Fix misra issues

MISRA C-2012 Rule 20.7:
Macro parameter expands into an expression without being wrapped by parentheses.

MISRA C-2012 Rule 12.1:
Missing explicit parentheses on sub-expressi

fconf: Fix misra issues

MISRA C-2012 Rule 20.7:
Macro parameter expands into an expression without being wrapped by parentheses.

MISRA C-2012 Rule 12.1:
Missing explicit parentheses on sub-expression.

MISRA C-2012 Rule 18.4:
Essential type of the left hand operand is not the same as that of the right
operand.

Include does not provide any needed symbols.

Change-Id: Ie1c6451cfbc8f519146c28b2cf15c50b1f36adc8
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

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Add Cortex-A65/AE to the supported FVP list

Cortex-A65x4 and Cortex-A65AEx8 is now included in the list of the
supported Arm Fixed Virtual Platforms.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Chan

Add Cortex-A65/AE to the supported FVP list

Cortex-A65x4 and Cortex-A65AEx8 is now included in the list of the
supported Arm Fixed Virtual Platforms.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: Ibfcaec11bc75549d60455e96858d79b679e71e5e

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intel: Update RSU driver return code

Modify RSU driver error code for backward-compatibility with
Linux RSU driver

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.hal

intel: Update RSU driver return code

Modify RSU driver error code for backward-compatibility with
Linux RSU driver

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib9e38d4017efe35d3aceeee27dce451fbd429fb5

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Merge "Modify multithreaded dts file of DynamIQ FVPs" into integration

Merge "change-log: Add fconf entry" into integration

Merge "Build: fix 'BL stage' comment for build macros" into integration

Build: fix 'BL stage' comment for build macros

The MAKE_BL macro is invoked for 1, 2, 2u, 31, 32.

Fix the comments.

Change-Id: I35dd25cc2ea13885c184fb9c8229a322b33f7e71
Signed-off-by: Masahiro Yam

Build: fix 'BL stage' comment for build macros

The MAKE_BL macro is invoked for 1, 2, 2u, 31, 32.

Fix the comments.

Change-Id: I35dd25cc2ea13885c184fb9c8229a322b33f7e71
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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Update pathnames in maintainers.rst file

The maintainers.rst file lists files and directories that each contributor looks
after in the TF-A source tree. As files and directories move around over tim

Update pathnames in maintainers.rst file

The maintainers.rst file lists files and directories that each contributor looks
after in the TF-A source tree. As files and directories move around over time,
some pathnames had become invalid. Fix them, either by updating the path if
it has just moved, or deleting it altogether if it doesn't seem to exist
anymore.

Change-Id: Idb6ff4d8d0b593138d4f555ec206abcf68b0064f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Merge "amlogic/axg: Add documentation page to the index" into integration

amlogic/axg: Add documentation page to the index

It is needed to make it appear in the table of contents. Right now,
all Amlogic documentation pages appear under the "Platform ports"
section, except

amlogic/axg: Add documentation page to the index

It is needed to make it appear in the table of contents. Right now,
all Amlogic documentation pages appear under the "Platform ports"
section, except the AXG one.

Change-Id: Ibcfc3b156888d2a9574953578978b629e185c708
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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change-log: Add fconf entry

Change-Id: I6686f172d0c24f6c457a39cdf4debcbf05475540
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Modify multithreaded dts file of DynamIQ FVPs

The dts file now contains a CPU map that precisely describes the
topology including thread nodes. The map was also extended to have 16
PEs to be able to

Modify multithreaded dts file of DynamIQ FVPs

The dts file now contains a CPU map that precisely describes the
topology including thread nodes. The map was also extended to have 16
PEs to be able to test multithreaded FVPs with 8 cores in the same
cluster.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: If39559b05d20bfd68d0ecf830ddcbc5233b288a0

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Merge "tools: Small improvement to print_memory_map script" into integration

Merge "uniphier: prepare uniphier_soc_info() for next SoC" into integration

Merge "FVP: Fix incorrect GIC mapping" into integration

Merge "allwinner: Implement PSCI system suspend using SCPI" into integration

Merge "allwinner: Add a msgbox driver for use with SCPI" into integration

uniphier: prepare uniphier_soc_info() for next SoC

The revision register address will be changed in the next SoC.

The LSI revision is needed in order to know where the revision
register is located,

uniphier: prepare uniphier_soc_info() for next SoC

The revision register address will be changed in the next SoC.

The LSI revision is needed in order to know where the revision
register is located, but you need to read out the revision
register for that. This is impossible.

We need to know the revision register address by other means.
Use BL_CODE_BASE, where the base address of the TF image that is
currently running. If it is bigger than 0x80000000 (i.e. the DRAM
base is 0x80000000), we assume it is a legacy SoC.

Change-Id: I9d7f4325fe2085a8a1ab5310025e5948da611256
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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Merge "allwinner: Reserve and map space for the SCP firmware" into integration