| 73a96051 | 28-Feb-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1282 from robertovargas-arm/misra-changes
Misra changes |
| 7fabe1a8 | 12-Feb-2018 |
Roberto Vargas <roberto.vargas@arm.com> |
Fix MISRA rule 8.4 in common code
Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined.
Change-Id: I26e042cb251a6f9590afa1340fda
Fix MISRA rule 8.4 in common code
Rule 8.4: A compatible declaration shall be visible when
an object or function with external linkage is defined.
Change-Id: I26e042cb251a6f9590afa1340fdac73e42f23979
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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| 99e198ec | 28-Feb-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1284 from jeenu-arm/tspd-ehf
TSPD and EHF |
| 472be0f7 | 22-Jan-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
TSPD: Register preempted SMC error code with EHF
An earlier patch extended ehf_allow_ns_preemption() API to also register
an error code to offer to Non-secure when a Yielding SMC is preempted by
SDE
TSPD: Register preempted SMC error code with EHF
An earlier patch extended ehf_allow_ns_preemption() API to also register
an error code to offer to Non-secure when a Yielding SMC is preempted by
SDEI interrupt. In TSPD's case, register the error code TSP_PREEMPTED.
Change-Id: I31992b6651f80694e83bc5092b044ef7a3eda690
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| 8e3032f9 | 22-Jan-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
SDEI: Pop dispatch context only after error checking
Currently, when the client attempts to do SDEI_EVENT_COMPLETE or
SDEI_EVENT_COMPLETE_AND_RESUME, the dispatcher pops off the outstanding
dispatch
SDEI: Pop dispatch context only after error checking
Currently, when the client attempts to do SDEI_EVENT_COMPLETE or
SDEI_EVENT_COMPLETE_AND_RESUME, the dispatcher pops off the outstanding
dispatch context for sanity check. There are however other checks
following this, which could potentially return failure. If that happens,
by popping the context, the dispatcher has inadvertently discarded a
valid context.
This patch fixes this bug by inspecting (not actually popping) the
outstanding context. The context is popped only after all error checks
are completed.
Change-Id: Ie199f6442f871a8177a8247a0c646543bad76d21
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| 06ff251e | 22-Feb-2018 |
Arve Hjønnevåg <arve@android.com> |
tegra/trusty: Setup tegra specific trusty args in platform code
Fixes tegra build with SPD=trusty. Not tested.
Change-Id: I851a2b00b8b1cc65112b6088980a811d8eda1a99 |
| 6bf0e079 | 19-Feb-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Ensure the correct execution of TLBI instructions
After executing a TLBI a DSB is needed to ensure completion of the
TLBI.
rk3328: The MMU is allowed to load TLB entries for as long as it is
enable
Ensure the correct execution of TLBI instructions
After executing a TLBI a DSB is needed to ensure completion of the
TLBI.
rk3328: The MMU is allowed to load TLB entries for as long as it is
enabled. Because of this, the correct place to execute a TLBI is right
after disabling the MMU.
Change-Id: I8280f248d10b49a8c354a4ccbdc8f8345ac4c170
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| fb1198b1 | 14-Feb-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Remove URLs from comments
This fixes all defects according to MISRA Rule 3.1: "The character
sequences /* and // shall not be used within a comment". This affects
all URLs in comments, so they have
Remove URLs from comments
This fixes all defects according to MISRA Rule 3.1: "The character
sequences /* and // shall not be used within a comment". This affects
all URLs in comments, so they have been removed:
- The link in `sdei_state.c` can also be found in the documentation file
`docs/sdei.rst`.
- The bug that the file `io_fip.c` talks about doesn't affect the
currently supported version of GCC, so it doesn't make sense to keep
the comment. Note that the version of GCC officially supported is the
one that comes with Linaro Release 17.10, which is GCC 6.2.
- The link in `tzc400.c` was broken, and it didn't correctly direct to
the Technical Reference Manual it should. The link has been replaced
by the title of the document, which is more convenient when looking
for the document.
Change-Id: I89f60c25f635fd4c008a5d3a14028f814c147bbe
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| 6027796f | 11-Jan-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
TSPD: Require NS preemption along with EL3 exception handling
At present, the build option TSP_NS_INTR_ASYNC_PREEMPT controls how
Non-secure interrupt affects TSPs execution. When TSP is executing:
TSPD: Require NS preemption along with EL3 exception handling
At present, the build option TSP_NS_INTR_ASYNC_PREEMPT controls how
Non-secure interrupt affects TSPs execution. When TSP is executing:
1. When TSP_NS_INTR_ASYNC_PREEMPT=0, Non-secure interrupts are received
at the TSP's exception vector, and TSP voluntarily preempts itself.
2. When TSP_NS_INTR_ASYNC_PREEMPT=1, Non-secure interrupts causes a
trap to EL3, which preempts TSP execution.
When EL3 exception handling is in place (i.e.,
EL3_EXCEPTION_HANDLING=1), FIQs are always trapped to EL3. On a system
with GICv3, pending NS interrupts while TSP is executing will be
signalled as FIQ (which traps to EL3). This situation necessitates the
same treatment applied to case (2) above.
Therefore, when EL3 exception handling is in place, additionally
require that TSP_NS_INTR_ASYNC_PREEMPT is set to one 1.
Strictly speaking, this is not required on a system with GICv2, but the
same model is uniformly followed regardless, for simplicity.
Relevant documentation updated.
Change-Id: I928a8ed081fb0ac96e8b1dfe9375c98384da1ccd
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| 1dd022ca | 10-Jan-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
TSPD: Explicitly allow NS preemption for Yielding SMCs
When EL3 exception handling is in effect (i.e.,
EL3_EXCEPTION_HANDLING=1), Non-secure interrupts can't preempt Secure
execution. However, for y
TSPD: Explicitly allow NS preemption for Yielding SMCs
When EL3 exception handling is in effect (i.e.,
EL3_EXCEPTION_HANDLING=1), Non-secure interrupts can't preempt Secure
execution. However, for yielding SMCs, preemption by Non-secure
interupts is intended.
This patch therefore adds a call to ehf_allow_ns_preemption() before
dispatching a Yielding SMC to TSP.
Change-Id: Ia3a1ae252f3adc0f14e6d7e0502f251bdb349bdf
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| 64b33235 | 01-Feb-2018 |
Arve Hjønnevåg <arve@android.com> |
trusty: generic-arm64-smcall: Use SPDX license identifiers
Signed-off-by: Arve Hjønnevåg <arve@android.com> |
| 3a1b0676 | 19-Jan-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Implement support for SMCCC v1.1
SMCCC v1.1 comes with a relaxed calling convention for AArch64
callers. The caller only needs to save x0-x3 before doing an SMC
call.
This patch adds support for S
Implement support for SMCCC v1.1
SMCCC v1.1 comes with a relaxed calling convention for AArch64
callers. The caller only needs to save x0-x3 before doing an SMC
call.
This patch adds support for SMCCC_VERSION and SMCCC_ARCH_FEATURES.
Refer to "Firmware Interfaces for mitigating CVE_2017_5715 System
Software on Arm Systems"[0] for more information.
[0] https://developer.arm.com/-/media/developer/pdf/ARM%20DEN%200070A%20Firmware%20interfaces%20for%20mitigating%20CVE-2017-5715_V1.0.pdf
Change-Id: If5b1c55c17d6c5c7cb9c2c3ed355d3a91cdad0a9
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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| fab2319e | 27-Nov-2017 |
Arve Hjønnevåg <arve@android.com> |
trusty: Pass cpu suspend/resume reason to trusty
Add off/on argument to SMC_FC_CPU_SUSPEND SMC_FC_CPU_RESUME and pass
1 when called from the cpu on/off hooks.
Change-Id: Ie233c446fd38b3ff8546e445a8
trusty: Pass cpu suspend/resume reason to trusty
Add off/on argument to SMC_FC_CPU_SUSPEND SMC_FC_CPU_RESUME and pass
1 when called from the cpu on/off hooks.
Change-Id: Ie233c446fd38b3ff8546e445a8d86a15d2816093
Signed-off-by: Arve Hjønnevåg <arve@android.com>
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| 27d8e1e7 | 28-Sep-2017 |
Arve Hjønnevåg <arve@android.com> |
trusty: Run bl33 in EL1 instead of EL2 is trusty image is 32-bit
The secure physical timer is inacessible from 32-bit S-EL1 (when EL3
is 64-bit) so trusty will use the non-secure physical timer in t
trusty: Run bl33 in EL1 instead of EL2 is trusty image is 32-bit
The secure physical timer is inacessible from 32-bit S-EL1 (when EL3
is 64-bit) so trusty will use the non-secure physical timer in this
case. Linux will use the virtual timer instead of the physical timer
when started in EL1.
Change-Id: Ie49348d9a27e5287676dd4a77f678ecbd6c2309f
Signed-off-by: Arve Hjønnevåg <arve@android.com>
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| cb03c917 | 04-Aug-2015 |
Arve Hjønnevåg <arve@android.com> |
trusty: Add fpu/simd support
The original patch has been partly merged. This adds the missing
pieces.
Change-Id: I77fd434feab396ff05d9b8e0c1761e4dd588a701
Signed-off-by: Arve Hjønnevåg <arve@androi
trusty: Add fpu/simd support
The original patch has been partly merged. This adds the missing
pieces.
Change-Id: I77fd434feab396ff05d9b8e0c1761e4dd588a701
Signed-off-by: Arve Hjønnevåg <arve@android.com>
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|
| 61496151 | 13-May-2015 |
Arve Hjønnevåg <arve@android.com> |
trusty: Add generic-arm64 support
Add smc calls to return gic base address and print to the debug
console. Allows running a generic trusty binary.
Change-Id: I4b6540f140f11432cdff43c3f5a2097df09dc9
trusty: Add generic-arm64 support
Add smc calls to return gic base address and print to the debug
console. Allows running a generic trusty binary.
Change-Id: I4b6540f140f11432cdff43c3f5a2097df09dc9d1
Signed-off-by: Arve Hjønnevåg <arve@android.com>
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|
| 7c3309c9 | 28-Nov-2017 |
Arve Hjønnevåg <arve@android.com> |
trusty: Restore working trusty setup code and include trusty image in build
Change-Id: I081901e7df22f78dd9c4fc4c6bfad2aceb870a2d
Signed-off-by: Arve Hjønnevåg <arve@android.com> |
| 759a7be9 | 16-Jan-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1219 from antonio-nino-diaz-arm/an/mm-version
SPM: Fix version header definitions |
| a5b4c400 | 08-Jan-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
SPM: Fix version header definitions
Rename SP_VERSION macros to MM_VERSION, which is the name used in the MM
specification [1]. Also, a few more helper macros have been added.
MM-specific definitio
SPM: Fix version header definitions
Rename SP_VERSION macros to MM_VERSION, which is the name used in the MM
specification [1]. Also, a few more helper macros have been added.
MM-specific definitions have been moved to their own header file.
[1] http://infocenter.arm.com/help/topic/com.arm.doc.den0060a/DEN0060A_ARM_MM_Interface_Specification.pdf
Change-Id: Ia10e48c7e81a7a1f5eeca29a5270cae740a4a88a
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| 62d862eb | 08-Jan-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
spd: tlkd: support for "NS memory ranges" function ID
This patch adds support to receive function ID with NS world's
memory ranges to provide the memory snapshot to TLK.
Signed-off-by: Varun Wadeka
spd: tlkd: support for "NS memory ranges" function ID
This patch adds support to receive function ID with NS world's
memory ranges to provide the memory snapshot to TLK.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| a43c85db | 08-Jan-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
SPM: Allow secondary CPUs to use the Secure Partition
The Secure Partition should be able to be used from any CPU, not just
the lead one. This patch point the secure contexts of all secondary
CPUs t
SPM: Allow secondary CPUs to use the Secure Partition
The Secure Partition should be able to be used from any CPU, not just
the lead one. This patch point the secure contexts of all secondary
CPUs to the same one used by the lead CPU for the Secure Partition. This
way, they can also use it.
In order to prevent more than one CPU from using the Secure Partition at
the same time, a lock has been added.
Change-Id: Ica76373127c3626498b06c558a4874ce72201ff7
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| 26bd5f82 | 18-Dec-2017 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
SPM: Move initialization flag to context struct
Whether a Secure Partition is being initialized or not is something
related to that specific partition, so it should be saved with the
rest of the inf
SPM: Move initialization flag to context struct
Whether a Secure Partition is being initialized or not is something
related to that specific partition, so it should be saved with the
rest of the information related to it.
Change-Id: Ie8a780f70df83fb03ef9c01ba37960208d9b5319
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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|
| 4d2787ce | 07-Dec-2017 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
SPM: Fix MM_COMMUNICATE_AARCH32/64 parameters
This partially reverts commit d6b532b50f8, keeping only the fixes to
the assertions. The changes related to the order of arguments passed
to the secure
SPM: Fix MM_COMMUNICATE_AARCH32/64 parameters
This partially reverts commit d6b532b50f8, keeping only the fixes to
the assertions. The changes related to the order of arguments passed
to the secure partition were not correct and violated the
specification of the SP_EVENT_COMPLETE SMC.
This patch also improves the MM_COMMUNICATE argument validation. The
cookie argument, as it comes from normal world, can't be trusted and thus
needs to always be validated at run time rather than using an assertion.
Also validate the communication buffer address and return
INVALID_PARAMETER if it is zero, as per the MM specification.
Fix a few typos in comments and use the "secure partition" terminology
rather than "secure payload".
Change-Id: Ice6b7b5494b729dd44611f9a93d362c55ab244f7
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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| 83df7ce3 | 10-Dec-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1187 from antonio-nino-diaz-arm/an/spm-xlat-dram
SPM: Move S-EL1/S-EL0 xlat tables to TZC DRAM |
| 9f0ee04f | 09-Dec-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1184 from antonio-nino-diaz-arm/an/bl31-in-dram
fvp: Disable SYSTEM_SUSPEND when ARM_BL31_IN_DRAM |