| ac26b96b | 28-Jul-2016 |
Krishna Sitaraman <ksitaraman@nvidia.com> |
Tegra186: update t18x_ari.h to v3.0
This patch updates the ARI header to version 3.0
Change-Id: I7cfe0c61c80a6b78625232135dd63393602d32fe
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Si
Tegra186: update t18x_ari.h to v3.0
This patch updates the ARI header to version 3.0
Change-Id: I7cfe0c61c80a6b78625232135dd63393602d32fe
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 25621454 | 08-Aug-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: trampoline: update "System Suspend" exit criteria
The TZRAM memory loses its state during "System Suspend". This patch
check if TZRAM base address contains valid data, to decide if the sys
Tegra186: trampoline: update "System Suspend" exit criteria
The TZRAM memory loses its state during "System Suspend". This patch
check if TZRAM base address contains valid data, to decide if the system
is exiting from "System Suspend". To enable TZDRAM encryption, the Memory
Controller's TZDRAM base/size registers would be populated by the BPMP
when the system "wakes up".
Change-Id: I5fc8ba1ae3bce12f0ece493f6f9f5f4d92a46344
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 53451898 | 19-Jul-2016 |
Krishna Sitaraman <ksitaraman@nvidia.com> |
Tegra186: Add smc handler for coresight clock gating
This change adds function to invoke for MISC_CCPLEX ARI calls and
the corresponding smc handler. This can be used to enable/disable
Coresight clo
Tegra186: Add smc handler for coresight clock gating
This change adds function to invoke for MISC_CCPLEX ARI calls and
the corresponding smc handler. This can be used to enable/disable
Coresight clock gating.
Change-Id: I4bc17aa478a46c29bfe17fd74f839a383ee2b644
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 719f3ec2 | 29-Jul-2016 |
Harvey Hsieh <hhsieh@nvidia.com> |
Tegra: memctrl_v2: save TZDRAM settings to secure scratch registers
Save TZDRAM settings for SC7 resume firmware to restore.
SECURITY_BOM: MC_SECURITY_CFG0_0 = SECURE_RSV55_SCRATCH_0
SECURITY_B
Tegra: memctrl_v2: save TZDRAM settings to secure scratch registers
Save TZDRAM settings for SC7 resume firmware to restore.
SECURITY_BOM: MC_SECURITY_CFG0_0 = SECURE_RSV55_SCRATCH_0
SECURITY_BOM_HI: MC_SECURITY_CFG3_0 = SECURE_RSV55_SCRATCH_1
SECURITY_SIZE_MB: MC_SECURITY_CFG1_0 = SECURE_RSV54_SCRATCH_1
Change-Id: I78e891d9ebf576ff2a17ff87cf3aff4030ee11b8
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 6ef90b96 | 27-Jul-2016 |
Krishna Sitaraman <ksitaraman@nvidia.com> |
Tegra186: mce: fix return value for enum features ari
This patch fixes the incorrect return value that was being passed
back for the ENUM_FEATURES ARI call.
Change-Id: I3842c6ce27ea24698608830cf4c1
Tegra186: mce: fix return value for enum features ari
This patch fixes the incorrect return value that was being passed
back for the ENUM_FEATURES ARI call.
Change-Id: I3842c6ce27ea24698608830cf4c12cfa7ff64421
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 10007118 | 28-Jul-2016 |
Krishna Sitaraman <ksitaraman@nvidia.com> |
Tegra186: mce: clear reserved fields for ARI calls
This patch clears the unused or reserved ARI input registers
before issuing the actual ARI command.
Change-Id: I454b86566bfe088049a5c63527c1323d7b
Tegra186: mce: clear reserved fields for ARI calls
This patch clears the unused or reserved ARI input registers
before issuing the actual ARI command.
Change-Id: I454b86566bfe088049a5c63527c1323d7b25248a
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 4d045d0e | 05-Apr-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Build: add generic way to include SCP_BL2 into FIP image
If SCP_BL2 is passed in from the command line, it is recognized by
make_helpers/tbbr/tbbr_tools.mk, and the cert_create tool generates
the co
Build: add generic way to include SCP_BL2 into FIP image
If SCP_BL2 is passed in from the command line, it is recognized by
make_helpers/tbbr/tbbr_tools.mk, and the cert_create tool generates
the corresponding key and content certificates.
On the other hand, the top-level Makefile does not care SCP_BL2, so
the --scp-fw option is not passed to the fiptool. As far as I see
plat/arm/css/common/css_common.mk, it looks like a platform's job to
add $(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw)).
We can make the top-level Makefile kind enough to take care of it.
This is useful when we want to have optional SCP_BL2 firmware.
Adjust css_common.mk so that Juno still requires SCP_BL2 by default.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| b6dcbf58 | 04-Apr-2017 |
Paul Kocialkowski <contact@paulk.fr> |
rockchip: Remove unused rockchip_pd_pwr_down_wfi function
The rockchip_pd_pwr_down_wfi function is currently unused, which may
trigger compiler warnings or errors. Remove it.
Change-Id: I7e1b0ae092
rockchip: Remove unused rockchip_pd_pwr_down_wfi function
The rockchip_pd_pwr_down_wfi function is currently unused, which may
trigger compiler warnings or errors. Remove it.
Change-Id: I7e1b0ae092e8855528ac2065ecefc8bd45305f31
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
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| f9608bc8 | 08-Mar-2017 |
Douglas Raillard <douglas.raillard@arm.com> |
Fix ARM_BL31_IN_DRAM build
Some header files using the ULL() macro were not directly including
utils.h where the macro definition resides. As a consequence, a linker
script with values using this ma
Fix ARM_BL31_IN_DRAM build
Some header files using the ULL() macro were not directly including
utils.h where the macro definition resides. As a consequence, a linker
script with values using this macro did not see the macro definition
and kept the "ULL(<value>)" call in the preprocessed file, which lead to
link error.
Files using ULL() macro now include utils.h directly.
Change-Id: I433a7f36bd21a156c20e69bc2a2bb406140ebdf9
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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|
| e6d2aea1 | 28-Feb-2017 |
dp-arm <dimitris.papastamos@arm.com> |
Juno: Initialize stack protector canary from the trusted entropy source
Change-Id: I7f3e4bfd46613c6311ba4015d56705414fd6feab
Signed-off-by: dp-arm <dimitris.papastamos@arm.com> |
| df9a39ea | 27-Feb-2017 |
dp-arm <dimitris.papastamos@arm.com> |
Juno: Introduce juno_getentropy(void *buf, size_t len)
This function fills the buffer (first argument) with the specified
number of bytes (second argument) from the trusted entropy source.
This fun
Juno: Introduce juno_getentropy(void *buf, size_t len)
This function fills the buffer (first argument) with the specified
number of bytes (second argument) from the trusted entropy source.
This function will be used to initialize the stack protector canary.
Change-Id: Iff15aaf4778c13fa883ecb5528fcf9b8479d4489
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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|
| 51faada7 | 24-Feb-2017 |
Douglas Raillard <douglas.raillard@arm.com> |
Add support for GCC stack protection
Introduce new build option ENABLE_STACK_PROTECTOR. It enables
compilation of all BL images with one of the GCC -fstack-protector-*
options.
A new platform funct
Add support for GCC stack protection
Introduce new build option ENABLE_STACK_PROTECTOR. It enables
compilation of all BL images with one of the GCC -fstack-protector-*
options.
A new platform function plat_get_stack_protector_canary() is introduced.
It returns a value that is used to initialize the canary for stack
corruption detection. Returning a random value will prevent an attacker
from predicting the value and greatly increase the effectiveness of the
protection.
A message is printed at the ERROR level when a stack corruption is
detected.
To be effective, the global data must be stored at an address
lower than the base of the stacks. Failure to do so would allow an
attacker to overwrite the canary as part of an attack which would void
the protection.
FVP implementation of plat_get_stack_protector_canary is weak as
there is no real source of entropy on the FVP. It therefore relies on a
timer's value, which could be predictable.
Change-Id: Icaaee96392733b721fa7c86a81d03660d3c1bc06
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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|
| 801cf93c | 17-Feb-2017 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Add and use plat_crash_console_flush() API
This API makes sure that all the characters sent to the crash console
are output before returning from it.
Porting guide updated.
Change-Id: I1785f970a40
Add and use plat_crash_console_flush() API
This API makes sure that all the characters sent to the crash console
are output before returning from it.
Porting guide updated.
Change-Id: I1785f970a40f6aacfbe592b6a911b1f249bb2735
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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|
| ad4c2ec6 | 08-Feb-2017 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Add console_core_flush() in upstream platforms
It is needed to add placeholders for this function because, as this is
not a `plat_xxx()` function, there aren't weak definitions of it in any
file.
I
Add console_core_flush() in upstream platforms
It is needed to add placeholders for this function because, as this is
not a `plat_xxx()` function, there aren't weak definitions of it in any
file.
If `console_flush()` is used and there isn't an implementation of
`console_core_flush()` in any file, the compilation will fail.
Change-Id: I50eb56d085c4c9fbc85d40c343e86af6412f3020
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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|
| c61cd638 | 19-Jul-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: memctrl_v2: get chip revision using platform identifiers
This patch switches to the functions which identify the underlying
platform in order to calculate the chip SKU.
Change-Id: I20cf56234
Tegra: memctrl_v2: get chip revision using platform identifiers
This patch switches to the functions which identify the underlying
platform in order to calculate the chip SKU.
Change-Id: I20cf5623465289ccfab28d6578efcf762bfeb456
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 524bd090 | 19-Jul-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: mce: read MCE's firmware version on "real" platforms
This patch runs the MCE firmware's version check only if the underlying
platform has the capability to the run the firmware. MCE firmwa
Tegra186: mce: read MCE's firmware version on "real" platforms
This patch runs the MCE firmware's version check only if the underlying
platform has the capability to the run the firmware. MCE firmware is not
running on simulation platforms, identified by v0.3 or v0.6, read from the
Tegra Chip ID value.
Change-Id: I3b1788b1ee2a0d4464017bb879ac5792cb7022b8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 2b04f927 | 19-Jul-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: use helper functions to get major/minor version
This patch uses helper functions to read the chips's major and minor
version values.
Change-Id: I5b2530a31af5ab3778a8aa63380def4e9f9ee6ec
S
Tegra186: use helper functions to get major/minor version
This patch uses helper functions to read the chips's major and minor
version values.
Change-Id: I5b2530a31af5ab3778a8aa63380def4e9f9ee6ec
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 49cbbc4e | 12-Jul-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: memmap all UART controllers
This patch adds all the UART controllers to the memory map.
Change-Id: I035e55ca7bff0a96115102f2295981f9e3a5da6b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.
Tegra186: memmap all UART controllers
This patch adds all the UART controllers to the memory map.
Change-Id: I035e55ca7bff0a96115102f2295981f9e3a5da6b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 9c2a3d8a | 02-Jun-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: implement plat_get_syscnt_freq2()
Commit f3d3b316f82faa88e42f3d09c97cd9e52ac92599 replaced
plat_get_syscnt_freq by plat_get_syscnt_freq2 on all the
upstream platforms. This patch modifies
Tegra186: implement plat_get_syscnt_freq2()
Commit f3d3b316f82faa88e42f3d09c97cd9e52ac92599 replaced
plat_get_syscnt_freq by plat_get_syscnt_freq2 on all the
upstream platforms. This patch modifies the Tegra186 code
which is not present usptream, yet.
Change-Id: Ieda6168050a7769680a3a94513637fed03463a2d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 698f4250 | 21-Apr-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: smmu: disable TCU prefetch for all the 64 contexts
This patch disables TCU prefetch for all the contexts in order
to improve SMMU performance.
Change-Id: I82ca49a0e396d9f064f5c62a5f00c4b2101
Tegra: smmu: disable TCU prefetch for all the 64 contexts
This patch disables TCU prefetch for all the contexts in order
to improve SMMU performance.
Change-Id: I82ca49a0e396d9f064f5c62a5f00c4b2101d8459
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 48afb167 | 23-May-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: handlers to get BL31 arguments from previous bootloader
This patch overrides the default handlers to get BL31 arguments from the
previous bootloader. The previous bootloader stores the poi
Tegra186: handlers to get BL31 arguments from previous bootloader
This patch overrides the default handlers to get BL31 arguments from the
previous bootloader. The previous bootloader stores the pointer to the
arguments in PMC secure scratch register #53.
BL31 is the first component running on the CPU, as there isn't a previous
bootloader. We set the RESET_TO_BL31 flag to enable the path which assumes
that there are no input parameters passed by the previous bootloader.
Change-Id: Idacc1df292a70c9c1cb4d5c3a774bd796175d5e8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 962014f5 | 01-Jun-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: delete 'Video Memory Carveout' handling
This patch removes duplicate code from the platform's SiP handler
routine for processing Video Memory Carveout region requests and
uses the common S
Tegra186: delete 'Video Memory Carveout' handling
This patch removes duplicate code from the platform's SiP handler
routine for processing Video Memory Carveout region requests and
uses the common SiP handler instead.
Change-Id: Ib307de017fd88d5ed3c816288327cae750a67806
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 2f583f8e | 25-May-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: memctrl_v2: TZRAM aperture configuration settings
This patch enables the configuration settings for the TZRAM
aperture by programming the base/size of the aperture and
restricting access to i
Tegra: memctrl_v2: TZRAM aperture configuration settings
This patch enables the configuration settings for the TZRAM
aperture by programming the base/size of the aperture and
restricting access to it. We allow only the CPU to read/write
by programming the access configuration registers to 0.
Change-Id: Ie16ad29f4c5ec7aafa972b0a0230b4790ad5619e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 512da21a | 29-Apr-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: modify the return type for `plat_get_syscnt_freq()`
Commit c073fda1c692d7c74415d26fb483d6336330fcc0 upstream changed the
return type for `plat_get_syscnt_freq()` from uint64_t to unsigned
Tegra186: modify the return type for `plat_get_syscnt_freq()`
Commit c073fda1c692d7c74415d26fb483d6336330fcc0 upstream changed the
return type for `plat_get_syscnt_freq()` from uint64_t to unsigned
long long.
This patch modifies the return type for the Tegra186 platform.
Change-Id: Ic9e5c364b90972265576e271582a4347e5eaa6eb
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 1eed3838 | 18-May-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: Enable ECC and Parity Protection for A02p SKUs
This patch enables ECC and Parity Protection for Cortex-A57 CPUs during boot,
for Tegra186 A02p SKUs.
Change-Id: I8522a6cb61f5e4fa9e0471f558
Tegra186: Enable ECC and Parity Protection for A02p SKUs
This patch enables ECC and Parity Protection for Cortex-A57 CPUs during boot,
for Tegra186 A02p SKUs.
Change-Id: I8522a6cb61f5e4fa9e0471f558a0c3ee8078370e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|