1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <bl31.h> 34 #include <bl_common.h> 35 #include <console.h> 36 #include <context.h> 37 #include <context_mgmt.h> 38 #include <cortex_a57.h> 39 #include <debug.h> 40 #include <denver.h> 41 #include <interrupt_mgmt.h> 42 #include <mce.h> 43 #include <platform.h> 44 #include <tegra_def.h> 45 #include <tegra_private.h> 46 #include <xlat_tables.h> 47 48 DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1) 49 extern uint64_t tegra_enable_l2_ecc_parity_prot; 50 51 /******************************************************************************* 52 * The Tegra power domain tree has a single system level power domain i.e. a 53 * single root node. The first entry in the power domain descriptor specifies 54 * the number of power domains at the highest power level. 55 ******************************************************************************* 56 */ 57 const unsigned char tegra_power_domain_tree_desc[] = { 58 /* No of root nodes */ 59 1, 60 /* No of clusters */ 61 PLATFORM_CLUSTER_COUNT, 62 /* No of CPU cores - cluster0 */ 63 PLATFORM_MAX_CPUS_PER_CLUSTER, 64 /* No of CPU cores - cluster1 */ 65 PLATFORM_MAX_CPUS_PER_CLUSTER 66 }; 67 68 /* 69 * Table of regions to map using the MMU. 70 */ 71 static const mmap_region_t tegra_mmap[] = { 72 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 73 MT_DEVICE | MT_RW | MT_SECURE), 74 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ 75 MT_DEVICE | MT_RW | MT_SECURE), 76 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 77 MT_DEVICE | MT_RW | MT_SECURE), 78 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 79 MT_DEVICE | MT_RW | MT_SECURE), 80 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB */ 81 MT_DEVICE | MT_RW | MT_SECURE), 82 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ 83 MT_DEVICE | MT_RW | MT_SECURE), 84 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 85 MT_DEVICE | MT_RW | MT_SECURE), 86 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ 87 MT_DEVICE | MT_RW | MT_SECURE), 88 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ 89 MT_DEVICE | MT_RW | MT_SECURE), 90 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ 91 MT_DEVICE | MT_RW | MT_SECURE), 92 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 93 MT_DEVICE | MT_RW | MT_SECURE), 94 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 95 MT_DEVICE | MT_RW | MT_SECURE), 96 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ 97 MT_DEVICE | MT_RW | MT_SECURE), 98 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 99 MT_DEVICE | MT_RW | MT_SECURE), 100 MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x1000000, /* 64KB */ 101 MT_DEVICE | MT_RW | MT_SECURE), 102 {0} 103 }; 104 105 /******************************************************************************* 106 * Set up the pagetables as per the platform memory map & initialize the MMU 107 ******************************************************************************/ 108 const mmap_region_t *plat_get_mmio_map(void) 109 { 110 /* MMIO space */ 111 return tegra_mmap; 112 } 113 114 /******************************************************************************* 115 * Handler to get the System Counter Frequency 116 ******************************************************************************/ 117 unsigned int plat_get_syscnt_freq2(void) 118 { 119 return 31250000; 120 } 121 122 /******************************************************************************* 123 * Maximum supported UART controllers 124 ******************************************************************************/ 125 #define TEGRA186_MAX_UART_PORTS 7 126 127 /******************************************************************************* 128 * This variable holds the UART port base addresses 129 ******************************************************************************/ 130 static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 131 0, /* undefined - treated as an error case */ 132 TEGRA_UARTA_BASE, 133 TEGRA_UARTB_BASE, 134 TEGRA_UARTC_BASE, 135 TEGRA_UARTD_BASE, 136 TEGRA_UARTE_BASE, 137 TEGRA_UARTF_BASE, 138 TEGRA_UARTG_BASE, 139 }; 140 141 /******************************************************************************* 142 * Retrieve the UART controller base to be used as the console 143 ******************************************************************************/ 144 uint32_t plat_get_console_from_id(int id) 145 { 146 if (id > TEGRA186_MAX_UART_PORTS) 147 return 0; 148 149 return tegra186_uart_addresses[id]; 150 } 151 152 /* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */ 153 #define TEGRA186_VER_A02P 0x1201 154 155 /******************************************************************************* 156 * Handler for early platform setup 157 ******************************************************************************/ 158 void plat_early_platform_setup(void) 159 { 160 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 161 uint32_t chip_minor, chip_major, chip_subrev, val; 162 163 /* sanity check MCE firmware compatibility */ 164 mce_verify_firmware_version(); 165 166 /* 167 * Enable ECC and Parity Protection for Cortex-A57 CPUs 168 * for Tegra A02p SKUs 169 */ 170 if (impl != DENVER_IMPL) { 171 172 /* get the major, minor and sub-version values */ 173 chip_major = (mmio_read_32(TEGRA_MISC_BASE + 174 HARDWARE_REVISION_OFFSET) >> 175 MAJOR_VERSION_SHIFT) & MAJOR_VERSION_MASK; 176 chip_minor = (mmio_read_32(TEGRA_MISC_BASE + 177 HARDWARE_REVISION_OFFSET) >> 178 MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK; 179 chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) & 180 SUBREVISION_MASK; 181 182 /* prepare chip version number */ 183 val = (chip_major << 12) | (chip_minor << 8) | chip_subrev; 184 185 /* enable L2 ECC for Tegra186 A02P and beyond */ 186 if (val >= TEGRA186_VER_A02P) { 187 188 val = read_l2ctlr_el1(); 189 val |= L2_ECC_PARITY_PROTECTION_BIT; 190 write_l2ctlr_el1(val); 191 192 /* 193 * Set the flag to enable ECC/Parity Protection 194 * when we exit System Suspend or Cluster Powerdn 195 */ 196 tegra_enable_l2_ecc_parity_prot = 1; 197 } 198 } 199 } 200 201 /* Secure IRQs for Tegra186 */ 202 static const irq_sec_cfg_t tegra186_sec_irqs[] = { 203 { 204 TEGRA186_TOP_WDT_IRQ, 205 TEGRA186_SEC_IRQ_TARGET_MASK, 206 INTR_TYPE_EL3, 207 }, 208 { 209 TEGRA186_AON_WDT_IRQ, 210 TEGRA186_SEC_IRQ_TARGET_MASK, 211 INTR_TYPE_EL3, 212 }, 213 }; 214 215 /******************************************************************************* 216 * Initialize the GIC and SGIs 217 ******************************************************************************/ 218 void plat_gic_setup(void) 219 { 220 tegra_gic_setup(tegra186_sec_irqs, 221 sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); 222 223 /* 224 * Initialize the FIQ handler only if the platform supports any 225 * FIQ interrupt sources. 226 */ 227 if (sizeof(tegra186_sec_irqs) > 0) 228 tegra_fiq_handler_setup(); 229 } 230 231 /******************************************************************************* 232 * Return pointer to the BL31 params from previous bootloader 233 ******************************************************************************/ 234 bl31_params_t *plat_get_bl31_params(void) 235 { 236 uint32_t val; 237 238 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); 239 240 return (bl31_params_t *)(uintptr_t)val; 241 } 242 243 /******************************************************************************* 244 * Return pointer to the BL31 platform params from previous bootloader 245 ******************************************************************************/ 246 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 247 { 248 uint32_t val; 249 250 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); 251 252 return (plat_params_from_bl2_t *)(uintptr_t)val; 253 } 254