1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <bl31.h> 34 #include <bl_common.h> 35 #include <console.h> 36 #include <context.h> 37 #include <context_mgmt.h> 38 #include <cortex_a57.h> 39 #include <debug.h> 40 #include <denver.h> 41 #include <interrupt_mgmt.h> 42 #include <mce.h> 43 #include <platform.h> 44 #include <tegra_def.h> 45 #include <tegra_private.h> 46 #include <xlat_tables.h> 47 48 DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1) 49 extern uint64_t tegra_enable_l2_ecc_parity_prot; 50 51 /******************************************************************************* 52 * The Tegra power domain tree has a single system level power domain i.e. a 53 * single root node. The first entry in the power domain descriptor specifies 54 * the number of power domains at the highest power level. 55 ******************************************************************************* 56 */ 57 const unsigned char tegra_power_domain_tree_desc[] = { 58 /* No of root nodes */ 59 1, 60 /* No of clusters */ 61 PLATFORM_CLUSTER_COUNT, 62 /* No of CPU cores - cluster0 */ 63 PLATFORM_MAX_CPUS_PER_CLUSTER, 64 /* No of CPU cores - cluster1 */ 65 PLATFORM_MAX_CPUS_PER_CLUSTER 66 }; 67 68 /* 69 * Table of regions to map using the MMU. 70 */ 71 static const mmap_region_t tegra_mmap[] = { 72 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 73 MT_DEVICE | MT_RW | MT_SECURE), 74 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ 75 MT_DEVICE | MT_RW | MT_SECURE), 76 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 77 MT_DEVICE | MT_RW | MT_SECURE), 78 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 79 MT_DEVICE | MT_RW | MT_SECURE), 80 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/ 81 MT_DEVICE | MT_RW | MT_SECURE), 82 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */ 83 MT_DEVICE | MT_RW | MT_SECURE), 84 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */ 85 MT_DEVICE | MT_RW | MT_SECURE), 86 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ 87 MT_DEVICE | MT_RW | MT_SECURE), 88 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 89 MT_DEVICE | MT_RW | MT_SECURE), 90 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ 91 MT_DEVICE | MT_RW | MT_SECURE), 92 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ 93 MT_DEVICE | MT_RW | MT_SECURE), 94 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ 95 MT_DEVICE | MT_RW | MT_SECURE), 96 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 97 MT_DEVICE | MT_RW | MT_SECURE), 98 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 99 MT_DEVICE | MT_RW | MT_SECURE), 100 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ 101 MT_DEVICE | MT_RW | MT_SECURE), 102 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 103 MT_DEVICE | MT_RW | MT_SECURE), 104 MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x1000000, /* 64KB */ 105 MT_DEVICE | MT_RW | MT_SECURE), 106 {0} 107 }; 108 109 /******************************************************************************* 110 * Set up the pagetables as per the platform memory map & initialize the MMU 111 ******************************************************************************/ 112 const mmap_region_t *plat_get_mmio_map(void) 113 { 114 /* MMIO space */ 115 return tegra_mmap; 116 } 117 118 /******************************************************************************* 119 * Handler to get the System Counter Frequency 120 ******************************************************************************/ 121 unsigned int plat_get_syscnt_freq2(void) 122 { 123 return 31250000; 124 } 125 126 /******************************************************************************* 127 * Maximum supported UART controllers 128 ******************************************************************************/ 129 #define TEGRA186_MAX_UART_PORTS 7 130 131 /******************************************************************************* 132 * This variable holds the UART port base addresses 133 ******************************************************************************/ 134 static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 135 0, /* undefined - treated as an error case */ 136 TEGRA_UARTA_BASE, 137 TEGRA_UARTB_BASE, 138 TEGRA_UARTC_BASE, 139 TEGRA_UARTD_BASE, 140 TEGRA_UARTE_BASE, 141 TEGRA_UARTF_BASE, 142 TEGRA_UARTG_BASE, 143 }; 144 145 /******************************************************************************* 146 * Retrieve the UART controller base to be used as the console 147 ******************************************************************************/ 148 uint32_t plat_get_console_from_id(int id) 149 { 150 if (id > TEGRA186_MAX_UART_PORTS) 151 return 0; 152 153 return tegra186_uart_addresses[id]; 154 } 155 156 /* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */ 157 #define TEGRA186_VER_A02P 0x1201 158 159 /******************************************************************************* 160 * Handler for early platform setup 161 ******************************************************************************/ 162 void plat_early_platform_setup(void) 163 { 164 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 165 uint32_t chip_minor, chip_major, chip_subrev, val; 166 167 /* sanity check MCE firmware compatibility */ 168 mce_verify_firmware_version(); 169 170 /* 171 * Enable ECC and Parity Protection for Cortex-A57 CPUs 172 * for Tegra A02p SKUs 173 */ 174 if (impl != DENVER_IMPL) { 175 176 /* get the major, minor and sub-version values */ 177 chip_major = (mmio_read_32(TEGRA_MISC_BASE + 178 HARDWARE_REVISION_OFFSET) >> 179 MAJOR_VERSION_SHIFT) & MAJOR_VERSION_MASK; 180 chip_minor = (mmio_read_32(TEGRA_MISC_BASE + 181 HARDWARE_REVISION_OFFSET) >> 182 MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK; 183 chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) & 184 SUBREVISION_MASK; 185 186 /* prepare chip version number */ 187 val = (chip_major << 12) | (chip_minor << 8) | chip_subrev; 188 189 /* enable L2 ECC for Tegra186 A02P and beyond */ 190 if (val >= TEGRA186_VER_A02P) { 191 192 val = read_l2ctlr_el1(); 193 val |= L2_ECC_PARITY_PROTECTION_BIT; 194 write_l2ctlr_el1(val); 195 196 /* 197 * Set the flag to enable ECC/Parity Protection 198 * when we exit System Suspend or Cluster Powerdn 199 */ 200 tegra_enable_l2_ecc_parity_prot = 1; 201 } 202 } 203 } 204 205 /* Secure IRQs for Tegra186 */ 206 static const irq_sec_cfg_t tegra186_sec_irqs[] = { 207 { 208 TEGRA186_TOP_WDT_IRQ, 209 TEGRA186_SEC_IRQ_TARGET_MASK, 210 INTR_TYPE_EL3, 211 }, 212 { 213 TEGRA186_AON_WDT_IRQ, 214 TEGRA186_SEC_IRQ_TARGET_MASK, 215 INTR_TYPE_EL3, 216 }, 217 }; 218 219 /******************************************************************************* 220 * Initialize the GIC and SGIs 221 ******************************************************************************/ 222 void plat_gic_setup(void) 223 { 224 tegra_gic_setup(tegra186_sec_irqs, 225 sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0])); 226 227 /* 228 * Initialize the FIQ handler only if the platform supports any 229 * FIQ interrupt sources. 230 */ 231 if (sizeof(tegra186_sec_irqs) > 0) 232 tegra_fiq_handler_setup(); 233 } 234 235 /******************************************************************************* 236 * Return pointer to the BL31 params from previous bootloader 237 ******************************************************************************/ 238 bl31_params_t *plat_get_bl31_params(void) 239 { 240 uint32_t val; 241 242 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); 243 244 return (bl31_params_t *)(uintptr_t)val; 245 } 246 247 /******************************************************************************* 248 * Return pointer to the BL31 platform params from previous bootloader 249 ******************************************************************************/ 250 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 251 { 252 uint32_t val; 253 254 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); 255 256 return (plat_params_from_bl2_t *)(uintptr_t)val; 257 } 258