Merge "fix(intel): update ssbl naming conventions" into integration

fix(arm): resolve build issue with ARM_ROTPK_LOCATION=regs option

Fix the broken build when using the ARM_ROTPK_LOCATION=regs option.

Change-Id: Ieaa7baebd86448d198a1b9d2149a3490700b45d3
Signed-off

fix(arm): resolve build issue with ARM_ROTPK_LOCATION=regs option

Fix the broken build when using the ARM_ROTPK_LOCATION=regs option.

Change-Id: Ieaa7baebd86448d198a1b9d2149a3490700b45d3
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...

fix(arm): resolve misra rule R11.6 violation

Fixed below MISRA violation:
- MISRA violation: MC3R1.R11.6:
- A cast shall not be performed between a pointer to void and an
arithmetic data type.

fix(arm): resolve misra rule R11.6 violation

Fixed below MISRA violation:
- MISRA violation: MC3R1.R11.6:
- A cast shall not be performed between a pointer to void and an
arithmetic data type. (i.e cast from integer to void*)
- Fix:
- cast via portable and misra compliant type "uintptr_t" and
use 0U instead of NULL for comparisons.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ie3a7561d9a254027c5364485a1d72fc1320dfcad

show more ...

feat(tc): port BL31-BL33 interface to firmware handoff framework

Adding support for this framework at the handoff boundary between
firmware stage BL31 and BL33 on TC.

Signed-off-by: Jayanth Dodderi

feat(tc): port BL31-BL33 interface to firmware handoff framework

Adding support for this framework at the handoff boundary between
firmware stage BL31 and BL33 on TC.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ia6cd29c8b6cdda0a127a3bac02f6fa1dcfc07151

show more ...

feat(tc): port BL2-BL31 interface to firmware handoff framework

Adding support for this framework at the handoff boundary between
firmware stage BL2 and BL31 on TC.

Signed-off-by: Jayanth Dodderi C

feat(tc): port BL2-BL31 interface to firmware handoff framework

Adding support for this framework at the handoff boundary between
firmware stage BL2 and BL31 on TC.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I8e29b859e57a732e53f7532a5869ed4c8665b161

show more ...

feat(tc): port BL1-BL2 interface to firmware handoff framework

The firmware handoff framework, is a light weight mechanism for
sharing information between bootloader stages.
Adding support for this

feat(tc): port BL1-BL2 interface to firmware handoff framework

The firmware handoff framework, is a light weight mechanism for
sharing information between bootloader stages.
Adding support for this framework at the handoff boundary between
firmware stage BL1 and BL2 on TC.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Iae13adbcdd6ebbdcc61d04e017655c6b8d715ea0

show more ...

feat(stm32mp2): use USART1 for debug console on ultra-fly boards

This commit configures the debug console to use USART1 for
ultra-fly boards, ensuring the early console works as expected
on these bo

feat(stm32mp2): use USART1 for debug console on ultra-fly boards

This commit configures the debug console to use USART1 for
ultra-fly boards, ensuring the early console works as expected
on these boards.

These changes are specific to the ultra-fly boards and do not
affect any other boards.

Change-Id: I17f2c50779426dc31a8e85d6903141c331882c86
Signed-off-by: Boerge Struempfel <boerge.struempfel@gmail.com>

show more ...

Merge "feat(versal2): is OCM configured as coherent" into integration

Merge changes from topic "versal2-qemu" into integration

* changes:
fix(versal2): align QEMU APU GT frequency with silicon
fix(zynqmp): fix syscnt frequency for QEMU

Merge "fix(cpus): remove errata setting PF_MODE to conservative" into integration

Merge changes from topic "jc/tc_fw_handoff" into integration

* changes:
refactor(arm): simplify early platform setup function in BL31
refactor(arm): simplify early platform setup function in BL2

Merge changes from topic "jc/tc_fw_handoff" into integration

* changes:
refactor(arm): simplify early platform setup function in BL31
refactor(arm): simplify early platform setup function in BL2
feat(arm): add support for Transfer List creation

show more ...

Merge changes I1dfb95aa,I9eb61c48 into integration

* changes:
feat(intel): support FCS commands with SiPSVC V3 framework
feat(intel): implementation of SiPSVC-V3 protocol framework

fix(intel): update ssbl naming conventions

Update RSU SSBL name query in line with other bootloaders
and use secure string functions.

Change-Id: I8ae6b80eb74e91c6a82e59986cba137cf5ef6977
Signed-off

fix(intel): update ssbl naming conventions

Update RSU SSBL name query in line with other bootloaders
and use secure string functions.

Change-Id: I8ae6b80eb74e91c6a82e59986cba137cf5ef6977
Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>

show more ...

refactor(arm): simplify early platform setup function in BL31

Refactor `arm_bl31_early_platform_setup` to accept generic u_register_t
values, enabling support for firmware handoff boot arguments in

refactor(arm): simplify early platform setup function in BL31

Refactor `arm_bl31_early_platform_setup` to accept generic u_register_t
values, enabling support for firmware handoff boot arguments in
common code. This simplifies the interface for early platform setup.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Iff20300d2372e1a9825827ddccbd1b3bc6751e40

show more ...

refactor(arm): simplify early platform setup function in BL2

Refactor `arm_bl2_early_platform_setup` to accept generic u_register_t
values, enabling support for firmware handoff boot arguments in
co

refactor(arm): simplify early platform setup function in BL2

Refactor `arm_bl2_early_platform_setup` to accept generic u_register_t
values, enabling support for firmware handoff boot arguments in
common code. This simplifies the interface for early platform setup.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ie0dbe4d32bbef22bd185fdafe50091a2ea5f550f

show more ...

feat(arm): add support for Transfer List creation

This patch introduces Firmware Handoff support for Arm based
platforms listed under Firmware_Handoff specification.
[https://firmwarehandoff.github.

feat(arm): add support for Transfer List creation

This patch introduces Firmware Handoff support for Arm based
platforms listed under Firmware_Handoff specification.
[https://firmwarehandoff.github.io/firmware_handoff/main/transfer_list.html]

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ie3f30ffe38f809db907b663a8dbf1e48944ec690

show more ...

fix(fvp): allow PSCI 0.2 in the device tree

Although the platform assumes it will use the device tree hosted with
it, there are device trees out there (eg in Linux) that will also work
just fine. So

fix(fvp): allow PSCI 0.2 in the device tree

Although the platform assumes it will use the device tree hosted with
it, there are device trees out there (eg in Linux) that will also work
just fine. Some of them, unfortunately, specify PSCI 0.2, but FCONF
performs a fatal check for 1.0. Add a fallback to 0.2 so that those
device trees can work.

Change-Id: I1543aa6d1dd12730299078500685928a13b16820
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A

fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A. The current workaround attempts to follow option 2 but
misapplies it. Specifically, it statically sets PF_MODE to
conservative, which is not the recommended approach. According to the
erratum documentation, PF_MODE should be configured in conservative
mode only when we disable data prefetcher however this is not done
in TF-A and thus the workaround is not needed in TF-A.

The static setting of PF_MODE in TF-A does not correctly address the
erratum and may introduce unnecessary performance degradation on
platforms that adopt it without fully understanding its implications.

To prevent incorrect or unintended use, the current implementation of
this erratum workaround should be removed from TF-A and not adopted by
platforms.

List of Impacted CPU's with Errata Numbers and reference to SDEN -

Cortex-A78 - 2132060 - https://developer.arm.com/documentation/SDEN1401784/latest
Cortex-A78C - 2132064 - https://developer.arm.com/documentation/SDEN-2004089/latest
Cortex-A710 - 2058056 - https://developer.arm.com/documentation/SDEN-1775101/latest
Cortex-X2 - 2058056 - https://developer.arm.com/documentation/SDEN-1775100/latest
Cortex-X3 - 2070301 - https://developer.arm.com/documentation/SDEN2055130/latest
Neoverse-N2 - 2138953 - https://developer.arm.com/documentation/SDEN-1982442/latest
Neoverse-V1 - 2108267 - https://developer.arm.com/documentation/SDEN-1401781/latest
Neoverse-V2 - 2331132 - https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: Icf4048508ae070b2df073cc46c63be058b2779df
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...

fix(versal2): align QEMU APU GT frequency with silicon

The APU generic timer frequency in QEMU is now aligned on silicon to the
value of 100MHz.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Chang

fix(versal2): align QEMU APU GT frequency with silicon

The APU generic timer frequency in QEMU is now aligned on silicon to the
value of 100MHz.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Change-Id: I4ef0a040c14fdb2fbb3f2d9d4e6ca6ee8ac8e229

show more ...

fix(zynqmp): fix syscnt frequency for QEMU

QEMU uses a 62.5MHz clock frequency for the ARM generic timers.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Change-Id: Ib846e17feb3cd44878a62add320fa47

fix(zynqmp): fix syscnt frequency for QEMU

QEMU uses a 62.5MHz clock frequency for the ARM generic timers.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Change-Id: Ib846e17feb3cd44878a62add320fa4795fd5c69e

show more ...

feat(versal2): is OCM configured as coherent

Warn users about disabled OCM coherency which is not enabled by
default in designs. If it is not enabled and TF-A is running out
of OCM,TF-A won't work p

feat(versal2): is OCM configured as coherent

Warn users about disabled OCM coherency which is not enabled by
default in designs. If it is not enabled and TF-A is running out
of OCM,TF-A won't work properly.
This check is done only in Debug mode and isolation disabled.

Change-Id: I7661e0183503b71085c57fa35014341d14522203
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

show more ...

Merge "feat(rmmd): verify FEAT_MEC present before calling plat hoook" into integration

feat(rmmd): verify FEAT_MEC present before calling plat hoook

Some platforms do not support FEAT_MEC. Hence, they do not provide
an interface to update the update of the key corresponding to a
MECID

feat(rmmd): verify FEAT_MEC present before calling plat hoook

Some platforms do not support FEAT_MEC. Hence, they do not provide
an interface to update the update of the key corresponding to a
MECID.

This patch adds a condition in order to verify FEAT_MEC is present
before calling the corresponding platform hook, thus preventing it
from being called when the platform does not support the feature.

Change-Id: Ib1eb9e42f475e27ec31529569e888b93b207148c
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

show more ...

fix(versal): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: I3d07808821da3bdd46be819ad829cb284f9d53d3
Signed-off-by:

fix(versal): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: I3d07808821da3bdd46be819ad829cb284f9d53d3
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

fix(versal-net): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: I153d26bd92ea26efcd7f236e2f1d89c3e5442ba4
Signed-off-

fix(versal-net): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: I153d26bd92ea26efcd7f236e2f1d89c3e5442ba4
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...