1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25ifeq (${HW_ASSISTED_COHERENCY}, 0) 26FVP_DT_PREFIX := fvp-base-gicv3-psci 27else 28FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 29endif 30# fdts is wrong otherwise 31 32# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 33# the FVP platform. 34ifeq (${ENABLE_RME},1) 35FVP_TRUSTED_SRAM_SIZE := 384 36else 37FVP_TRUSTED_SRAM_SIZE := 256 38endif 39 40# Macro to enable helpers for running SPM tests. Disabled by default. 41PLAT_TEST_SPM := 0 42 43# By default dont build CPUs with no FVP model. 44BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 45 46ENABLE_FEAT_AMU := 2 47ENABLE_FEAT_AMUv1p1 := 2 48ENABLE_FEAT_HCX := 2 49ENABLE_FEAT_RNG := 2 50ENABLE_FEAT_TWED := 2 51ENABLE_FEAT_GCS := 2 52 53ifeq (${ARCH}, aarch64) 54 55ifeq (${SPM_MM}, 0) 56ifeq (${CTX_INCLUDE_FPREGS}, 0) 57 ENABLE_SME_FOR_NS := 2 58 ENABLE_SME2_FOR_NS := 2 59else 60 ENABLE_SVE_FOR_NS := 0 61 ENABLE_SME_FOR_NS := 0 62 ENABLE_SME2_FOR_NS := 0 63endif 64endif 65 66 ENABLE_BRBE_FOR_NS := 2 67 ENABLE_TRBE_FOR_NS := 2 68 ENABLE_FEAT_D128 := 2 69 ENABLE_FEAT_FPMR := 2 70 ENABLE_FEAT_MOPS := 2 71endif 72 73ENABLE_SYS_REG_TRACE_FOR_NS := 2 74ENABLE_FEAT_CSV2_2 := 2 75ENABLE_FEAT_CSV2_3 := 2 76ENABLE_FEAT_DEBUGV8P9 := 2 77ENABLE_FEAT_DIT := 2 78ENABLE_FEAT_PAN := 2 79ENABLE_FEAT_VHE := 2 80CTX_INCLUDE_NEVE_REGS := 2 81ENABLE_FEAT_SEL2 := 2 82ENABLE_TRF_FOR_NS := 2 83ENABLE_FEAT_ECV := 2 84ENABLE_FEAT_FGT := 2 85ENABLE_FEAT_FGT2 := 2 86ENABLE_FEAT_THE := 2 87ENABLE_FEAT_TCR2 := 2 88ENABLE_FEAT_S2PIE := 2 89ENABLE_FEAT_S1PIE := 2 90ENABLE_FEAT_S2POE := 2 91ENABLE_FEAT_S1POE := 2 92ENABLE_FEAT_SCTLR2 := 2 93ENABLE_FEAT_MTE2 := 2 94ENABLE_FEAT_LS64_ACCDATA := 2 95 96ifeq (${ENABLE_RME},1) 97 ENABLE_FEAT_MEC := 2 98 RMMD_ENABLE_IDE_KEY_PROG := 1 99endif 100 101# The FVP platform depends on this macro to build with correct GIC driver. 102$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 103 104# Pass FVP_CLUSTER_COUNT to the build system. 105$(eval $(call add_define,FVP_CLUSTER_COUNT)) 106 107# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 108$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 109 110# Pass FVP_MAX_PE_PER_CPU to the build system. 111$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 112 113# Pass FVP_GICR_REGION_PROTECTION to the build system. 114$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 115 116# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 117$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 118 119# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 120# choose the CCI driver , else the CCN driver 121ifeq ($(FVP_CLUSTER_COUNT), 0) 122$(error "Incorrect cluster count specified for FVP port") 123else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 124FVP_INTERCONNECT_DRIVER := FVP_CCI 125else 126FVP_INTERCONNECT_DRIVER := FVP_CCN 127endif 128 129$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 130 131# Choose the GIC sources depending upon the how the FVP will be invoked 132ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 133 134# The GIC model (GIC-600 or GIC-500) will be detected at runtime 135GICV3_SUPPORT_GIC600 := 1 136GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 137 138# Include GICv3 driver files 139include drivers/arm/gic/v3/gicv3.mk 140 141FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 142 plat/common/plat_gicv3.c \ 143 plat/common/plat_gicv3_base.c \ 144 plat/arm/board/fvp/fvp_gicv3.c 145 146else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 147 148# No GICv4 extension 149GIC_ENABLE_V4_EXTN := 0 150$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 151 152# Include GICv2 driver files 153include drivers/arm/gic/v2/gicv2.mk 154 155FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 156 plat/common/plat_gicv2.c \ 157 plat/common/plat_gicv2_base.c 158 159FVP_DT_PREFIX := fvp-base-gicv2-psci 160else 161$(error "Incorrect GIC driver chosen on FVP port") 162endif 163 164ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 165FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 166else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 167FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 168 plat/arm/common/arm_ccn.c 169else 170$(error "Incorrect CCN driver chosen on FVP port") 171endif 172 173FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 174 plat/arm/board/fvp/fvp_security.c \ 175 plat/arm/common/arm_tzc400.c 176 177 178PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 179 -Iinclude/lib/psa 180 181 182PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 183 184FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 185 186ifeq (${ARCH}, aarch64) 187 188# select a different set of CPU files, depending on whether we compile for 189# hardware assisted coherency cores or not 190ifeq (${HW_ASSISTED_COHERENCY}, 0) 191# Cores used without DSU 192 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 193 lib/cpus/aarch64/cortex_a53.S \ 194 lib/cpus/aarch64/cortex_a57.S \ 195 lib/cpus/aarch64/cortex_a72.S \ 196 lib/cpus/aarch64/cortex_a73.S 197else 198# Cores used with DSU only 199 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 200 # AArch64-only cores 201 # TODO: add all cores to the appropriate lists 202 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 203 lib/cpus/aarch64/cortex_a65ae.S \ 204 lib/cpus/aarch64/cortex_a76.S \ 205 lib/cpus/aarch64/cortex_a76ae.S \ 206 lib/cpus/aarch64/cortex_a77.S \ 207 lib/cpus/aarch64/cortex_a78.S \ 208 lib/cpus/aarch64/cortex_a78_ae.S \ 209 lib/cpus/aarch64/cortex_a78c.S \ 210 lib/cpus/aarch64/cortex_a710.S \ 211 lib/cpus/aarch64/cortex_a715.S \ 212 lib/cpus/aarch64/cortex_a720.S \ 213 lib/cpus/aarch64/cortex_a720_ae.S \ 214 lib/cpus/aarch64/neoverse_n1.S \ 215 lib/cpus/aarch64/neoverse_n2.S \ 216 lib/cpus/aarch64/neoverse_v1.S \ 217 lib/cpus/aarch64/neoverse_e1.S \ 218 lib/cpus/aarch64/cortex_x2.S \ 219 lib/cpus/aarch64/cortex_x4.S 220 endif 221 # AArch64/AArch32 cores 222 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 223 lib/cpus/aarch64/cortex_a75.S 224endif 225 226#Include all CPUs to build to support all-errata build. 227ifeq (${ENABLE_ERRATA_ALL},1) 228 BUILD_CPUS_WITH_NO_FVP_MODEL = 1 229 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a320.S \ 230 lib/cpus/aarch64/cortex_a510.S \ 231 lib/cpus/aarch64/cortex_a520.S \ 232 lib/cpus/aarch64/cortex_a725.S \ 233 lib/cpus/aarch64/cortex_x1.S \ 234 lib/cpus/aarch64/cortex_x3.S \ 235 lib/cpus/aarch64/cortex_x925.S \ 236 lib/cpus/aarch64/neoverse_n3.S \ 237 lib/cpus/aarch64/neoverse_v2.S \ 238 lib/cpus/aarch64/neoverse_v3.S 239endif 240 241#Build AArch64-only CPUs with no FVP model yet. 242ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 243 # travis/gelas need these 244 FEAT_PABANDON := 1 245 ERRATA_SME_POWER_DOWN := 1 246 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_gelas.S \ 247 lib/cpus/aarch64/nevis.S \ 248 lib/cpus/aarch64/travis.S \ 249 lib/cpus/aarch64/cortex_alto.S 250endif 251 252else 253FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 254 lib/cpus/aarch32/cortex_a57.S \ 255 lib/cpus/aarch32/cortex_a53.S 256endif 257 258BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 259 drivers/arm/sp805/sp805.c \ 260 drivers/delay_timer/delay_timer.c \ 261 drivers/io/io_semihosting.c \ 262 lib/semihosting/semihosting.c \ 263 lib/semihosting/${ARCH}/semihosting_call.S \ 264 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 265 plat/arm/board/fvp/fvp_bl1_setup.c \ 266 plat/arm/board/fvp/fvp_cpu_pwr.c \ 267 plat/arm/board/fvp/fvp_err.c \ 268 plat/arm/board/fvp/fvp_io_storage.c \ 269 plat/arm/board/fvp/fvp_topology.c \ 270 ${FVP_CPU_LIBS} \ 271 ${FVP_INTERCONNECT_SOURCES} 272 273ifeq (${USE_SP804_TIMER},1) 274BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 275else 276BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 277endif 278 279 280BL2_SOURCES += drivers/arm/sp805/sp805.c \ 281 drivers/io/io_semihosting.c \ 282 lib/utils/mem_region.c \ 283 lib/semihosting/semihosting.c \ 284 lib/semihosting/${ARCH}/semihosting_call.S \ 285 plat/arm/board/fvp/fvp_bl2_setup.c \ 286 plat/arm/board/fvp/fvp_err.c \ 287 plat/arm/board/fvp/fvp_io_storage.c \ 288 plat/arm/common/arm_nor_psci_mem_protect.c \ 289 ${FVP_SECURITY_SOURCES} 290 291 292ifeq (${COT_DESC_IN_DTB},1) 293BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 294endif 295 296ifeq (${ENABLE_RME},1) 297BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 298 plat/arm/board/fvp/fvp_cpu_pwr.c 299 300BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 301 plat/arm/board/fvp/fvp_realm_attest_key.c \ 302 plat/arm/board/fvp/fvp_el3_token_sign.c \ 303 plat/arm/board/fvp/fvp_ide_keymgmt.c 304endif 305 306ifeq (${ENABLE_FEAT_RNG_TRAP},1) 307BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 308endif 309 310ifeq (${RESET_TO_BL2},1) 311BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 312 plat/arm/board/fvp/fvp_cpu_pwr.c \ 313 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 314 ${FVP_CPU_LIBS} \ 315 ${FVP_INTERCONNECT_SOURCES} 316endif 317 318ifeq (${USE_SP804_TIMER},1) 319BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 320endif 321 322BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 323 ${FVP_SECURITY_SOURCES} 324 325ifeq (${USE_SP804_TIMER},1) 326BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 327endif 328 329BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 330 drivers/arm/smmu/smmu_v3.c \ 331 drivers/delay_timer/delay_timer.c \ 332 drivers/cfi/v2m/v2m_flash.c \ 333 lib/utils/mem_region.c \ 334 plat/arm/board/fvp/fvp_bl31_setup.c \ 335 plat/arm/board/fvp/fvp_console.c \ 336 plat/arm/board/fvp/fvp_pm.c \ 337 plat/arm/board/fvp/fvp_topology.c \ 338 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 339 plat/arm/board/fvp/fvp_cpu_pwr.c \ 340 plat/arm/common/arm_nor_psci_mem_protect.c \ 341 ${FVP_CPU_LIBS} \ 342 ${FVP_GIC_SOURCES} \ 343 ${FVP_INTERCONNECT_SOURCES} \ 344 ${FVP_SECURITY_SOURCES} 345 346# Support for fconf in BL31 347# Added separately from the above list for better readability 348ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 349BL31_SOURCES += lib/fconf/fconf.c \ 350 lib/fconf/fconf_dyn_cfg_getter.c \ 351 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 352 353BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 354 355ifeq (${SEC_INT_DESC_IN_FCONF},1) 356BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 357endif 358 359endif 360 361ifeq (${USE_SP804_TIMER},1) 362BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 363else 364BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 365endif 366 367# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 368FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 369 370FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 371$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 372HW_CONFIG := ${FVP_HW_CONFIG} 373 374# Set default initrd base 128MiB offset of the default kernel address in FVP 375INITRD_BASE ?= 0x90000000 376 377# Kernel base address supports Linux kernels before v5.7 378# DTB base 1MiB before normal base kernel address in FVP (0x88000000) 379ifeq (${ARM_LINUX_KERNEL_AS_BL33},1) 380 PRELOADED_BL33_BASE ?= 0x80080000 381 ifeq (${RESET_TO_BL31},1) 382 ARM_PRELOADED_DTB_BASE ?= 0x87F00000 383 endif 384endif 385 386ifeq (${TRANSFER_LIST}, 0) 387FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 388 ${PLAT}_fw_config.dts \ 389 ${PLAT}_tb_fw_config.dts \ 390 ${PLAT}_soc_fw_config.dts \ 391 ${PLAT}_nt_fw_config.dts \ 392 ) 393 394FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 395FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 396FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 397FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 398 399ifeq (${SPD},tspd) 400FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 401FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 402 403# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 404$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 405endif 406 407ifeq (${SPD},spmd) 408 409ifeq ($(ARM_SPMC_MANIFEST_DTS),) 410ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 411endif 412 413FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 414FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 415 416# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 417$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 418endif 419 420# Add the FW_CONFIG to FIP and specify the same to certtool 421$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 422# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 423$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 424# Add the NT_FW_CONFIG to FIP and specify the same to certtool 425$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 426# Add the TB_FW_CONFIG to FIP and specify the same to certtool 427$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 428endif 429 430# Add the HW_CONFIG to FIP and specify the same to certtool 431$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 432 433ifeq (${TRANSFER_LIST}, 1) 434 435ifeq ($(RESET_TO_BL31), 1) 436FW_HANDOFF_SIZE := 20000 437 438TRANSFER_LIST_DTB_OFFSET := 0x20 439$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 440endif 441endif 442 443ifeq (${HOB_LIST}, 1) 444include lib/hob/hob.mk 445endif 446 447# Enable dynamic mitigation support by default 448DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 449 450ifneq (${ENABLE_FEAT_AMU},0) 451BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 452 lib/cpus/aarch64/cpuamu_helpers.S 453 454ifeq (${HW_ASSISTED_COHERENCY}, 1) 455BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 456 lib/cpus/aarch64/neoverse_n1_pubsub.c 457endif 458endif 459 460ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 461 ifeq (${ENABLE_FEAT_RAS},1) 462 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 463 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 464 else 465 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 466 endif 467 else 468 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 469 endif 470endif 471 472ifneq (${ENABLE_STACK_PROTECTOR},0) 473PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 474endif 475 476# Enable the dynamic translation tables library. 477ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 478 ifeq (${ARCH},aarch32) 479 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 480 else # AArch64 481 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 482 endif 483endif 484 485ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 486 ifeq (${ARCH},aarch32) 487 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 488 else # AArch64 489 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 490 ifeq (${SPD},tspd) 491 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 492 endif 493 endif 494endif 495 496ifeq (${USE_DEBUGFS},1) 497 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 498endif 499 500# Add support for platform supplied linker script for BL31 build 501$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 502 503ifneq (${RESET_TO_BL2}, 0) 504 override BL1_SOURCES = 505endif 506 507include plat/arm/board/common/board_common.mk 508include plat/arm/common/arm_common.mk 509 510ifeq (${MEASURED_BOOT},1) 511BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 512 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 513 lib/psa/measured_boot.c 514 515BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 516 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 517 lib/psa/measured_boot.c 518endif 519 520ifeq (${DRTM_SUPPORT}, 1) 521BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 522 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 523 plat/arm/board/fvp/fvp_drtm_err.c \ 524 plat/arm/board/fvp/fvp_drtm_measurement.c \ 525 plat/arm/board/fvp/fvp_drtm_stub.c \ 526 plat/arm/common/arm_dyn_cfg.c \ 527 plat/arm/board/fvp/fvp_err.c 528endif 529 530ifeq (${TRUSTED_BOARD_BOOT}, 1) 531BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 532BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 533 534# FVP being a development platform, enable capability to disable Authentication 535# dynamically if TRUSTED_BOARD_BOOT is set. 536DYN_DISABLE_AUTH := 1 537endif 538 539ifeq (${SPMC_AT_EL3}, 1) 540PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 541endif 542 543PSCI_OS_INIT_MODE := 1 544 545ifeq (${SPD},spmd) 546BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 547endif 548 549# Test specific macros, keep them at bottom of this file 550$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 551ifeq (${PLATFORM_TEST_EA_FFH}, 1) 552 ifeq (${FFH_SUPPORT}, 0) 553 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 554 endif 555 556endif 557 558$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 559ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 560 ifeq (${ENABLE_FEAT_RAS}, 0) 561 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 562 endif 563 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 564 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 565 endif 566endif 567 568$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 569ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 570 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 571 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 572 endif 573 ifeq (${ENABLE_SPMD_LP}, 0) 574 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 575 endif 576 ifeq (${ENABLE_FEAT_RAS}, 0) 577 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 578 endif 579 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 580 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 581 endif 582endif 583 584ifeq (${ERRATA_ABI_SUPPORT}, 1) 585include plat/arm/board/fvp/fvp_cpu_errata.mk 586endif 587 588# Build macro necessary for running SPM tests on FVP platform 589$(eval $(call add_define,PLAT_TEST_SPM)) 590