imx: imx_clock: mmc: Add USDHC clock API

This patch adds an API to configure up the base USDHC clocks, taking a
bit-mask of silicon specific bits as an input from a higher layer in order
to direct t

imx: imx_clock: mmc: Add USDHC clock API

This patch adds an API to configure up the base USDHC clocks, taking a
bit-mask of silicon specific bits as an input from a higher layer in order
to direct the necessary clock source.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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imx: imx_clock: uart: Add UART clock API

This patch adds an API to configure up the base UART clocks, taking a
bit-mask of silicon specific bits as an input from a higher layer in order
to direct th

imx: imx_clock: uart: Add UART clock API

This patch adds an API to configure up the base UART clocks, taking a
bit-mask of silicon specific bits as an input from a higher layer in order
to direct the necessary clock source.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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imx: imx_clock: Add driver and associated clock register definitions

This commit:

- Defines a clock stub with a conjoined header defining the clock
memory map.

- Defines the CCM Clock Gating Reg

imx: imx_clock: Add driver and associated clock register definitions

This commit:

- Defines a clock stub with a conjoined header defining the clock
memory map.

- Defines the CCM Clock Gating Register which comes in a quadrumvirate
register set to read, set, clear and toggle individual clock gates into
one of four states based bitmask.

00: Domain clocks not needed
01: Domain clocks needed when in RUN
10: Domain clocks needed when in RUN and WAIT
11: Domain clocks needed all the time

- Defines clock control register bits

There are various quadrumvirate register blocks target-root, misc-root,
post-root, pre-root in the CCM.

The number of registers is huge but the four registers in each
quadrumvirate block contain the same bits, so the number of bit
definitions is actually quite low.

- Defines clock identifiers

An array of clock gates is provided in the CCM block. In order to index
that array and thus enable/disable clock gates for the right components,
we need to provide meaningful names to the indices.

Section 5.2.5 of the i.MX7 Solo Application Processor Reference Manual
Rev 0.1 provides the relevant details.

- Defines target mux select bits
This is a comprehensive definition of the target clock mux select bits.
These bits are required to correctly select the clock source. Defining
all of the bits up-front even for unused blocks in ATF means we can
switch on any block we want at a later date without having to write new
code in the clock-mux layer.

- Defines identifier indices into root-slice array
The root-slice array of control registers has a specific set of indices,
which differ from the clock-gate indices.

- Provides a clock gate enable/disable routine
Provides a clock-gate enable/disable routine via the set/clr
registers in a given clock-gate control register block.

This index passed should be one of the enums associated with CCM and
depending on enable/disable being passed either set or clr will be
written to.

The Domain0 bits are currently the only bits targeted by this write, more
work may need to be done on the domain bits in subsequent patches as a
result.

- imx: Adds set/clr routines to clock layer

Adds a set and clr routine to the clock layer. These routines allow us to
access the set and clear registers of the "target" block registers. These
are the registers where we select the clock source from the available list.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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imx7: imx_regs: Add a shared imx-regs.h for i.MX7 ATF platforms

In order to have some common code shared between similar SOCs its pretty
common to have IP blocks reused. In reusing those blocks we f

imx7: imx_regs: Add a shared imx-regs.h for i.MX7 ATF platforms

In order to have some common code shared between similar SOCs its pretty
common to have IP blocks reused. In reusing those blocks we frequently need
to map compatible blocks to different addresses depending on the SOC.

This patch adds a basic memory map of the i.MX7 based on the "Cortex-A7
Memory Map" section 2.12 of "i.MX7Solo Applications Processor Reference
Manual, Rev 0.1 08/2016"

In memory map terms the i.MX7S and i.MX7D are identical with the D
variant containing two Cortex-A7 cores plus a Cortex-M core and the S
variant containing one Cortex-A7 and one Cortex-M.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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zynqmp: Add ATF support for Data blob encryption and decryption

This patch adds ATF support for AES data blob encrypt/decrypt.
ATF establishes a path to send the address of the structure
to the xils

zynqmp: Add ATF support for Data blob encryption and decryption

This patch adds ATF support for AES data blob encrypt/decrypt.
ATF establishes a path to send the address of the structure
to the xilsecure, so that it will pick addresses of the data
and performs the requested operation (encrypt/decrypt) and puts
the result in load address.

where structure contains
- Data blob src address
- load address
- IV address
- Key address - this will actual key addr in case of KUP
else it will be zero.
- Data-size
- Aes-op type
- KeySrc

Signed-off-by: Kalyani Akula <kalyani.akula@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

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zynqmp: Remove emulation platform support

This patch removes support for emulation platforms
EP108 and Veloce.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

zynqmp: pm: Correct function header of clock APIs

Correct function header of pm_api_clock_getparent() and
pm_api_clock_setparent().

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Acked-by: Will

zynqmp: pm: Correct function header of clock APIs

Correct function header of pm_api_clock_getparent() and
pm_api_clock_setparent().

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Acked-by: Will Wong <WILLW@xilinx.com>

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zynqmp: pm_service: Ignore enable/disable of PLL type clocks

PLL type clock is enabled by FSBL on boot-up. PMUFW enable/disable
them based on their user count. So, it should not be handled from ATF.

zynqmp: pm_service: Ignore enable/disable of PLL type clocks

PLL type clock is enabled by FSBL on boot-up. PMUFW enable/disable
them based on their user count. So, it should not be handled from ATF.

Put PLL type clock into bypass and reset mode only while changing
PLL rate (FBDIV).

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

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zynqmp: Add new API for pl configuration readback

This patch adds new API's for performing pl configuration
readback.

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signe

zynqmp: Add new API for pl configuration readback

This patch adds new API's for performing pl configuration
readback.

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

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zynqmp: pm: Use critical flag instead of initenable

CCF has already provision to enable clock during registration
through CLK_IS_CRITICAL flag. Use CLK_IS_CRITICAL instead of
init_enable attribute.

zynqmp: pm: Use critical flag instead of initenable

CCF has already provision to enable clock during registration
through CLK_IS_CRITICAL flag. Use CLK_IS_CRITICAL instead of
init_enable attribute.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Jolly Shah <jolly.shah@xilinx.com>

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zynqmp: pm: Correct WDT clock database

WDT used by APU is FPD_WDT. FPD WDT clock is controlled by
FPD_SLCR.WDT_CLK_SEL register. Correct the same in WDT clock
database.

As per FPD_SLCR.WDT_CLK_SEL

zynqmp: pm: Correct WDT clock database

WDT used by APU is FPD_WDT. FPD WDT clock is controlled by
FPD_SLCR.WDT_CLK_SEL register. Correct the same in WDT clock
database.

As per FPD_SLCR.WDT_CLK_SEL register, there can be only two
parents of WDT clock not three. Fix the same by correcting it's
parents in clock database.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Jolly Shah <jolly.shah@xilinx.com>

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zynqmp: pm_service: Add support for writing to AFI registers

Add support for writing to AFI registers.
So that after writing a bitstream the interface can be programmed.

Signed-off-by: Shubhrajyoti

zynqmp: pm_service: Add support for writing to AFI registers

Add support for writing to AFI registers.
So that after writing a bitstream the interface can be programmed.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

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zynqmp: pm: Add IOCTL to set boot health status

Since the MMIO read/write APIs are removed from Linux user space,
Linux cannot directly write to the Global General Storage Register 4
any more to set

zynqmp: pm: Add IOCTL to set boot health status

Since the MMIO read/write APIs are removed from Linux user space,
Linux cannot directly write to the Global General Storage Register 4
any more to set healthy boot status.

Create an IOCTL to allow Linux to set boot health status.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Will Wong <willw@xilinx.com>

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zynqmp: pm_service: Add support for resetting ULPI transceiver

To make ULPI transceiver work, a HIGH - LOW - HIGH pulse needs
to be given to resetb pin of ULPI chip. In ZYNQMP, this resetb
pin is be

zynqmp: pm_service: Add support for resetting ULPI transceiver

To make ULPI transceiver work, a HIGH - LOW - HIGH pulse needs
to be given to resetb pin of ULPI chip. In ZYNQMP, this resetb
pin is being driven by BOOT MODE PIN 1. The BOOT MODE PIN's
are controlled by BOOT_PIN_CTRL register present in CRL_APB
address region. Since CRL_APB can be resticted to secure access,
this pin should be controlled by ATF.

This patch adds the support for the same.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

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Support shared Mbed TLS heap for SGM

Change-Id: Ibbfedb6601feff51dfb82c1d94850716c5a36d24
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Support shared Mbed TLS heap for SGI

Change-Id: Iac454c745543842bfeed004aee7a3f4fb94d37e1
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Support shared Mbed TLS heap for FVP

This patch introduces the shared Mbed TLS heap optimisation for Arm
platforms. The objective is the Mbed TLS heap to be shared between BL1
and BL2 so as to not a

Support shared Mbed TLS heap for FVP

This patch introduces the shared Mbed TLS heap optimisation for Arm
platforms. The objective is the Mbed TLS heap to be shared between BL1
and BL2 so as to not allocate the heap memory twice. To achieve that,
the patch introduces all the necessary helpers for implementing this
optimisation. It also applies it for FVP.

Change-Id: I6d85eaa1361517b7490956b2ac50f5fa0d0bb008
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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Prepare Mbed TLS drivers for shared heap

The Mbed TLS drivers, in order to work, need a heap for internal usage.
This heap, instead of being directly referenced by the drivers, now it
is being acces

Prepare Mbed TLS drivers for shared heap

The Mbed TLS drivers, in order to work, need a heap for internal usage.
This heap, instead of being directly referenced by the drivers, now it
is being accessed indirectly through a pointer. Also, the heap, instead
of being part of the drivers, now it is being received through the
plat_get_mbedtls_heap() function. This function requests a heap from the
current BL image which utilises the Mbed TLS drivers.

Those changes create the opportunity for the Mbed TLS heap to be shared
among different images, thus saving memory. A default heap
implementation is provided but it can be overridden by a platform
specific, optimised implemenetation.

Change-Id: I286a1f10097a9cdcbcd312201eea576c18d157fa
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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Merge pull request #1540 from MISL-EBU-System-SW/marvell-updates-18.09

Marvell updates 18.09

plat: marvell: Update Marvell base code version to 18.09.1

Change-Id: I908844364bf8080612aaa6d750d7d2441ecc2eb8
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

plat: svc: ap807: add SVC configuration for AP807

- add svc configuration according to values burnt
to the chip efuse

Change-Id: Icf5d7cc41bc09ac2244d0a126106e681afebb064
Signed-off-by: Christine

plat: svc: ap807: add SVC configuration for AP807

- add svc configuration according to values burnt
to the chip efuse

Change-Id: Icf5d7cc41bc09ac2244d0a126106e681afebb064
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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fix: marvell: Check the required libraries before building doimage

Some customers are missing host libraries required for doimage
builds.
This patch requests for the library installation check for e

fix: marvell: Check the required libraries before building doimage

Some customers are missing host libraries required for doimage
builds.
This patch requests for the library installation check for every
doimage build and suggest the required installation steps in case
of missing headers.

Change-Id: Icde18c3d4d6045f65e50d2dc9e6514971f40033e
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>

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plat: a8k: enable PMU overflow interrupt handler

This patch enables handling PMU overflow IRQ by GIC SPI's
directly in EL3. Also implement additional SMC routine,
which can disable the solution on d

plat: a8k: enable PMU overflow interrupt handler

This patch enables handling PMU overflow IRQ by GIC SPI's
directly in EL3. Also implement additional SMC routine,
which can disable the solution on demand in runtime.

Since it is possible to configure PMU interrupt trigger type
in the MADT ACPI table, it is enough to set it only once in EL3
during initialization.

Change-Id: Ie76aa62ccc4fd7cabfec9e3d5ed9970ada1c1b2a
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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Merge pull request #1541 from rajanv-xilinx/integration-num-clocks

zynqmp: pm: Add API to get number of clocks

marvell: pm: do not panic by default in cpu_standby

Current default behavior of cpu_standby callback
is problematic during the SBSA test, which is
unable to run due to EL3 panic. Make it dependent o

marvell: pm: do not panic by default in cpu_standby

Current default behavior of cpu_standby callback
is problematic during the SBSA test, which is
unable to run due to EL3 panic. Make it dependent on
the PM firmware running.

Change-Id: I7a53de8c880bd23b157dd65ce14bb48b5a5c76c8
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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