1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PSCI_H 8 #define PSCI_H 9 10 #include <bakery_lock.h> 11 #include <bl_common.h> 12 #include <platform_def.h> /* for PLAT_NUM_PWR_DOMAINS */ 13 #include <psci_lib.h> /* To maintain compatibility for SPDs */ 14 #include <utils_def.h> 15 16 /******************************************************************************* 17 * Number of power domains whose state this PSCI implementation can track 18 ******************************************************************************/ 19 #ifdef PLAT_NUM_PWR_DOMAINS 20 #define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS 21 #else 22 #define PSCI_NUM_PWR_DOMAINS (2 * PLATFORM_CORE_COUNT) 23 #endif 24 25 #define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \ 26 PLATFORM_CORE_COUNT) 27 28 /* This is the power level corresponding to a CPU */ 29 #define PSCI_CPU_PWR_LVL U(0) 30 31 /* 32 * The maximum power level supported by PSCI. Since PSCI CPU_SUSPEND 33 * uses the old power_state parameter format which has 2 bits to specify the 34 * power level, this constant is defined to be 3. 35 */ 36 #define PSCI_MAX_PWR_LVL U(3) 37 38 /******************************************************************************* 39 * Defines for runtime services function ids 40 ******************************************************************************/ 41 #define PSCI_VERSION U(0x84000000) 42 #define PSCI_CPU_SUSPEND_AARCH32 U(0x84000001) 43 #define PSCI_CPU_SUSPEND_AARCH64 U(0xc4000001) 44 #define PSCI_CPU_OFF U(0x84000002) 45 #define PSCI_CPU_ON_AARCH32 U(0x84000003) 46 #define PSCI_CPU_ON_AARCH64 U(0xc4000003) 47 #define PSCI_AFFINITY_INFO_AARCH32 U(0x84000004) 48 #define PSCI_AFFINITY_INFO_AARCH64 U(0xc4000004) 49 #define PSCI_MIG_AARCH32 U(0x84000005) 50 #define PSCI_MIG_AARCH64 U(0xc4000005) 51 #define PSCI_MIG_INFO_TYPE U(0x84000006) 52 #define PSCI_MIG_INFO_UP_CPU_AARCH32 U(0x84000007) 53 #define PSCI_MIG_INFO_UP_CPU_AARCH64 U(0xc4000007) 54 #define PSCI_SYSTEM_OFF U(0x84000008) 55 #define PSCI_SYSTEM_RESET U(0x84000009) 56 #define PSCI_FEATURES U(0x8400000A) 57 #define PSCI_NODE_HW_STATE_AARCH32 U(0x8400000d) 58 #define PSCI_NODE_HW_STATE_AARCH64 U(0xc400000d) 59 #define PSCI_SYSTEM_SUSPEND_AARCH32 U(0x8400000E) 60 #define PSCI_SYSTEM_SUSPEND_AARCH64 U(0xc400000E) 61 #define PSCI_STAT_RESIDENCY_AARCH32 U(0x84000010) 62 #define PSCI_STAT_RESIDENCY_AARCH64 U(0xc4000010) 63 #define PSCI_STAT_COUNT_AARCH32 U(0x84000011) 64 #define PSCI_STAT_COUNT_AARCH64 U(0xc4000011) 65 #define PSCI_SYSTEM_RESET2_AARCH32 U(0x84000012) 66 #define PSCI_SYSTEM_RESET2_AARCH64 U(0xc4000012) 67 #define PSCI_MEM_PROTECT U(0x84000013) 68 #define PSCI_MEM_CHK_RANGE_AARCH32 U(0x84000014) 69 #define PSCI_MEM_CHK_RANGE_AARCH64 U(0xc4000014) 70 71 /* 72 * Number of PSCI calls (above) implemented 73 */ 74 #if ENABLE_PSCI_STAT 75 #define PSCI_NUM_CALLS U(22) 76 #else 77 #define PSCI_NUM_CALLS U(18) 78 #endif 79 80 /* The macros below are used to identify PSCI calls from the SMC function ID */ 81 #define PSCI_FID_MASK U(0xffe0) 82 #define PSCI_FID_VALUE U(0) 83 #define is_psci_fid(_fid) \ 84 (((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE) 85 86 /******************************************************************************* 87 * PSCI Migrate and friends 88 ******************************************************************************/ 89 #define PSCI_TOS_UP_MIG_CAP 0 90 #define PSCI_TOS_NOT_UP_MIG_CAP 1 91 #define PSCI_TOS_NOT_PRESENT_MP 2 92 93 /******************************************************************************* 94 * PSCI CPU_SUSPEND 'power_state' parameter specific defines 95 ******************************************************************************/ 96 #define PSTATE_ID_SHIFT U(0) 97 98 #if PSCI_EXTENDED_STATE_ID 99 #define PSTATE_VALID_MASK U(0xB0000000) 100 #define PSTATE_TYPE_SHIFT U(30) 101 #define PSTATE_ID_MASK U(0xfffffff) 102 #else 103 #define PSTATE_VALID_MASK U(0xFCFE0000) 104 #define PSTATE_TYPE_SHIFT U(16) 105 #define PSTATE_PWR_LVL_SHIFT U(24) 106 #define PSTATE_ID_MASK U(0xffff) 107 #define PSTATE_PWR_LVL_MASK U(0x3) 108 109 #define psci_get_pstate_pwrlvl(pstate) (((pstate) >> PSTATE_PWR_LVL_SHIFT) & \ 110 PSTATE_PWR_LVL_MASK) 111 #define psci_make_powerstate(state_id, type, pwrlvl) \ 112 (((state_id) & PSTATE_ID_MASK) << PSTATE_ID_SHIFT) |\ 113 (((type) & PSTATE_TYPE_MASK) << PSTATE_TYPE_SHIFT) |\ 114 (((pwrlvl) & PSTATE_PWR_LVL_MASK) << PSTATE_PWR_LVL_SHIFT) 115 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 116 117 #define PSTATE_TYPE_STANDBY U(0x0) 118 #define PSTATE_TYPE_POWERDOWN U(0x1) 119 #define PSTATE_TYPE_MASK U(0x1) 120 121 /******************************************************************************* 122 * PSCI CPU_FEATURES feature flag specific defines 123 ******************************************************************************/ 124 /* Features flags for CPU SUSPEND power state parameter format. Bits [1:1] */ 125 #define FF_PSTATE_SHIFT U(1) 126 #define FF_PSTATE_ORIG U(0) 127 #define FF_PSTATE_EXTENDED U(1) 128 #if PSCI_EXTENDED_STATE_ID 129 #define FF_PSTATE FF_PSTATE_EXTENDED 130 #else 131 #define FF_PSTATE FF_PSTATE_ORIG 132 #endif 133 134 /* Features flags for CPU SUSPEND OS Initiated mode support. Bits [0:0] */ 135 #define FF_MODE_SUPPORT_SHIFT U(0) 136 #define FF_SUPPORTS_OS_INIT_MODE U(1) 137 138 /******************************************************************************* 139 * PSCI version 140 ******************************************************************************/ 141 #define PSCI_MAJOR_VER (U(1) << 16) 142 #define PSCI_MINOR_VER U(0x1) 143 144 /******************************************************************************* 145 * PSCI error codes 146 ******************************************************************************/ 147 #define PSCI_E_SUCCESS 0 148 #define PSCI_E_NOT_SUPPORTED -1 149 #define PSCI_E_INVALID_PARAMS -2 150 #define PSCI_E_DENIED -3 151 #define PSCI_E_ALREADY_ON -4 152 #define PSCI_E_ON_PENDING -5 153 #define PSCI_E_INTERN_FAIL -6 154 #define PSCI_E_NOT_PRESENT -7 155 #define PSCI_E_DISABLED -8 156 #define PSCI_E_INVALID_ADDRESS -9 157 158 #define PSCI_INVALID_MPIDR ~((u_register_t)0) 159 160 /* 161 * SYSTEM_RESET2 macros 162 */ 163 #define PSCI_RESET2_TYPE_VENDOR_SHIFT U(31) 164 #define PSCI_RESET2_TYPE_VENDOR (U(1) << PSCI_RESET2_TYPE_VENDOR_SHIFT) 165 #define PSCI_RESET2_TYPE_ARCH (U(0) << PSCI_RESET2_TYPE_VENDOR_SHIFT) 166 #define PSCI_RESET2_SYSTEM_WARM_RESET (PSCI_RESET2_TYPE_ARCH | U(0)) 167 168 #ifndef __ASSEMBLY__ 169 170 #include <stdint.h> 171 172 /* Function to help build the psci capabilities bitfield */ 173 174 static inline unsigned int define_psci_cap(unsigned int x) 175 { 176 return U(1) << (x & U(0x1f)); 177 } 178 179 180 /* Power state helper functions */ 181 182 static inline unsigned int psci_get_pstate_id(unsigned int power_state) 183 { 184 return ((power_state) >> PSTATE_ID_SHIFT) & PSTATE_ID_MASK; 185 } 186 187 static inline unsigned int psci_get_pstate_type(unsigned int power_state) 188 { 189 return ((power_state) >> PSTATE_TYPE_SHIFT) & PSTATE_TYPE_MASK; 190 } 191 192 static inline unsigned int psci_check_power_state(unsigned int power_state) 193 { 194 return ((power_state) & PSTATE_VALID_MASK); 195 } 196 197 /* 198 * These are the states reported by the PSCI_AFFINITY_INFO API for the specified 199 * CPU. The definitions of these states can be found in Section 5.7.1 in the 200 * PSCI specification (ARM DEN 0022C). 201 */ 202 typedef enum { 203 AFF_STATE_ON = U(0), 204 AFF_STATE_OFF = U(1), 205 AFF_STATE_ON_PENDING = U(2) 206 } aff_info_state_t; 207 208 /* 209 * These are the power states reported by PSCI_NODE_HW_STATE API for the 210 * specified CPU. The definitions of these states can be found in Section 5.15.3 211 * of PSCI specification (ARM DEN 0022C). 212 */ 213 #define HW_ON 0 214 #define HW_OFF 1 215 #define HW_STANDBY 2 216 217 /* 218 * Macro to represent invalid affinity level within PSCI. 219 */ 220 #define PSCI_INVALID_PWR_LVL (PLAT_MAX_PWR_LVL + U(1)) 221 222 /* 223 * Type for representing the local power state at a particular level. 224 */ 225 typedef uint8_t plat_local_state_t; 226 227 /* The local state macro used to represent RUN state. */ 228 #define PSCI_LOCAL_STATE_RUN U(0) 229 230 /* 231 * Function to test whether the plat_local_state is RUN state 232 */ 233 static inline int is_local_state_run(unsigned int plat_local_state) 234 { 235 return (plat_local_state == PSCI_LOCAL_STATE_RUN) ? 1 : 0; 236 } 237 238 /* 239 * Function to test whether the plat_local_state is RETENTION state 240 */ 241 static inline int is_local_state_retn(unsigned int plat_local_state) 242 { 243 return ((plat_local_state > PSCI_LOCAL_STATE_RUN) && 244 (plat_local_state <= PLAT_MAX_RET_STATE)) ? 1 : 0; 245 } 246 247 /* 248 * Function to test whether the plat_local_state is OFF state 249 */ 250 static inline int is_local_state_off(unsigned int plat_local_state) 251 { 252 return ((plat_local_state > PLAT_MAX_RET_STATE) && 253 (plat_local_state <= PLAT_MAX_OFF_STATE)) ? 1 : 0; 254 } 255 256 /***************************************************************************** 257 * This data structure defines the representation of the power state parameter 258 * for its exchange between the generic PSCI code and the platform port. For 259 * example, it is used by the platform port to specify the requested power 260 * states during a power management operation. It is used by the generic code to 261 * inform the platform about the target power states that each level should 262 * enter. 263 ****************************************************************************/ 264 typedef struct psci_power_state { 265 /* 266 * The pwr_domain_state[] stores the local power state at each level 267 * for the CPU. 268 */ 269 plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + U(1)]; 270 } psci_power_state_t; 271 272 /******************************************************************************* 273 * Structure used to store per-cpu information relevant to the PSCI service. 274 * It is populated in the per-cpu data array. In return we get a guarantee that 275 * this information will not reside on a cache line shared with another cpu. 276 ******************************************************************************/ 277 typedef struct psci_cpu_data { 278 /* State as seen by PSCI Affinity Info API */ 279 aff_info_state_t aff_info_state; 280 281 /* 282 * Highest power level which takes part in a power management 283 * operation. 284 */ 285 unsigned int target_pwrlvl; 286 287 /* The local power state of this CPU */ 288 plat_local_state_t local_state; 289 } psci_cpu_data_t; 290 291 /******************************************************************************* 292 * Structure populated by platform specific code to export routines which 293 * perform common low level power management functions 294 ******************************************************************************/ 295 typedef struct plat_psci_ops { 296 void (*cpu_standby)(plat_local_state_t cpu_state); 297 int (*pwr_domain_on)(u_register_t mpidr); 298 void (*pwr_domain_off)(const psci_power_state_t *target_state); 299 void (*pwr_domain_suspend_pwrdown_early)( 300 const psci_power_state_t *target_state); 301 void (*pwr_domain_suspend)(const psci_power_state_t *target_state); 302 void (*pwr_domain_on_finish)(const psci_power_state_t *target_state); 303 void (*pwr_domain_suspend_finish)( 304 const psci_power_state_t *target_state); 305 void (*pwr_domain_pwr_down_wfi)( 306 const psci_power_state_t *target_state) __dead2; 307 void (*system_off)(void) __dead2; 308 void (*system_reset)(void) __dead2; 309 int (*validate_power_state)(unsigned int power_state, 310 psci_power_state_t *req_state); 311 int (*validate_ns_entrypoint)(uintptr_t ns_entrypoint); 312 void (*get_sys_suspend_power_state)( 313 psci_power_state_t *req_state); 314 int (*get_pwr_lvl_state_idx)(plat_local_state_t pwr_domain_state, 315 int pwrlvl); 316 int (*translate_power_state_by_mpidr)(u_register_t mpidr, 317 unsigned int power_state, 318 psci_power_state_t *output_state); 319 int (*get_node_hw_state)(u_register_t mpidr, unsigned int power_level); 320 int (*mem_protect_chk)(uintptr_t base, u_register_t length); 321 int (*read_mem_protect)(int *val); 322 int (*write_mem_protect)(int val); 323 int (*system_reset2)(int is_vendor, 324 int reset_type, u_register_t cookie); 325 } plat_psci_ops_t; 326 327 /******************************************************************************* 328 * Function & Data prototypes 329 ******************************************************************************/ 330 unsigned int psci_version(void); 331 int psci_cpu_on(u_register_t target_cpu, 332 uintptr_t entrypoint, 333 u_register_t context_id); 334 int psci_cpu_suspend(unsigned int power_state, 335 uintptr_t entrypoint, 336 u_register_t context_id); 337 int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id); 338 int psci_cpu_off(void); 339 int psci_affinity_info(u_register_t target_affinity, 340 unsigned int lowest_affinity_level); 341 int psci_migrate(u_register_t target_cpu); 342 int psci_migrate_info_type(void); 343 u_register_t psci_migrate_info_up_cpu(void); 344 int psci_node_hw_state(u_register_t target_cpu, 345 unsigned int power_level); 346 int psci_features(unsigned int psci_fid); 347 void __dead2 psci_power_down_wfi(void); 348 void psci_arch_setup(void); 349 350 /* 351 * The below API is deprecated. This is now replaced by bl31_warmboot_entry in 352 * AArch64. 353 */ 354 void psci_entrypoint(void) __deprecated; 355 356 #endif /*__ASSEMBLY__*/ 357 358 #endif /* PSCI_H */ 359