1/* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <console.h> 10#include <platform_def.h> 11 12 .weak plat_report_exception 13 .weak plat_crash_console_init 14 .weak plat_crash_console_putc 15 .weak plat_crash_console_flush 16 .weak plat_reset_handler 17 .weak plat_disable_acp 18 .weak bl1_plat_prepare_exit 19 .weak plat_panic_handler 20 .weak bl31_plat_enable_mmu 21 .weak bl32_plat_enable_mmu 22 23 .weak plat_handle_uncontainable_ea 24 .weak plat_handle_double_fault 25 .weak plat_handle_el3_ea 26 27 .globl platform_get_core_pos 28 29#define MPIDR_RES_BIT_MASK 0xff000000 30 31 /* ------------------------------------------------------------------ 32 * int platform_get_core_pos(int mpidr) 33 * Returns the CPU index of the CPU specified by mpidr. This is 34 * defined when platform compatibility is disabled to enable Trusted 35 * Firmware components like SPD using the old platform API to work. 36 * This API is deprecated and it assumes that the mpidr specified is 37 * that of a valid and present CPU. Instead, plat_my_core_pos() 38 * should be used for CPU index of the current CPU and 39 * plat_core_pos_by_mpidr() should be used for CPU index of a 40 * CPU specified by its mpidr. 41 * ------------------------------------------------------------------ 42 */ 43func_deprecated platform_get_core_pos 44 bic x0, x0, #MPIDR_RES_BIT_MASK 45 mrs x1, mpidr_el1 46 bic x1, x1, #MPIDR_RES_BIT_MASK 47 cmp x0, x1 48 beq plat_my_core_pos 49 b platform_core_pos_helper 50endfunc_deprecated platform_get_core_pos 51 52 /* ----------------------------------------------------- 53 * Placeholder function which should be redefined by 54 * each platform. 55 * ----------------------------------------------------- 56 */ 57func plat_report_exception 58 ret 59endfunc plat_report_exception 60 61#if MULTI_CONSOLE_API 62 /* ----------------------------------------------------- 63 * int plat_crash_console_init(void) 64 * Use normal console by default. Switch it to crash 65 * mode so serial consoles become active again. 66 * NOTE: This default implementation will only work for 67 * crashes that occur after a normal console (marked 68 * valid for the crash state) has been registered with 69 * the console framework. To debug crashes that occur 70 * earlier, the platform has to override these functions 71 * with an implementation that initializes a console 72 * driver with hardcoded parameters. See 73 * docs/porting-guide.rst for more information. 74 * ----------------------------------------------------- 75 */ 76func plat_crash_console_init 77#if defined(IMAGE_BL1) 78 /* 79 * BL1 code can possibly crash so early that the data segment is not yet 80 * accessible. Don't risk undefined behavior by trying to run the normal 81 * console framework. Platforms that want to debug BL1 will need to 82 * override this with custom functions that can run from registers only. 83 */ 84 mov x0, #0 85 ret 86#else /* IMAGE_BL1 */ 87 mov x3, x30 88 mov x0, #CONSOLE_FLAG_CRASH 89 bl console_switch_state 90 mov x0, #1 91 ret x3 92#endif 93endfunc plat_crash_console_init 94 95 /* ----------------------------------------------------- 96 * void plat_crash_console_putc(int character) 97 * Output through the normal console by default. 98 * ----------------------------------------------------- 99 */ 100func plat_crash_console_putc 101 b console_putc 102endfunc plat_crash_console_putc 103 104 /* ----------------------------------------------------- 105 * void plat_crash_console_flush(void) 106 * Flush normal console by default. 107 * ----------------------------------------------------- 108 */ 109func plat_crash_console_flush 110 b console_flush 111endfunc plat_crash_console_flush 112 113#else /* MULTI_CONSOLE_API */ 114 115 /* ----------------------------------------------------- 116 * In the old API these are all no-op stubs that need to 117 * be overridden by the platform to be useful. 118 * ----------------------------------------------------- 119 */ 120func plat_crash_console_init 121 mov x0, #0 122 ret 123endfunc plat_crash_console_init 124 125func plat_crash_console_putc 126 ret 127endfunc plat_crash_console_putc 128 129func plat_crash_console_flush 130 ret 131endfunc plat_crash_console_flush 132#endif 133 134 /* ----------------------------------------------------- 135 * Placeholder function which should be redefined by 136 * each platform. This function should preserve x19 - x29. 137 * ----------------------------------------------------- 138 */ 139func plat_reset_handler 140 ret 141endfunc plat_reset_handler 142 143 /* ----------------------------------------------------- 144 * Placeholder function which should be redefined by 145 * each platform. This function is allowed to use 146 * registers x0 - x17. 147 * ----------------------------------------------------- 148 */ 149func plat_disable_acp 150 ret 151endfunc plat_disable_acp 152 153 /* ----------------------------------------------------- 154 * void bl1_plat_prepare_exit(entry_point_info_t *ep_info); 155 * Called before exiting BL1. Default: do nothing 156 * ----------------------------------------------------- 157 */ 158func bl1_plat_prepare_exit 159 ret 160endfunc bl1_plat_prepare_exit 161 162 /* ----------------------------------------------------- 163 * void plat_panic_handler(void) __dead2; 164 * Endless loop by default. 165 * ----------------------------------------------------- 166 */ 167func plat_panic_handler 168 wfi 169 b plat_panic_handler 170endfunc plat_panic_handler 171 172 /* ----------------------------------------------------- 173 * void bl31_plat_enable_mmu(uint32_t flags); 174 * 175 * Enable MMU in BL31. 176 * ----------------------------------------------------- 177 */ 178func bl31_plat_enable_mmu 179 b enable_mmu_direct_el3 180endfunc bl31_plat_enable_mmu 181 182 /* ----------------------------------------------------- 183 * void bl32_plat_enable_mmu(uint32_t flags); 184 * 185 * Enable MMU in BL32. 186 * ----------------------------------------------------- 187 */ 188func bl32_plat_enable_mmu 189 b enable_mmu_direct_el1 190endfunc bl32_plat_enable_mmu 191 192 193 /* ----------------------------------------------------- 194 * Platform handler for Uncontainable External Abort. 195 * 196 * x0: EA reason 197 * x1: EA syndrome 198 * ----------------------------------------------------- 199 */ 200func plat_handle_uncontainable_ea 201 b report_unhandled_exception 202endfunc plat_handle_uncontainable_ea 203 204 /* ----------------------------------------------------- 205 * Platform handler for Double Fault. 206 * 207 * x0: EA reason 208 * x1: EA syndrome 209 * ----------------------------------------------------- 210 */ 211func plat_handle_double_fault 212 b report_unhandled_exception 213endfunc plat_handle_double_fault 214 215 /* ----------------------------------------------------- 216 * Platform handler for EL3 External Abort. 217 * ----------------------------------------------------- 218 */ 219func plat_handle_el3_ea 220 b report_unhandled_exception 221endfunc plat_handle_el3_ea 222