1Trusted Firmware-A Porting Guide 2================================ 3 4 5.. section-numbering:: 6 :suffix: . 7 8.. contents:: 9 10-------------- 11 12Introduction 13------------ 14 15Porting Trusted Firmware-A (TF-A) to a new platform involves making some 16mandatory and optional modifications for both the cold and warm boot paths. 17Modifications consist of: 18 19- Implementing a platform-specific function or variable, 20- Setting up the execution context in a certain way, or 21- Defining certain constants (for example #defines). 22 23The platform-specific functions and variables are declared in 24`include/plat/common/platform.h`_. The firmware provides a default implementation 25of variables and functions to fulfill the optional requirements. These 26implementations are all weakly defined; they are provided to ease the porting 27effort. Each platform port can override them with its own implementation if the 28default implementation is inadequate. 29 30Platform ports that want to be aligned with standard Arm platforms (for example 31FVP and Juno) may also use `include/plat/arm/common/plat\_arm.h`_ and the 32corresponding source files in ``plat/arm/common/``. These provide standard 33implementations for some of the required platform porting functions. However, 34using these functions requires the platform port to implement additional 35Arm standard platform porting functions. These additional functions are not 36documented here. 37 38Some modifications are common to all Boot Loader (BL) stages. Section 2 39discusses these in detail. The subsequent sections discuss the remaining 40modifications for each BL stage in detail. 41 42This document should be read in conjunction with the TF-A `User Guide`_. 43 44Common modifications 45-------------------- 46 47This section covers the modifications that should be made by the platform for 48each BL stage to correctly port the firmware stack. They are categorized as 49either mandatory or optional. 50 51Common mandatory modifications 52------------------------------ 53 54A platform port must enable the Memory Management Unit (MMU) as well as the 55instruction and data caches for each BL stage. Setting up the translation 56tables is the responsibility of the platform port because memory maps differ 57across platforms. A memory translation library (see ``lib/xlat_tables/``) is 58provided to help in this setup. 59 60Note that although this library supports non-identity mappings, this is intended 61only for re-mapping peripheral physical addresses and allows platforms with high 62I/O addresses to reduce their virtual address space. All other addresses 63corresponding to code and data must currently use an identity mapping. 64 65Also, the only translation granule size supported in TF-A is 4KB, as various 66parts of the code assume that is the case. It is not possible to switch to 6716 KB or 64 KB granule sizes at the moment. 68 69In Arm standard platforms, each BL stage configures the MMU in the 70platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses 71an identity mapping for all addresses. 72 73If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a 74block of identity mapped secure memory with Device-nGnRE attributes aligned to 75page boundary (4K) for each BL stage. All sections which allocate coherent 76memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a 77section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its 78possible for the firmware to place variables in it using the following C code 79directive: 80 81:: 82 83 __section("bakery_lock") 84 85Or alternatively the following assembler code directive: 86 87:: 88 89 .section bakery_lock 90 91The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are 92used to allocate any data structures that are accessed both when a CPU is 93executing with its MMU and caches enabled, and when it's running with its MMU 94and caches disabled. Examples are given below. 95 96The following variables, functions and constants must be defined by the platform 97for the firmware to work correctly. 98 99File : platform\_def.h [mandatory] 100~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 101 102Each platform must ensure that a header file of this name is in the system 103include path with the following constants defined. This may require updating the 104list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. In the Arm development 105platforms, this file is found in ``plat/arm/board/<plat_name>/include/``. 106 107Platform ports may optionally use the file `include/plat/common/common\_def.h`_, 108which provides typical values for some of the constants below. These values are 109likely to be suitable for all platform ports. 110 111Platform ports that want to be aligned with standard Arm platforms (for example 112FVP and Juno) may also use `include/plat/arm/common/arm\_def.h`_, which provides 113standard values for some of the constants below. However, this requires the 114platform port to define additional platform porting constants in 115``platform_def.h``. These additional constants are not documented here. 116 117- **#define : PLATFORM\_LINKER\_FORMAT** 118 119 Defines the linker format used by the platform, for example 120 ``elf64-littleaarch64``. 121 122- **#define : PLATFORM\_LINKER\_ARCH** 123 124 Defines the processor architecture for the linker by the platform, for 125 example ``aarch64``. 126 127- **#define : PLATFORM\_STACK\_SIZE** 128 129 Defines the normal stack memory available to each CPU. This constant is used 130 by `plat/common/aarch64/platform\_mp\_stack.S`_ and 131 `plat/common/aarch64/platform\_up\_stack.S`_. 132 133- **define : CACHE\_WRITEBACK\_GRANULE** 134 135 Defines the size in bits of the largest cache line across all the cache 136 levels in the platform. 137 138- **#define : FIRMWARE\_WELCOME\_STR** 139 140 Defines the character string printed by BL1 upon entry into the ``bl1_main()`` 141 function. 142 143- **#define : PLATFORM\_CORE\_COUNT** 144 145 Defines the total number of CPUs implemented by the platform across all 146 clusters in the system. 147 148- **#define : PLAT\_NUM\_PWR\_DOMAINS** 149 150 Defines the total number of nodes in the power domain topology 151 tree at all the power domain levels used by the platform. 152 This macro is used by the PSCI implementation to allocate 153 data structures to represent power domain topology. 154 155- **#define : PLAT\_MAX\_PWR\_LVL** 156 157 Defines the maximum power domain level that the power management operations 158 should apply to. More often, but not always, the power domain level 159 corresponds to affinity level. This macro allows the PSCI implementation 160 to know the highest power domain level that it should consider for power 161 management operations in the system that the platform implements. For 162 example, the Base AEM FVP implements two clusters with a configurable 163 number of CPUs and it reports the maximum power domain level as 1. 164 165- **#define : PLAT\_MAX\_OFF\_STATE** 166 167 Defines the local power state corresponding to the deepest power down 168 possible at every power domain level in the platform. The local power 169 states for each level may be sparsely allocated between 0 and this value 170 with 0 being reserved for the RUN state. The PSCI implementation uses this 171 value to initialize the local power states of the power domain nodes and 172 to specify the requested power state for a PSCI\_CPU\_OFF call. 173 174- **#define : PLAT\_MAX\_RET\_STATE** 175 176 Defines the local power state corresponding to the deepest retention state 177 possible at every power domain level in the platform. This macro should be 178 a value less than PLAT\_MAX\_OFF\_STATE and greater than 0. It is used by the 179 PSCI implementation to distinguish between retention and power down local 180 power states within PSCI\_CPU\_SUSPEND call. 181 182- **#define : PLAT\_MAX\_PWR\_LVL\_STATES** 183 184 Defines the maximum number of local power states per power domain level 185 that the platform supports. The default value of this macro is 2 since 186 most platforms just support a maximum of two local power states at each 187 power domain level (power-down and retention). If the platform needs to 188 account for more local power states, then it must redefine this macro. 189 190 Currently, this macro is used by the Generic PSCI implementation to size 191 the array used for PSCI\_STAT\_COUNT/RESIDENCY accounting. 192 193- **#define : BL1\_RO\_BASE** 194 195 Defines the base address in secure ROM where BL1 originally lives. Must be 196 aligned on a page-size boundary. 197 198- **#define : BL1\_RO\_LIMIT** 199 200 Defines the maximum address in secure ROM that BL1's actual content (i.e. 201 excluding any data section allocated at runtime) can occupy. 202 203- **#define : BL1\_RW\_BASE** 204 205 Defines the base address in secure RAM where BL1's read-write data will live 206 at runtime. Must be aligned on a page-size boundary. 207 208- **#define : BL1\_RW\_LIMIT** 209 210 Defines the maximum address in secure RAM that BL1's read-write data can 211 occupy at runtime. 212 213- **#define : BL2\_BASE** 214 215 Defines the base address in secure RAM where BL1 loads the BL2 binary image. 216 Must be aligned on a page-size boundary. This constant is not applicable 217 when BL2_IN_XIP_MEM is set to '1'. 218 219- **#define : BL2\_LIMIT** 220 221 Defines the maximum address in secure RAM that the BL2 image can occupy. 222 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'. 223 224- **#define : BL2\_RO\_BASE** 225 226 Defines the base address in secure XIP memory where BL2 RO section originally 227 lives. Must be aligned on a page-size boundary. This constant is only needed 228 when BL2_IN_XIP_MEM is set to '1'. 229 230- **#define : BL2\_RO\_LIMIT** 231 232 Defines the maximum address in secure XIP memory that BL2's actual content 233 (i.e. excluding any data section allocated at runtime) can occupy. This 234 constant is only needed when BL2_IN_XIP_MEM is set to '1'. 235 236- **#define : BL2\_RW\_BASE** 237 238 Defines the base address in secure RAM where BL2's read-write data will live 239 at runtime. Must be aligned on a page-size boundary. This constant is only 240 needed when BL2_IN_XIP_MEM is set to '1'. 241 242- **#define : BL2\_RW\_LIMIT** 243 244 Defines the maximum address in secure RAM that BL2's read-write data can 245 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set 246 to '1'. 247 248- **#define : BL31\_BASE** 249 250 Defines the base address in secure RAM where BL2 loads the BL31 binary 251 image. Must be aligned on a page-size boundary. 252 253- **#define : BL31\_LIMIT** 254 255 Defines the maximum address in secure RAM that the BL31 image can occupy. 256 257For every image, the platform must define individual identifiers that will be 258used by BL1 or BL2 to load the corresponding image into memory from non-volatile 259storage. For the sake of performance, integer numbers will be used as 260identifiers. The platform will use those identifiers to return the relevant 261information about the image to be loaded (file handler, load address, 262authentication information, etc.). The following image identifiers are 263mandatory: 264 265- **#define : BL2\_IMAGE\_ID** 266 267 BL2 image identifier, used by BL1 to load BL2. 268 269- **#define : BL31\_IMAGE\_ID** 270 271 BL31 image identifier, used by BL2 to load BL31. 272 273- **#define : BL33\_IMAGE\_ID** 274 275 BL33 image identifier, used by BL2 to load BL33. 276 277If Trusted Board Boot is enabled, the following certificate identifiers must 278also be defined: 279 280- **#define : TRUSTED\_BOOT\_FW\_CERT\_ID** 281 282 BL2 content certificate identifier, used by BL1 to load the BL2 content 283 certificate. 284 285- **#define : TRUSTED\_KEY\_CERT\_ID** 286 287 Trusted key certificate identifier, used by BL2 to load the trusted key 288 certificate. 289 290- **#define : SOC\_FW\_KEY\_CERT\_ID** 291 292 BL31 key certificate identifier, used by BL2 to load the BL31 key 293 certificate. 294 295- **#define : SOC\_FW\_CONTENT\_CERT\_ID** 296 297 BL31 content certificate identifier, used by BL2 to load the BL31 content 298 certificate. 299 300- **#define : NON\_TRUSTED\_FW\_KEY\_CERT\_ID** 301 302 BL33 key certificate identifier, used by BL2 to load the BL33 key 303 certificate. 304 305- **#define : NON\_TRUSTED\_FW\_CONTENT\_CERT\_ID** 306 307 BL33 content certificate identifier, used by BL2 to load the BL33 content 308 certificate. 309 310- **#define : FWU\_CERT\_ID** 311 312 Firmware Update (FWU) certificate identifier, used by NS\_BL1U to load the 313 FWU content certificate. 314 315- **#define : PLAT\_CRYPTOCELL\_BASE** 316 317 This defines the base address of Arm® TrustZone® CryptoCell and must be 318 defined if CryptoCell crypto driver is used for Trusted Board Boot. For 319 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is 320 set. 321 322If the AP Firmware Updater Configuration image, BL2U is used, the following 323must also be defined: 324 325- **#define : BL2U\_BASE** 326 327 Defines the base address in secure memory where BL1 copies the BL2U binary 328 image. Must be aligned on a page-size boundary. 329 330- **#define : BL2U\_LIMIT** 331 332 Defines the maximum address in secure memory that the BL2U image can occupy. 333 334- **#define : BL2U\_IMAGE\_ID** 335 336 BL2U image identifier, used by BL1 to fetch an image descriptor 337 corresponding to BL2U. 338 339If the SCP Firmware Update Configuration Image, SCP\_BL2U is used, the following 340must also be defined: 341 342- **#define : SCP\_BL2U\_IMAGE\_ID** 343 344 SCP\_BL2U image identifier, used by BL1 to fetch an image descriptor 345 corresponding to SCP\_BL2U. 346 NOTE: TF-A does not provide source code for this image. 347 348If the Non-Secure Firmware Updater ROM, NS\_BL1U is used, the following must 349also be defined: 350 351- **#define : NS\_BL1U\_BASE** 352 353 Defines the base address in non-secure ROM where NS\_BL1U executes. 354 Must be aligned on a page-size boundary. 355 NOTE: TF-A does not provide source code for this image. 356 357- **#define : NS\_BL1U\_IMAGE\_ID** 358 359 NS\_BL1U image identifier, used by BL1 to fetch an image descriptor 360 corresponding to NS\_BL1U. 361 362If the Non-Secure Firmware Updater, NS\_BL2U is used, the following must also 363be defined: 364 365- **#define : NS\_BL2U\_BASE** 366 367 Defines the base address in non-secure memory where NS\_BL2U executes. 368 Must be aligned on a page-size boundary. 369 NOTE: TF-A does not provide source code for this image. 370 371- **#define : NS\_BL2U\_IMAGE\_ID** 372 373 NS\_BL2U image identifier, used by BL1 to fetch an image descriptor 374 corresponding to NS\_BL2U. 375 376For the the Firmware update capability of TRUSTED BOARD BOOT, the following 377macros may also be defined: 378 379- **#define : PLAT\_FWU\_MAX\_SIMULTANEOUS\_IMAGES** 380 381 Total number of images that can be loaded simultaneously. If the platform 382 doesn't specify any value, it defaults to 10. 383 384If a SCP\_BL2 image is supported by the platform, the following constants must 385also be defined: 386 387- **#define : SCP\_BL2\_IMAGE\_ID** 388 389 SCP\_BL2 image identifier, used by BL2 to load SCP\_BL2 into secure memory 390 from platform storage before being transfered to the SCP. 391 392- **#define : SCP\_FW\_KEY\_CERT\_ID** 393 394 SCP\_BL2 key certificate identifier, used by BL2 to load the SCP\_BL2 key 395 certificate (mandatory when Trusted Board Boot is enabled). 396 397- **#define : SCP\_FW\_CONTENT\_CERT\_ID** 398 399 SCP\_BL2 content certificate identifier, used by BL2 to load the SCP\_BL2 400 content certificate (mandatory when Trusted Board Boot is enabled). 401 402If a BL32 image is supported by the platform, the following constants must 403also be defined: 404 405- **#define : BL32\_IMAGE\_ID** 406 407 BL32 image identifier, used by BL2 to load BL32. 408 409- **#define : TRUSTED\_OS\_FW\_KEY\_CERT\_ID** 410 411 BL32 key certificate identifier, used by BL2 to load the BL32 key 412 certificate (mandatory when Trusted Board Boot is enabled). 413 414- **#define : TRUSTED\_OS\_FW\_CONTENT\_CERT\_ID** 415 416 BL32 content certificate identifier, used by BL2 to load the BL32 content 417 certificate (mandatory when Trusted Board Boot is enabled). 418 419- **#define : BL32\_BASE** 420 421 Defines the base address in secure memory where BL2 loads the BL32 binary 422 image. Must be aligned on a page-size boundary. 423 424- **#define : BL32\_LIMIT** 425 426 Defines the maximum address that the BL32 image can occupy. 427 428If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the 429platform, the following constants must also be defined: 430 431- **#define : TSP\_SEC\_MEM\_BASE** 432 433 Defines the base address of the secure memory used by the TSP image on the 434 platform. This must be at the same address or below ``BL32_BASE``. 435 436- **#define : TSP\_SEC\_MEM\_SIZE** 437 438 Defines the size of the secure memory used by the BL32 image on the 439 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully accomodate 440 the memory required by the BL32 image, defined by ``BL32_BASE`` and 441 ``BL32_LIMIT``. 442 443- **#define : TSP\_IRQ\_SEC\_PHY\_TIMER** 444 445 Defines the ID of the secure physical generic timer interrupt used by the 446 TSP's interrupt handling code. 447 448If the platform port uses the translation table library code, the following 449constants must also be defined: 450 451- **#define : PLAT\_XLAT\_TABLES\_DYNAMIC** 452 453 Optional flag that can be set per-image to enable the dynamic allocation of 454 regions even when the MMU is enabled. If not defined, only static 455 functionality will be available, if defined and set to 1 it will also 456 include the dynamic functionality. 457 458- **#define : MAX\_XLAT\_TABLES** 459 460 Defines the maximum number of translation tables that are allocated by the 461 translation table library code. To minimize the amount of runtime memory 462 used, choose the smallest value needed to map the required virtual addresses 463 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL 464 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions 465 as well. 466 467- **#define : MAX\_MMAP\_REGIONS** 468 469 Defines the maximum number of regions that are allocated by the translation 470 table library code. A region consists of physical base address, virtual base 471 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as 472 defined in the ``mmap_region_t`` structure. The platform defines the regions 473 that should be mapped. Then, the translation table library will create the 474 corresponding tables and descriptors at runtime. To minimize the amount of 475 runtime memory used, choose the smallest value needed to register the 476 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is 477 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate 478 the dynamic regions as well. 479 480- **#define : ADDR\_SPACE\_SIZE** 481 482 Defines the total size of the address space in bytes. For example, for a 32 483 bit address space, this value should be ``(1ULL << 32)``. This definition is 484 now deprecated, platforms should use ``PLAT_PHY_ADDR_SPACE_SIZE`` and 485 ``PLAT_VIRT_ADDR_SPACE_SIZE`` instead. 486 487- **#define : PLAT\_VIRT\_ADDR\_SPACE\_SIZE** 488 489 Defines the total size of the virtual address space in bytes. For example, 490 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``. 491 492- **#define : PLAT\_PHY\_ADDR\_SPACE\_SIZE** 493 494 Defines the total size of the physical address space in bytes. For example, 495 for a 32 bit physical address space, this value should be ``(1ULL << 32)``. 496 497If the platform port uses the IO storage framework, the following constants 498must also be defined: 499 500- **#define : MAX\_IO\_DEVICES** 501 502 Defines the maximum number of registered IO devices. Attempting to register 503 more devices than this value using ``io_register_device()`` will fail with 504 -ENOMEM. 505 506- **#define : MAX\_IO\_HANDLES** 507 508 Defines the maximum number of open IO handles. Attempting to open more IO 509 entities than this value using ``io_open()`` will fail with -ENOMEM. 510 511- **#define : MAX\_IO\_BLOCK\_DEVICES** 512 513 Defines the maximum number of registered IO block devices. Attempting to 514 register more devices this value using ``io_dev_open()`` will fail 515 with -ENOMEM. MAX\_IO\_BLOCK\_DEVICES should be less than MAX\_IO\_DEVICES. 516 With this macro, multiple block devices could be supported at the same 517 time. 518 519If the platform needs to allocate data within the per-cpu data framework in 520BL31, it should define the following macro. Currently this is only required if 521the platform decides not to use the coherent memory section by undefining the 522``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the 523required memory within the the per-cpu data to minimize wastage. 524 525- **#define : PLAT\_PCPU\_DATA\_SIZE** 526 527 Defines the memory (in bytes) to be reserved within the per-cpu data 528 structure for use by the platform layer. 529 530The following constants are optional. They should be defined when the platform 531memory layout implies some image overlaying like in Arm standard platforms. 532 533- **#define : BL31\_PROGBITS\_LIMIT** 534 535 Defines the maximum address in secure RAM that the BL31's progbits sections 536 can occupy. 537 538- **#define : TSP\_PROGBITS\_LIMIT** 539 540 Defines the maximum address that the TSP's progbits sections can occupy. 541 542If the platform port uses the PL061 GPIO driver, the following constant may 543optionally be defined: 544 545- **PLAT\_PL061\_MAX\_GPIOS** 546 Maximum number of GPIOs required by the platform. This allows control how 547 much memory is allocated for PL061 GPIO controllers. The default value is 548 549 #. $(eval $(call add\_define,PLAT\_PL061\_MAX\_GPIOS)) 550 551If the platform port uses the partition driver, the following constant may 552optionally be defined: 553 554- **PLAT\_PARTITION\_MAX\_ENTRIES** 555 Maximum number of partition entries required by the platform. This allows 556 control how much memory is allocated for partition entries. The default 557 value is 128. 558 `For example, define the build flag in platform.mk`_: 559 PLAT\_PARTITION\_MAX\_ENTRIES := 12 560 $(eval $(call add\_define,PLAT\_PARTITION\_MAX\_ENTRIES)) 561 562The following constant is optional. It should be defined to override the default 563behaviour of the ``assert()`` function (for example, to save memory). 564 565- **PLAT\_LOG\_LEVEL\_ASSERT** 566 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, 567 ``assert()`` prints the name of the file, the line number and the asserted 568 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file 569 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it 570 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't 571 defined, it defaults to ``LOG_LEVEL``. 572 573If the platform port uses the Activity Monitor Unit, the following constants 574may be defined: 575 576- **PLAT\_AMU\_GROUP1\_COUNTERS\_MASK** 577 This mask reflects the set of group counters that should be enabled. The 578 maximum number of group 1 counters supported by AMUv1 is 16 so the mask 579 can be at most 0xffff. If the platform does not define this mask, no group 1 580 counters are enabled. If the platform defines this mask, the following 581 constant needs to also be defined. 582 583- **PLAT\_AMU\_GROUP1\_NR\_COUNTERS** 584 This value is used to allocate an array to save and restore the counters 585 specified by ``PLAT_AMU_GROUP1_COUNTERS_MASK`` on CPU suspend. 586 This value should be equal to the highest bit position set in the 587 mask, plus 1. The maximum number of group 1 counters in AMUv1 is 16. 588 589File : plat\_macros.S [mandatory] 590~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 591 592Each platform must ensure a file of this name is in the system include path with 593the following macro defined. In the Arm development platforms, this file is 594found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. 595 596- **Macro : plat\_crash\_print\_regs** 597 598 This macro allows the crash reporting routine to print relevant platform 599 registers in case of an unhandled exception in BL31. This aids in debugging 600 and this macro can be defined to be empty in case register reporting is not 601 desired. 602 603 For instance, GIC or interconnect registers may be helpful for 604 troubleshooting. 605 606Handling Reset 607-------------- 608 609BL1 by default implements the reset vector where execution starts from a cold 610or warm boot. BL31 can be optionally set as a reset vector using the 611``RESET_TO_BL31`` make variable. 612 613For each CPU, the reset vector code is responsible for the following tasks: 614 615#. Distinguishing between a cold boot and a warm boot. 616 617#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that 618 the CPU is placed in a platform-specific state until the primary CPU 619 performs the necessary steps to remove it from this state. 620 621#. In the case of a warm boot, ensuring that the CPU jumps to a platform- 622 specific address in the BL31 image in the same processor mode as it was 623 when released from reset. 624 625The following functions need to be implemented by the platform port to enable 626reset vector code to perform the above tasks. 627 628Function : plat\_get\_my\_entrypoint() [mandatory when PROGRAMMABLE\_RESET\_ADDRESS == 0] 629~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 630 631:: 632 633 Argument : void 634 Return : uintptr_t 635 636This function is called with the MMU and caches disabled 637(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for 638distinguishing between a warm and cold reset for the current CPU using 639platform-specific means. If it's a warm reset, then it returns the warm 640reset entrypoint point provided to ``plat_setup_psci_ops()`` during 641BL31 initialization. If it's a cold reset then this function must return zero. 642 643This function does not follow the Procedure Call Standard used by the 644Application Binary Interface for the Arm 64-bit architecture. The caller should 645not assume that callee saved registers are preserved across a call to this 646function. 647 648This function fulfills requirement 1 and 3 listed above. 649 650Note that for platforms that support programming the reset address, it is 651expected that a CPU will start executing code directly at the right address, 652both on a cold and warm reset. In this case, there is no need to identify the 653type of reset nor to query the warm reset entrypoint. Therefore, implementing 654this function is not required on such platforms. 655 656Function : plat\_secondary\_cold\_boot\_setup() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0] 657~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 658 659:: 660 661 Argument : void 662 663This function is called with the MMU and data caches disabled. It is responsible 664for placing the executing secondary CPU in a platform-specific state until the 665primary CPU performs the necessary actions to bring it out of that state and 666allow entry into the OS. This function must not return. 667 668In the Arm FVP port, when using the normal boot flow, each secondary CPU powers 669itself off. The primary CPU is responsible for powering up the secondary CPUs 670when normal world software requires them. When booting an EL3 payload instead, 671they stay powered on and are put in a holding pen until their mailbox gets 672populated. 673 674This function fulfills requirement 2 above. 675 676Note that for platforms that can't release secondary CPUs out of reset, only the 677primary CPU will execute the cold boot code. Therefore, implementing this 678function is not required on such platforms. 679 680Function : plat\_is\_my\_cpu\_primary() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0] 681~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 682 683:: 684 685 Argument : void 686 Return : unsigned int 687 688This function identifies whether the current CPU is the primary CPU or a 689secondary CPU. A return value of zero indicates that the CPU is not the 690primary CPU, while a non-zero return value indicates that the CPU is the 691primary CPU. 692 693Note that for platforms that can't release secondary CPUs out of reset, only the 694primary CPU will execute the cold boot code. Therefore, there is no need to 695distinguish between primary and secondary CPUs and implementing this function is 696not required. 697 698Function : platform\_mem\_init() [mandatory] 699~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 700 701:: 702 703 Argument : void 704 Return : void 705 706This function is called before any access to data is made by the firmware, in 707order to carry out any essential memory initialization. 708 709Function: plat\_get\_rotpk\_info() 710~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 711 712:: 713 714 Argument : void *, void **, unsigned int *, unsigned int * 715 Return : int 716 717This function is mandatory when Trusted Board Boot is enabled. It returns a 718pointer to the ROTPK stored in the platform (or a hash of it) and its length. 719The ROTPK must be encoded in DER format according to the following ASN.1 720structure: 721 722:: 723 724 AlgorithmIdentifier ::= SEQUENCE { 725 algorithm OBJECT IDENTIFIER, 726 parameters ANY DEFINED BY algorithm OPTIONAL 727 } 728 729 SubjectPublicKeyInfo ::= SEQUENCE { 730 algorithm AlgorithmIdentifier, 731 subjectPublicKey BIT STRING 732 } 733 734In case the function returns a hash of the key: 735 736:: 737 738 DigestInfo ::= SEQUENCE { 739 digestAlgorithm AlgorithmIdentifier, 740 digest OCTET STRING 741 } 742 743The function returns 0 on success. Any other value is treated as error by the 744Trusted Board Boot. The function also reports extra information related 745to the ROTPK in the flags parameter: 746 747:: 748 749 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a 750 hash. 751 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK 752 verification while the platform ROTPK is not deployed. 753 When this flag is set, the function does not need to 754 return a platform ROTPK, and the authentication 755 framework uses the ROTPK in the certificate without 756 verifying it against the platform value. This flag 757 must not be used in a deployed production environment. 758 759Function: plat\_get\_nv\_ctr() 760~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 761 762:: 763 764 Argument : void *, unsigned int * 765 Return : int 766 767This function is mandatory when Trusted Board Boot is enabled. It returns the 768non-volatile counter value stored in the platform in the second argument. The 769cookie in the first argument may be used to select the counter in case the 770platform provides more than one (for example, on platforms that use the default 771TBBR CoT, the cookie will correspond to the OID values defined in 772TRUSTED\_FW\_NVCOUNTER\_OID or NON\_TRUSTED\_FW\_NVCOUNTER\_OID). 773 774The function returns 0 on success. Any other value means the counter value could 775not be retrieved from the platform. 776 777Function: plat\_set\_nv\_ctr() 778~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 779 780:: 781 782 Argument : void *, unsigned int 783 Return : int 784 785This function is mandatory when Trusted Board Boot is enabled. It sets a new 786counter value in the platform. The cookie in the first argument may be used to 787select the counter (as explained in plat\_get\_nv\_ctr()). The second argument is 788the updated counter value to be written to the NV counter. 789 790The function returns 0 on success. Any other value means the counter value could 791not be updated. 792 793Function: plat\_set\_nv\_ctr2() 794~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 795 796:: 797 798 Argument : void *, const auth_img_desc_t *, unsigned int 799 Return : int 800 801This function is optional when Trusted Board Boot is enabled. If this 802interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The 803first argument passed is a cookie and is typically used to 804differentiate between a Non Trusted NV Counter and a Trusted NV 805Counter. The second argument is a pointer to an authentication image 806descriptor and may be used to decide if the counter is allowed to be 807updated or not. The third argument is the updated counter value to 808be written to the NV counter. 809 810The function returns 0 on success. Any other value means the counter value 811either could not be updated or the authentication image descriptor indicates 812that it is not allowed to be updated. 813 814Common mandatory function modifications 815--------------------------------------- 816 817The following functions are mandatory functions which need to be implemented 818by the platform port. 819 820Function : plat\_my\_core\_pos() 821~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 822 823:: 824 825 Argument : void 826 Return : unsigned int 827 828This funtion returns the index of the calling CPU which is used as a 829CPU-specific linear index into blocks of memory (for example while allocating 830per-CPU stacks). This function will be invoked very early in the 831initialization sequence which mandates that this function should be 832implemented in assembly and should not rely on the avalability of a C 833runtime environment. This function can clobber x0 - x8 and must preserve 834x9 - x29. 835 836This function plays a crucial role in the power domain topology framework in 837PSCI and details of this can be found in `Power Domain Topology Design`_. 838 839Function : plat\_core\_pos\_by\_mpidr() 840~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 841 842:: 843 844 Argument : u_register_t 845 Return : int 846 847This function validates the ``MPIDR`` of a CPU and converts it to an index, 848which can be used as a CPU-specific linear index into blocks of memory. In 849case the ``MPIDR`` is invalid, this function returns -1. This function will only 850be invoked by BL31 after the power domain topology is initialized and can 851utilize the C runtime environment. For further details about how TF-A 852represents the power domain topology and how this relates to the linear CPU 853index, please refer `Power Domain Topology Design`_. 854 855Common optional modifications 856----------------------------- 857 858The following are helper functions implemented by the firmware that perform 859common platform-specific tasks. A platform may choose to override these 860definitions. 861 862Function : plat\_set\_my\_stack() 863~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 864 865:: 866 867 Argument : void 868 Return : void 869 870This function sets the current stack pointer to the normal memory stack that 871has been allocated for the current CPU. For BL images that only require a 872stack for the primary CPU, the UP version of the function is used. The size 873of the stack allocated to each CPU is specified by the platform defined 874constant ``PLATFORM_STACK_SIZE``. 875 876Common implementations of this function for the UP and MP BL images are 877provided in `plat/common/aarch64/platform\_up\_stack.S`_ and 878`plat/common/aarch64/platform\_mp\_stack.S`_ 879 880Function : plat\_get\_my\_stack() 881~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 882 883:: 884 885 Argument : void 886 Return : uintptr_t 887 888This function returns the base address of the normal memory stack that 889has been allocated for the current CPU. For BL images that only require a 890stack for the primary CPU, the UP version of the function is used. The size 891of the stack allocated to each CPU is specified by the platform defined 892constant ``PLATFORM_STACK_SIZE``. 893 894Common implementations of this function for the UP and MP BL images are 895provided in `plat/common/aarch64/platform\_up\_stack.S`_ and 896`plat/common/aarch64/platform\_mp\_stack.S`_ 897 898Function : plat\_report\_exception() 899~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 900 901:: 902 903 Argument : unsigned int 904 Return : void 905 906A platform may need to report various information about its status when an 907exception is taken, for example the current exception level, the CPU security 908state (secure/non-secure), the exception type, and so on. This function is 909called in the following circumstances: 910 911- In BL1, whenever an exception is taken. 912- In BL2, whenever an exception is taken. 913 914The default implementation doesn't do anything, to avoid making assumptions 915about the way the platform displays its status information. 916 917For AArch64, this function receives the exception type as its argument. 918Possible values for exceptions types are listed in the 919`include/common/bl\_common.h`_ header file. Note that these constants are not 920related to any architectural exception code; they are just a TF-A convention. 921 922For AArch32, this function receives the exception mode as its argument. 923Possible values for exception modes are listed in the 924`include/lib/aarch32/arch.h`_ header file. 925 926Function : plat\_reset\_handler() 927~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 928 929:: 930 931 Argument : void 932 Return : void 933 934A platform may need to do additional initialization after reset. This function 935allows the platform to do the platform specific intializations. Platform 936specific errata workarounds could also be implemented here. The api should 937preserve the values of callee saved registers x19 to x29. 938 939The default implementation doesn't do anything. If a platform needs to override 940the default implementation, refer to the `Firmware Design`_ for general 941guidelines. 942 943Function : plat\_disable\_acp() 944~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 945 946:: 947 948 Argument : void 949 Return : void 950 951This API allows a platform to disable the Accelerator Coherency Port (if 952present) during a cluster power down sequence. The default weak implementation 953doesn't do anything. Since this API is called during the power down sequence, 954it has restrictions for stack usage and it can use the registers x0 - x17 as 955scratch registers. It should preserve the value in x18 register as it is used 956by the caller to store the return address. 957 958Function : plat\_error\_handler() 959~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 960 961:: 962 963 Argument : int 964 Return : void 965 966This API is called when the generic code encounters an error situation from 967which it cannot continue. It allows the platform to perform error reporting or 968recovery actions (for example, reset the system). This function must not return. 969 970The parameter indicates the type of error using standard codes from ``errno.h``. 971Possible errors reported by the generic code are: 972 973- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted 974 Board Boot is enabled) 975- ``-ENOENT``: the requested image or certificate could not be found or an IO 976 error was detected 977- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this 978 error is usually an indication of an incorrect array size 979 980The default implementation simply spins. 981 982Function : plat\_panic\_handler() 983~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 984 985:: 986 987 Argument : void 988 Return : void 989 990This API is called when the generic code encounters an unexpected error 991situation from which it cannot recover. This function must not return, 992and must be implemented in assembly because it may be called before the C 993environment is initialized. 994 995Note: The address from where it was called is stored in x30 (Link Register). 996The default implementation simply spins. 997 998Function : plat\_get\_bl\_image\_load\_info() 999~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1000 1001:: 1002 1003 Argument : void 1004 Return : bl_load_info_t * 1005 1006This function returns pointer to the list of images that the platform has 1007populated to load. This function is currently invoked in BL2 to load the 1008BL3xx images, when LOAD\_IMAGE\_V2 is enabled. 1009 1010Function : plat\_get\_next\_bl\_params() 1011~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1012 1013:: 1014 1015 Argument : void 1016 Return : bl_params_t * 1017 1018This function returns a pointer to the shared memory that the platform has 1019kept aside to pass TF-A related information that next BL image needs. This 1020function is currently invoked in BL2 to pass this information to the next BL 1021image, when LOAD\_IMAGE\_V2 is enabled. 1022 1023Function : plat\_get\_stack\_protector\_canary() 1024~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1025 1026:: 1027 1028 Argument : void 1029 Return : u_register_t 1030 1031This function returns a random value that is used to initialize the canary used 1032when the stack protector is enabled with ENABLE\_STACK\_PROTECTOR. A predictable 1033value will weaken the protection as the attacker could easily write the right 1034value as part of the attack most of the time. Therefore, it should return a 1035true random number. 1036 1037Note: For the protection to be effective, the global data need to be placed at 1038a lower address than the stack bases. Failure to do so would allow an attacker 1039to overwrite the canary as part of the stack buffer overflow attack. 1040 1041Function : plat\_flush\_next\_bl\_params() 1042~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1043 1044:: 1045 1046 Argument : void 1047 Return : void 1048 1049This function flushes to main memory all the image params that are passed to 1050next image. This function is currently invoked in BL2 to flush this information 1051to the next BL image, when LOAD\_IMAGE\_V2 is enabled. 1052 1053Function : plat\_log\_get\_prefix() 1054~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1055 1056:: 1057 1058 Argument : unsigned int 1059 Return : const char * 1060 1061This function defines the prefix string corresponding to the `log_level` to be 1062prepended to all the log output from TF-A. The `log_level` (argument) will 1063correspond to one of the standard log levels defined in debug.h. The platform 1064can override the common implementation to define a different prefix string for 1065the log output. The implementation should be robust to future changes that 1066increase the number of log levels. 1067 1068Function : plat\_get\_mbedtls\_heap() 1069~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1070 1071:: 1072 1073 Arguments : void **heap_addr, size_t *heap_size 1074 Return : int 1075 1076This function is invoked during Mbed TLS library initialisation to get 1077a heap, by means of a starting address and a size. This heap will then be used 1078internally by the Mbed TLS library. The heap is requested from the current BL 1079stage, i.e. the current BL image inside which Mbed TLS is used. 1080 1081In the default implementation a heap is statically allocated inside every image 1082(i.e. every BL stage) that utilises Mbed TLS. So, in this case, the function 1083simply returns the address and size of this "pre-allocated" heap. However, by 1084overriding the default implementation, platforms have the potential to optimise 1085memory usage. For example, on some Arm platforms, the Mbed TLS heap is shared 1086between BL1 and BL2 stages and, thus, the necessary space is not reserved 1087twice. 1088 1089On success the function should return 0 and a negative error code otherwise. 1090 1091Modifications specific to a Boot Loader stage 1092--------------------------------------------- 1093 1094Boot Loader Stage 1 (BL1) 1095------------------------- 1096 1097BL1 implements the reset vector where execution starts from after a cold or 1098warm boot. For each CPU, BL1 is responsible for the following tasks: 1099 1100#. Handling the reset as described in section 2.2 1101 1102#. In the case of a cold boot and the CPU being the primary CPU, ensuring that 1103 only this CPU executes the remaining BL1 code, including loading and passing 1104 control to the BL2 stage. 1105 1106#. Identifying and starting the Firmware Update process (if required). 1107 1108#. Loading the BL2 image from non-volatile storage into secure memory at the 1109 address specified by the platform defined constant ``BL2_BASE``. 1110 1111#. Populating a ``meminfo`` structure with the following information in memory, 1112 accessible by BL2 immediately upon entry. 1113 1114 :: 1115 1116 meminfo.total_base = Base address of secure RAM visible to BL2 1117 meminfo.total_size = Size of secure RAM visible to BL2 1118 meminfo.free_base = Base address of secure RAM available for 1119 allocation to BL2 1120 meminfo.free_size = Size of secure RAM available for allocation to BL2 1121 1122 By default, BL1 places this ``meminfo`` structure at the beginning of the 1123 free memory available for its use. Since BL1 cannot allocate memory 1124 dynamically at the moment, its free memory will be available for BL2's use 1125 as-is. However, this means that BL2 must read the ``meminfo`` structure 1126 before it starts using its free memory (this is discussed in Section 3.2). 1127 1128 It is possible for the platform to decide where it wants to place the 1129 ``meminfo`` structure for BL2 or restrict the amount of memory visible to 1130 BL2 by overriding the weak default implementation of 1131 ``bl1_plat_handle_post_image_load`` API. 1132 1133The following functions need to be implemented by the platform port to enable 1134BL1 to perform the above tasks. 1135 1136Function : bl1\_early\_platform\_setup() [mandatory] 1137~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1138 1139:: 1140 1141 Argument : void 1142 Return : void 1143 1144This function executes with the MMU and data caches disabled. It is only called 1145by the primary CPU. 1146 1147On Arm standard platforms, this function: 1148 1149- Enables a secure instance of SP805 to act as the Trusted Watchdog. 1150 1151- Initializes a UART (PL011 console), which enables access to the ``printf`` 1152 family of functions in BL1. 1153 1154- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to 1155 the CCI slave interface corresponding to the cluster that includes the 1156 primary CPU. 1157 1158Function : bl1\_plat\_arch\_setup() [mandatory] 1159~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1160 1161:: 1162 1163 Argument : void 1164 Return : void 1165 1166This function performs any platform-specific and architectural setup that the 1167platform requires. Platform-specific setup might include configuration of 1168memory controllers and the interconnect. 1169 1170In Arm standard platforms, this function enables the MMU. 1171 1172This function helps fulfill requirement 2 above. 1173 1174Function : bl1\_platform\_setup() [mandatory] 1175~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1176 1177:: 1178 1179 Argument : void 1180 Return : void 1181 1182This function executes with the MMU and data caches enabled. It is responsible 1183for performing any remaining platform-specific setup that can occur after the 1184MMU and data cache have been enabled. 1185 1186if support for multiple boot sources is required, it initializes the boot 1187sequence used by plat\_try\_next\_boot\_source(). 1188 1189In Arm standard platforms, this function initializes the storage abstraction 1190layer used to load the next bootloader image. 1191 1192This function helps fulfill requirement 4 above. 1193 1194Function : bl1\_plat\_sec\_mem\_layout() [mandatory] 1195~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1196 1197:: 1198 1199 Argument : void 1200 Return : meminfo * 1201 1202This function should only be called on the cold boot path. It executes with the 1203MMU and data caches enabled. The pointer returned by this function must point to 1204a ``meminfo`` structure containing the extents and availability of secure RAM for 1205the BL1 stage. 1206 1207:: 1208 1209 meminfo.total_base = Base address of secure RAM visible to BL1 1210 meminfo.total_size = Size of secure RAM visible to BL1 1211 meminfo.free_base = Base address of secure RAM available for allocation 1212 to BL1 1213 meminfo.free_size = Size of secure RAM available for allocation to BL1 1214 1215This information is used by BL1 to load the BL2 image in secure RAM. BL1 also 1216populates a similar structure to tell BL2 the extents of memory available for 1217its own use. 1218 1219This function helps fulfill requirements 4 and 5 above. 1220 1221Function : bl1\_plat\_prepare\_exit() [optional] 1222~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1223 1224:: 1225 1226 Argument : entry_point_info_t * 1227 Return : void 1228 1229This function is called prior to exiting BL1 in response to the 1230``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform 1231platform specific clean up or bookkeeping operations before transferring 1232control to the next image. It receives the address of the ``entry_point_info_t`` 1233structure passed from BL2. This function runs with MMU disabled. 1234 1235Function : bl1\_plat\_set\_ep\_info() [optional] 1236~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1237 1238:: 1239 1240 Argument : unsigned int image_id, entry_point_info_t *ep_info 1241 Return : void 1242 1243This function allows platforms to override ``ep_info`` for the given ``image_id``. 1244 1245The default implementation just returns. 1246 1247Function : bl1\_plat\_get\_next\_image\_id() [optional] 1248~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1249 1250:: 1251 1252 Argument : void 1253 Return : unsigned int 1254 1255This and the following function must be overridden to enable the FWU feature. 1256 1257BL1 calls this function after platform setup to identify the next image to be 1258loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds 1259with the normal boot sequence, which loads and executes BL2. If the platform 1260returns a different image id, BL1 assumes that Firmware Update is required. 1261 1262The default implementation always returns ``BL2_IMAGE_ID``. The Arm development 1263platforms override this function to detect if firmware update is required, and 1264if so, return the first image in the firmware update process. 1265 1266Function : bl1\_plat\_get\_image\_desc() [optional] 1267~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1268 1269:: 1270 1271 Argument : unsigned int image_id 1272 Return : image_desc_t * 1273 1274BL1 calls this function to get the image descriptor information ``image_desc_t`` 1275for the provided ``image_id`` from the platform. 1276 1277The default implementation always returns a common BL2 image descriptor. Arm 1278standard platforms return an image descriptor corresponding to BL2 or one of 1279the firmware update images defined in the Trusted Board Boot Requirements 1280specification. 1281 1282Function : bl1\_plat\_handle\_pre\_image\_load() [optional] 1283~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1284 1285:: 1286 1287 Argument : unsigned int image_id 1288 Return : int 1289 1290This function can be used by the platforms to update/use image information 1291corresponding to ``image_id``. This function is invoked in BL1, both in cold 1292boot and FWU code path, before loading the image. 1293 1294Function : bl1\_plat\_handle\_post\_image\_load() [optional] 1295~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1296 1297:: 1298 1299 Argument : unsigned int image_id 1300 Return : int 1301 1302This function can be used by the platforms to update/use image information 1303corresponding to ``image_id``. This function is invoked in BL1, both in cold 1304boot and FWU code path, after loading and authenticating the image. 1305 1306The default weak implementation of this function calculates the amount of 1307Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t`` 1308structure at the beginning of this free memory and populates it. The address 1309of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint 1310information to BL2. 1311 1312Function : bl1\_plat\_fwu\_done() [optional] 1313~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1314 1315:: 1316 1317 Argument : unsigned int image_id, uintptr_t image_src, 1318 unsigned int image_size 1319 Return : void 1320 1321BL1 calls this function when the FWU process is complete. It must not return. 1322The platform may override this function to take platform specific action, for 1323example to initiate the normal boot flow. 1324 1325The default implementation spins forever. 1326 1327Function : bl1\_plat\_mem\_check() [mandatory] 1328~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1329 1330:: 1331 1332 Argument : uintptr_t mem_base, unsigned int mem_size, 1333 unsigned int flags 1334 Return : int 1335 1336BL1 calls this function while handling FWU related SMCs, more specifically when 1337copying or authenticating an image. Its responsibility is to ensure that the 1338region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and 1339that this memory corresponds to either a secure or non-secure memory region as 1340indicated by the security state of the ``flags`` argument. 1341 1342This function can safely assume that the value resulting from the addition of 1343``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not 1344overflow. 1345 1346This function must return 0 on success, a non-null error code otherwise. 1347 1348The default implementation of this function asserts therefore platforms must 1349override it when using the FWU feature. 1350 1351Boot Loader Stage 2 (BL2) 1352------------------------- 1353 1354The BL2 stage is executed only by the primary CPU, which is determined in BL1 1355using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at 1356``BL2_BASE``. BL2 executes in Secure EL1 and is responsible for: 1357 1358#. (Optional) Loading the SCP\_BL2 binary image (if present) from platform 1359 provided non-volatile storage. To load the SCP\_BL2 image, BL2 makes use of 1360 the ``meminfo`` returned by the ``bl2_plat_get_scp_bl2_meminfo()`` function. 1361 The platform also defines the address in memory where SCP\_BL2 is loaded 1362 through the optional constant ``SCP_BL2_BASE``. BL2 uses this information 1363 to determine if there is enough memory to load the SCP\_BL2 image. 1364 Subsequent handling of the SCP\_BL2 image is platform-specific and is 1365 implemented in the ``bl2_plat_handle_scp_bl2()`` function. 1366 If ``SCP_BL2_BASE`` is not defined then this step is not performed. 1367 1368#. Loading the BL31 binary image into secure RAM from non-volatile storage. To 1369 load the BL31 image, BL2 makes use of the ``meminfo`` structure passed to it 1370 by BL1. This structure allows BL2 to calculate how much secure RAM is 1371 available for its use. The platform also defines the address in secure RAM 1372 where BL31 is loaded through the constant ``BL31_BASE``. BL2 uses this 1373 information to determine if there is enough memory to load the BL31 image. 1374 1375#. (Optional) Loading the BL32 binary image (if present) from platform 1376 provided non-volatile storage. To load the BL32 image, BL2 makes use of 1377 the ``meminfo`` returned by the ``bl2_plat_get_bl32_meminfo()`` function. 1378 The platform also defines the address in memory where BL32 is loaded 1379 through the optional constant ``BL32_BASE``. BL2 uses this information 1380 to determine if there is enough memory to load the BL32 image. 1381 If ``BL32_BASE`` is not defined then this and the next step is not performed. 1382 1383#. (Optional) Arranging to pass control to the BL32 image (if present) that 1384 has been pre-loaded at ``BL32_BASE``. BL2 populates an ``entry_point_info`` 1385 structure in memory provided by the platform with information about how 1386 BL31 should pass control to the BL32 image. 1387 1388#. (Optional) Loading the normal world BL33 binary image (if not loaded by 1389 other means) into non-secure DRAM from platform storage and arranging for 1390 BL31 to pass control to this image. This address is determined using the 1391 ``plat_get_ns_image_entrypoint()`` function described below. 1392 1393#. BL2 populates an ``entry_point_info`` structure in memory provided by the 1394 platform with information about how BL31 should pass control to the 1395 other BL images. 1396 1397The following functions must be implemented by the platform port to enable BL2 1398to perform the above tasks. 1399 1400Function : bl2\_early\_platform\_setup() [mandatory] 1401~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1402 1403:: 1404 1405 Argument : meminfo * 1406 Return : void 1407 1408This function executes with the MMU and data caches disabled. It is only called 1409by the primary CPU. The arguments to this function is the address of the 1410``meminfo`` structure populated by BL1. 1411 1412The platform may copy the contents of the ``meminfo`` structure into a private 1413variable as the original memory may be subsequently overwritten by BL2. The 1414copied structure is made available to all BL2 code through the 1415``bl2_plat_sec_mem_layout()`` function. 1416 1417On Arm standard platforms, this function also: 1418 1419- Initializes a UART (PL011 console), which enables access to the ``printf`` 1420 family of functions in BL2. 1421 1422- Initializes the storage abstraction layer used to load further bootloader 1423 images. It is necessary to do this early on platforms with a SCP\_BL2 image, 1424 since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded. 1425 1426Function : bl2\_plat\_arch\_setup() [mandatory] 1427~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1428 1429:: 1430 1431 Argument : void 1432 Return : void 1433 1434This function executes with the MMU and data caches disabled. It is only called 1435by the primary CPU. 1436 1437The purpose of this function is to perform any architectural initialization 1438that varies across platforms. 1439 1440On Arm standard platforms, this function enables the MMU. 1441 1442Function : bl2\_platform\_setup() [mandatory] 1443~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1444 1445:: 1446 1447 Argument : void 1448 Return : void 1449 1450This function may execute with the MMU and data caches enabled if the platform 1451port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only 1452called by the primary CPU. 1453 1454The purpose of this function is to perform any platform initialization 1455specific to BL2. 1456 1457In Arm standard platforms, this function performs security setup, including 1458configuration of the TrustZone controller to allow non-secure masters access 1459to most of DRAM. Part of DRAM is reserved for secure world use. 1460 1461Function : bl2\_plat\_sec\_mem\_layout() [mandatory] 1462~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1463 1464:: 1465 1466 Argument : void 1467 Return : meminfo * 1468 1469This function should only be called on the cold boot path. It may execute with 1470the MMU and data caches enabled if the platform port does the necessary 1471initialization in ``bl2_plat_arch_setup()``. It is only called by the primary CPU. 1472 1473The purpose of this function is to return a pointer to a ``meminfo`` structure 1474populated with the extents of secure RAM available for BL2 to use. See 1475``bl2_early_platform_setup()`` above. 1476 1477Following functions are optionally used only when LOAD\_IMAGE\_V2 is enabled. 1478 1479Function : bl2\_plat\_handle\_pre\_image\_load() [optional] 1480~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1481 1482:: 1483 1484 Argument : unsigned int 1485 Return : int 1486 1487This function can be used by the platforms to update/use image information 1488for given ``image_id``. This function is currently invoked in BL2 before 1489loading each image, when LOAD\_IMAGE\_V2 is enabled. 1490 1491Function : bl2\_plat\_handle\_post\_image\_load() [optional] 1492~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1493 1494:: 1495 1496 Argument : unsigned int 1497 Return : int 1498 1499This function can be used by the platforms to update/use image information 1500for given ``image_id``. This function is currently invoked in BL2 after 1501loading each image, when LOAD\_IMAGE\_V2 is enabled. 1502 1503Following functions are required only when LOAD\_IMAGE\_V2 is disabled. 1504 1505Function : bl2\_plat\_get\_scp\_bl2\_meminfo() [mandatory] 1506~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1507 1508:: 1509 1510 Argument : meminfo * 1511 Return : void 1512 1513This function is used to get the memory limits where BL2 can load the 1514SCP\_BL2 image. The meminfo provided by this is used by load\_image() to 1515validate whether the SCP\_BL2 image can be loaded within the given 1516memory from the given base. 1517 1518Function : bl2\_plat\_handle\_scp\_bl2() [mandatory] 1519~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1520 1521:: 1522 1523 Argument : image_info * 1524 Return : int 1525 1526This function is called after loading SCP\_BL2 image and it is used to perform 1527any platform-specific actions required to handle the SCP firmware. Typically it 1528transfers the image into SCP memory using a platform-specific protocol and waits 1529until SCP executes it and signals to the Application Processor (AP) for BL2 1530execution to continue. 1531 1532This function returns 0 on success, a negative error code otherwise. 1533 1534Function : bl2\_plat\_get\_bl31\_params() [mandatory] 1535~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1536 1537:: 1538 1539 Argument : void 1540 Return : bl31_params * 1541 1542BL2 platform code needs to return a pointer to a ``bl31_params`` structure it 1543will use for passing information to BL31. The ``bl31_params`` structure carries 1544the following information. 1545- Header describing the version information for interpreting the bl31\_param 1546structure 1547- Information about executing the BL33 image in the ``bl33_ep_info`` field 1548- Information about executing the BL32 image in the ``bl32_ep_info`` field 1549- Information about the type and extents of BL31 image in the 1550``bl31_image_info`` field 1551- Information about the type and extents of BL32 image in the 1552``bl32_image_info`` field 1553- Information about the type and extents of BL33 image in the 1554``bl33_image_info`` field 1555 1556The memory pointed by this structure and its sub-structures should be 1557accessible from BL31 initialisation code. BL31 might choose to copy the 1558necessary content, or maintain the structures until BL33 is initialised. 1559 1560Funtion : bl2\_plat\_get\_bl31\_ep\_info() [mandatory] 1561~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1562 1563:: 1564 1565 Argument : void 1566 Return : entry_point_info * 1567 1568BL2 platform code returns a pointer which is used to populate the entry point 1569information for BL31 entry point. The location pointed by it should be 1570accessible from BL1 while processing the synchronous exception to run to BL31. 1571 1572In Arm standard platforms this is allocated inside a bl2\_to\_bl31\_params\_mem 1573structure in BL2 memory. 1574 1575Function : bl2\_plat\_set\_bl31\_ep\_info() [mandatory] 1576~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1577 1578:: 1579 1580 Argument : image_info *, entry_point_info * 1581 Return : void 1582 1583In the normal boot flow, this function is called after loading BL31 image and 1584it can be used to overwrite the entry point set by loader and also set the 1585security state and SPSR which represents the entry point system state for BL31. 1586 1587When booting an EL3 payload instead, this function is called after populating 1588its entry point address and can be used for the same purpose for the payload 1589image. It receives a null pointer as its first argument in this case. 1590 1591Function : bl2\_plat\_set\_bl32\_ep\_info() [mandatory] 1592~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1593 1594:: 1595 1596 Argument : image_info *, entry_point_info * 1597 Return : void 1598 1599This function is called after loading BL32 image and it can be used to 1600overwrite the entry point set by loader and also set the security state 1601and SPSR which represents the entry point system state for BL32. 1602 1603Function : bl2\_plat\_set\_bl33\_ep\_info() [mandatory] 1604~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1605 1606:: 1607 1608 Argument : image_info *, entry_point_info * 1609 Return : void 1610 1611This function is called after loading BL33 image and it can be used to 1612overwrite the entry point set by loader and also set the security state 1613and SPSR which represents the entry point system state for BL33. 1614 1615In the preloaded BL33 alternative boot flow, this function is called after 1616populating its entry point address. It is passed a null pointer as its first 1617argument in this case. 1618 1619Function : bl2\_plat\_get\_bl32\_meminfo() [mandatory] 1620~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1621 1622:: 1623 1624 Argument : meminfo * 1625 Return : void 1626 1627This function is used to get the memory limits where BL2 can load the 1628BL32 image. The meminfo provided by this is used by load\_image() to 1629validate whether the BL32 image can be loaded with in the given 1630memory from the given base. 1631 1632Function : bl2\_plat\_get\_bl33\_meminfo() [mandatory] 1633~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1634 1635:: 1636 1637 Argument : meminfo * 1638 Return : void 1639 1640This function is used to get the memory limits where BL2 can load the 1641BL33 image. The meminfo provided by this is used by load\_image() to 1642validate whether the BL33 image can be loaded with in the given 1643memory from the given base. 1644 1645This function isn't needed if either ``PRELOADED_BL33_BASE`` or ``EL3_PAYLOAD_BASE`` 1646build options are used. 1647 1648Function : bl2\_plat\_flush\_bl31\_params() [mandatory] 1649~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1650 1651:: 1652 1653 Argument : void 1654 Return : void 1655 1656Once BL2 has populated all the structures that needs to be read by BL1 1657and BL31 including the bl31\_params structures and its sub-structures, 1658the bl31\_ep\_info structure and any platform specific data. It flushes 1659all these data to the main memory so that it is available when we jump to 1660later Bootloader stages with MMU off 1661 1662Function : plat\_get\_ns\_image\_entrypoint() [mandatory] 1663~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1664 1665:: 1666 1667 Argument : void 1668 Return : uintptr_t 1669 1670As previously described, BL2 is responsible for arranging for control to be 1671passed to a normal world BL image through BL31. This function returns the 1672entrypoint of that image, which BL31 uses to jump to it. 1673 1674BL2 is responsible for loading the normal world BL33 image (e.g. UEFI). 1675 1676This function isn't needed if either ``PRELOADED_BL33_BASE`` or ``EL3_PAYLOAD_BASE`` 1677build options are used. 1678 1679Function : bl2\_plat\_preload\_setup [optional] 1680~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1681 1682:: 1683 1684 Argument : void 1685 Return : void 1686 1687This optional function performs any BL2 platform initialization 1688required before image loading, that is not done later in 1689bl2\_platform\_setup(). Specifically, if support for multiple 1690boot sources is required, it initializes the boot sequence used by 1691plat\_try\_next\_boot\_source(). 1692 1693Function : plat\_try\_next\_boot\_source() [optional] 1694~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1695 1696:: 1697 1698 Argument : void 1699 Return : int 1700 1701This optional function passes to the next boot source in the redundancy 1702sequence. 1703 1704This function moves the current boot redundancy source to the next 1705element in the boot sequence. If there are no more boot sources then it 1706must return 0, otherwise it must return 1. The default implementation 1707of this always returns 0. 1708 1709Boot Loader Stage 2 (BL2) at EL3 1710-------------------------------- 1711 1712When the platform has a non-TF-A Boot ROM it is desirable to jump 1713directly to BL2 instead of TF-A BL1. In this case BL2 is expected to 1714execute at EL3 instead of executing at EL1. Refer to the `Firmware 1715Design`_ for more information. 1716 1717All mandatory functions of BL2 must be implemented, except the functions 1718bl2\_early\_platform\_setup and bl2\_el3\_plat\_arch\_setup, because 1719their work is done now by bl2\_el3\_early\_platform\_setup and 1720bl2\_el3\_plat\_arch\_setup. These functions should generally implement 1721the bl1\_plat\_xxx() and bl2\_plat\_xxx() functionality combined. 1722 1723 1724Function : bl2\_el3\_early\_platform\_setup() [mandatory] 1725~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1726 1727:: 1728 1729 Argument : u_register_t, u_register_t, u_register_t, u_register_t 1730 Return : void 1731 1732This function executes with the MMU and data caches disabled. It is only called 1733by the primary CPU. This function receives four parameters which can be used 1734by the platform to pass any needed information from the Boot ROM to BL2. 1735 1736On Arm standard platforms, this function does the following: 1737 1738- Initializes a UART (PL011 console), which enables access to the ``printf`` 1739 family of functions in BL2. 1740 1741- Initializes the storage abstraction layer used to load further bootloader 1742 images. It is necessary to do this early on platforms with a SCP\_BL2 image, 1743 since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded. 1744 1745- Initializes the private variables that define the memory layout used. 1746 1747Function : bl2\_el3\_plat\_arch\_setup() [mandatory] 1748~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1749 1750:: 1751 1752 Argument : void 1753 Return : void 1754 1755This function executes with the MMU and data caches disabled. It is only called 1756by the primary CPU. 1757 1758The purpose of this function is to perform any architectural initialization 1759that varies across platforms. 1760 1761On Arm standard platforms, this function enables the MMU. 1762 1763Function : bl2\_el3\_plat\_prepare\_exit() [optional] 1764~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1765 1766:: 1767 1768 Argument : void 1769 Return : void 1770 1771This function is called prior to exiting BL2 and run the next image. 1772It should be used to perform platform specific clean up or bookkeeping 1773operations before transferring control to the next image. This function 1774runs with MMU disabled. 1775 1776FWU Boot Loader Stage 2 (BL2U) 1777------------------------------ 1778 1779The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU 1780process and is executed only by the primary CPU. BL1 passes control to BL2U at 1781``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: 1782 1783#. (Optional) Transfering the optional SCP\_BL2U binary image from AP secure 1784 memory to SCP RAM. BL2U uses the SCP\_BL2U ``image_info`` passed by BL1. 1785 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP\_BL2U 1786 should be copied from. Subsequent handling of the SCP\_BL2U image is 1787 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. 1788 If ``SCP_BL2U_BASE`` is not defined then this step is not performed. 1789 1790#. Any platform specific setup required to perform the FWU process. For 1791 example, Arm standard platforms initialize the TZC controller so that the 1792 normal world can access DDR memory. 1793 1794The following functions must be implemented by the platform port to enable 1795BL2U to perform the tasks mentioned above. 1796 1797Function : bl2u\_early\_platform\_setup() [mandatory] 1798~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1799 1800:: 1801 1802 Argument : meminfo *mem_info, void *plat_info 1803 Return : void 1804 1805This function executes with the MMU and data caches disabled. It is only 1806called by the primary CPU. The arguments to this function is the address 1807of the ``meminfo`` structure and platform specific info provided by BL1. 1808 1809The platform may copy the contents of the ``mem_info`` and ``plat_info`` into 1810private storage as the original memory may be subsequently overwritten by BL2U. 1811 1812On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, 1813to extract SCP\_BL2U image information, which is then copied into a private 1814variable. 1815 1816Function : bl2u\_plat\_arch\_setup() [mandatory] 1817~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1818 1819:: 1820 1821 Argument : void 1822 Return : void 1823 1824This function executes with the MMU and data caches disabled. It is only 1825called by the primary CPU. 1826 1827The purpose of this function is to perform any architectural initialization 1828that varies across platforms, for example enabling the MMU (since the memory 1829map differs across platforms). 1830 1831Function : bl2u\_platform\_setup() [mandatory] 1832~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1833 1834:: 1835 1836 Argument : void 1837 Return : void 1838 1839This function may execute with the MMU and data caches enabled if the platform 1840port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only 1841called by the primary CPU. 1842 1843The purpose of this function is to perform any platform initialization 1844specific to BL2U. 1845 1846In Arm standard platforms, this function performs security setup, including 1847configuration of the TrustZone controller to allow non-secure masters access 1848to most of DRAM. Part of DRAM is reserved for secure world use. 1849 1850Function : bl2u\_plat\_handle\_scp\_bl2u() [optional] 1851~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1852 1853:: 1854 1855 Argument : void 1856 Return : int 1857 1858This function is used to perform any platform-specific actions required to 1859handle the SCP firmware. Typically it transfers the image into SCP memory using 1860a platform-specific protocol and waits until SCP executes it and signals to the 1861Application Processor (AP) for BL2U execution to continue. 1862 1863This function returns 0 on success, a negative error code otherwise. 1864This function is included if SCP\_BL2U\_BASE is defined. 1865 1866Boot Loader Stage 3-1 (BL31) 1867---------------------------- 1868 1869During cold boot, the BL31 stage is executed only by the primary CPU. This is 1870determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes 1871control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all 1872CPUs. BL31 executes at EL3 and is responsible for: 1873 1874#. Re-initializing all architectural and platform state. Although BL1 performs 1875 some of this initialization, BL31 remains resident in EL3 and must ensure 1876 that EL3 architectural and platform state is completely initialized. It 1877 should make no assumptions about the system state when it receives control. 1878 1879#. Passing control to a normal world BL image, pre-loaded at a platform- 1880 specific address by BL2. BL31 uses the ``entry_point_info`` structure that BL2 1881 populated in memory to do this. 1882 1883#. Providing runtime firmware services. Currently, BL31 only implements a 1884 subset of the Power State Coordination Interface (PSCI) API as a runtime 1885 service. See Section 3.3 below for details of porting the PSCI 1886 implementation. 1887 1888#. Optionally passing control to the BL32 image, pre-loaded at a platform- 1889 specific address by BL2. BL31 exports a set of apis that allow runtime 1890 services to specify the security state in which the next image should be 1891 executed and run the corresponding image. BL31 uses the ``entry_point_info`` 1892 structure populated by BL2 to do this. 1893 1894If BL31 is a reset vector, It also needs to handle the reset as specified in 1895section 2.2 before the tasks described above. 1896 1897The following functions must be implemented by the platform port to enable BL31 1898to perform the above tasks. 1899 1900Function : bl31\_early\_platform\_setup() [mandatory] 1901~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1902 1903:: 1904 1905 Argument : bl31_params *, void * 1906 Return : void 1907 1908This function executes with the MMU and data caches disabled. It is only called 1909by the primary CPU. The arguments to this function are: 1910 1911- The address of the ``bl31_params`` structure populated by BL2. 1912- An opaque pointer that the platform may use as needed. 1913 1914The platform can copy the contents of the ``bl31_params`` structure and its 1915sub-structures into private variables if the original memory may be 1916subsequently overwritten by BL31 and similarly the ``void *`` pointing 1917to the platform data also needs to be saved. 1918 1919In Arm standard platforms, BL2 passes a pointer to a ``bl31_params`` structure 1920in BL2 memory. BL31 copies the information in this pointer to internal data 1921structures. It also performs the following: 1922 1923- Initialize a UART (PL011 console), which enables access to the ``printf`` 1924 family of functions in BL31. 1925 1926- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the 1927 CCI slave interface corresponding to the cluster that includes the primary 1928 CPU. 1929 1930Function : bl31\_plat\_arch\_setup() [mandatory] 1931~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1932 1933:: 1934 1935 Argument : void 1936 Return : void 1937 1938This function executes with the MMU and data caches disabled. It is only called 1939by the primary CPU. 1940 1941The purpose of this function is to perform any architectural initialization 1942that varies across platforms. 1943 1944On Arm standard platforms, this function enables the MMU. 1945 1946Function : bl31\_platform\_setup() [mandatory] 1947~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1948 1949:: 1950 1951 Argument : void 1952 Return : void 1953 1954This function may execute with the MMU and data caches enabled if the platform 1955port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only 1956called by the primary CPU. 1957 1958The purpose of this function is to complete platform initialization so that both 1959BL31 runtime services and normal world software can function correctly. 1960 1961On Arm standard platforms, this function does the following: 1962 1963- Initialize the generic interrupt controller. 1964 1965 Depending on the GIC driver selected by the platform, the appropriate GICv2 1966 or GICv3 initialization will be done, which mainly consists of: 1967 1968 - Enable secure interrupts in the GIC CPU interface. 1969 - Disable the legacy interrupt bypass mechanism. 1970 - Configure the priority mask register to allow interrupts of all priorities 1971 to be signaled to the CPU interface. 1972 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. 1973 - Target all secure SPIs to CPU0. 1974 - Enable these secure interrupts in the GIC distributor. 1975 - Configure all other interrupts as non-secure. 1976 - Enable signaling of secure interrupts in the GIC distributor. 1977 1978- Enable system-level implementation of the generic timer counter through the 1979 memory mapped interface. 1980 1981- Grant access to the system counter timer module 1982 1983- Initialize the power controller device. 1984 1985 In particular, initialise the locks that prevent concurrent accesses to the 1986 power controller device. 1987 1988Function : bl31\_plat\_runtime\_setup() [optional] 1989~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1990 1991:: 1992 1993 Argument : void 1994 Return : void 1995 1996The purpose of this function is allow the platform to perform any BL31 runtime 1997setup just prior to BL31 exit during cold boot. The default weak 1998implementation of this function will invoke ``console_switch_state()`` to switch 1999console output to consoles marked for use in the ``runtime`` state. 2000 2001Function : bl31\_plat\_get\_next\_image\_ep\_info() [mandatory] 2002~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2003 2004:: 2005 2006 Argument : uint32_t 2007 Return : entry_point_info * 2008 2009This function may execute with the MMU and data caches enabled if the platform 2010port does the necessary initializations in ``bl31_plat_arch_setup()``. 2011 2012This function is called by ``bl31_main()`` to retrieve information provided by 2013BL2 for the next image in the security state specified by the argument. BL31 2014uses this information to pass control to that image in the specified security 2015state. This function must return a pointer to the ``entry_point_info`` structure 2016(that was copied during ``bl31_early_platform_setup()``) if the image exists. It 2017should return NULL otherwise. 2018 2019Function : bl31_plat_enable_mmu [optional] 2020~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2021 2022:: 2023 2024 Argument : uint32_t 2025 Return : void 2026 2027This function enables the MMU. The boot code calls this function with MMU and 2028caches disabled. This function should program necessary registers to enable 2029translation, and upon return, the MMU on the calling PE must be enabled. 2030 2031The function must honor flags passed in the first argument. These flags are 2032defined by the translation library, and can be found in the file 2033``include/lib/xlat_tables/xlat_mmu_helpers.h``. 2034 2035On DynamIQ systems, this function must not use stack while enabling MMU, which 2036is how the function in xlat table library version 2 is implementated. 2037 2038Function : plat\_get\_syscnt\_freq2() [mandatory] 2039~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2040 2041:: 2042 2043 Argument : void 2044 Return : unsigned int 2045 2046This function is used by the architecture setup code to retrieve the counter 2047frequency for the CPU's generic timer. This value will be programmed into the 2048``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency 2049of the system counter, which is retrieved from the first entry in the frequency 2050modes table. 2051 2052#define : PLAT\_PERCPU\_BAKERY\_LOCK\_SIZE [optional] 2053~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2054 2055When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in 2056bytes) aligned to the cache line boundary that should be allocated per-cpu to 2057accommodate all the bakery locks. 2058 2059If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker 2060calculates the size of the ``bakery_lock`` input section, aligns it to the 2061nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` 2062and stores the result in a linker symbol. This constant prevents a platform 2063from relying on the linker and provide a more efficient mechanism for 2064accessing per-cpu bakery lock information. 2065 2066If this constant is defined and its value is not equal to the value 2067calculated by the linker then a link time assertion is raised. A compile time 2068assertion is raised if the value of the constant is not aligned to the cache 2069line boundary. 2070 2071SDEI porting requirements 2072~~~~~~~~~~~~~~~~~~~~~~~~~ 2073 2074The SDEI dispatcher requires the platform to provide the following macros 2075and functions, of which some are optional, and some others mandatory. 2076 2077Macros 2078...... 2079 2080Macro: PLAT_SDEI_NORMAL_PRI [mandatory] 2081^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2082 2083This macro must be defined to the EL3 exception priority level associated with 2084Normal SDEI events on the platform. This must have a higher value (therefore of 2085lower priority) than ``PLAT_SDEI_CRITICAL_PRI``. 2086 2087Macro: PLAT_SDEI_CRITICAL_PRI [mandatory] 2088^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2089 2090This macro must be defined to the EL3 exception priority level associated with 2091Critical SDEI events on the platform. This must have a lower value (therefore of 2092higher priority) than ``PLAT_SDEI_NORMAL_PRI``. 2093 2094**Note**: SDEI exception priorities must be the lowest among Secure priorities. 2095Among the SDEI exceptions, Critical SDEI priority must be higher than Normal 2096SDEI priority. 2097 2098Functions 2099......... 2100 2101Function: int plat_sdei_validate_entry_point(uintptr_t ep) [optional] 2102^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2103 2104:: 2105 2106 Argument: uintptr_t 2107 Return: int 2108 2109This function validates the address of client entry points provided for both 2110event registration and *Complete and Resume* SDEI calls. The function takes one 2111argument, which is the address of the handler the SDEI client requested to 2112register. The function must return ``0`` for successful validation, or ``-1`` 2113upon failure. 2114 2115The default implementation always returns ``0``. On Arm platforms, this function 2116is implemented to translate the entry point to physical address, and further to 2117ensure that the address is located in Non-secure DRAM. 2118 2119Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional] 2120^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 2121 2122:: 2123 2124 Argument: uint64_t 2125 Argument: unsigned int 2126 Return: void 2127 2128SDEI specification requires that a PE comes out of reset with the events masked. 2129The client therefore is expected to call ``PE_UNMASK`` to unmask SDEI events on 2130the PE. No SDEI events can be dispatched until such time. 2131 2132Should a PE receive an interrupt that was bound to an SDEI event while the 2133events are masked on the PE, the dispatcher implementation invokes the function 2134``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the 2135interrupt and the interrupt ID are passed as parameters. 2136 2137The default implementation only prints out a warning message. 2138 2139Power State Coordination Interface (in BL31) 2140-------------------------------------------- 2141 2142The TF-A implementation of the PSCI API is based around the concept of a 2143*power domain*. A *power domain* is a CPU or a logical group of CPUs which 2144share some state on which power management operations can be performed as 2145specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is 2146a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The 2147*power domains* are arranged in a hierarchical tree structure and each 2148*power domain* can be identified in a system by the cpu index of any CPU that 2149is part of that domain and a *power domain level*. A processing element (for 2150example, a CPU) is at level 0. If the *power domain* node above a CPU is a 2151logical grouping of CPUs that share some state, then level 1 is that group of 2152CPUs (for example, a cluster), and level 2 is a group of clusters (for 2153example, the system). More details on the power domain topology and its 2154organization can be found in `Power Domain Topology Design`_. 2155 2156BL31's platform initialization code exports a pointer to the platform-specific 2157power management operations required for the PSCI implementation to function 2158correctly. This information is populated in the ``plat_psci_ops`` structure. The 2159PSCI implementation calls members of the ``plat_psci_ops`` structure for performing 2160power management operations on the power domains. For example, the target 2161CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` 2162handler (if present) is called for the CPU power domain. 2163 2164The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to 2165describe composite power states specific to a platform. The PSCI implementation 2166defines a generic representation of the power-state parameter viz which is an 2167array of local power states where each index corresponds to a power domain 2168level. Each entry contains the local power state the power domain at that power 2169level could enter. It depends on the ``validate_power_state()`` handler to 2170convert the power-state parameter (possibly encoding a composite power state) 2171passed in a PSCI ``CPU_SUSPEND`` call to this representation. 2172 2173The following functions form part of platform port of PSCI functionality. 2174 2175Function : plat\_psci\_stat\_accounting\_start() [optional] 2176~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2177 2178:: 2179 2180 Argument : const psci_power_state_t * 2181 Return : void 2182 2183This is an optional hook that platforms can implement for residency statistics 2184accounting before entering a low power state. The ``pwr_domain_state`` field of 2185``state_info`` (first argument) can be inspected if stat accounting is done 2186differently at CPU level versus higher levels. As an example, if the element at 2187index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2188state, special hardware logic may be programmed in order to keep track of the 2189residency statistics. For higher levels (array indices > 0), the residency 2190statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2191default implementation will use PMF to capture timestamps. 2192 2193Function : plat\_psci\_stat\_accounting\_stop() [optional] 2194~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2195 2196:: 2197 2198 Argument : const psci_power_state_t * 2199 Return : void 2200 2201This is an optional hook that platforms can implement for residency statistics 2202accounting after exiting from a low power state. The ``pwr_domain_state`` field 2203of ``state_info`` (first argument) can be inspected if stat accounting is done 2204differently at CPU level versus higher levels. As an example, if the element at 2205index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down 2206state, special hardware logic may be programmed in order to keep track of the 2207residency statistics. For higher levels (array indices > 0), the residency 2208statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the 2209default implementation will use PMF to capture timestamps. 2210 2211Function : plat\_psci\_stat\_get\_residency() [optional] 2212~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2213 2214:: 2215 2216 Argument : unsigned int, const psci_power_state_t *, int 2217 Return : u_register_t 2218 2219This is an optional interface that is is invoked after resuming from a low power 2220state and provides the time spent resident in that low power state by the power 2221domain at a particular power domain level. When a CPU wakes up from suspend, 2222all its parent power domain levels are also woken up. The generic PSCI code 2223invokes this function for each parent power domain that is resumed and it 2224identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second 2225argument) describes the low power state that the power domain has resumed from. 2226The current CPU is the first CPU in the power domain to resume from the low 2227power state and the ``last_cpu_idx`` (third parameter) is the index of the last 2228CPU in the power domain to suspend and may be needed to calculate the residency 2229for that power domain. 2230 2231Function : plat\_get\_target\_pwr\_state() [optional] 2232~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2233 2234:: 2235 2236 Argument : unsigned int, const plat_local_state_t *, unsigned int 2237 Return : plat_local_state_t 2238 2239The PSCI generic code uses this function to let the platform participate in 2240state coordination during a power management operation. The function is passed 2241a pointer to an array of platform specific local power state ``states`` (second 2242argument) which contains the requested power state for each CPU at a particular 2243power domain level ``lvl`` (first argument) within the power domain. The function 2244is expected to traverse this array of upto ``ncpus`` (third argument) and return 2245a coordinated target power state by the comparing all the requested power 2246states. The target power state should not be deeper than any of the requested 2247power states. 2248 2249A weak definition of this API is provided by default wherein it assumes 2250that the platform assigns a local state value in order of increasing depth 2251of the power state i.e. for two power states X & Y, if X < Y 2252then X represents a shallower power state than Y. As a result, the 2253coordinated target local power state for a power domain will be the minimum 2254of the requested local power state values. 2255 2256Function : plat\_get\_power\_domain\_tree\_desc() [mandatory] 2257~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2258 2259:: 2260 2261 Argument : void 2262 Return : const unsigned char * 2263 2264This function returns a pointer to the byte array containing the power domain 2265topology tree description. The format and method to construct this array are 2266described in `Power Domain Topology Design`_. The BL31 PSCI initilization code 2267requires this array to be described by the platform, either statically or 2268dynamically, to initialize the power domain topology tree. In case the array 2269is populated dynamically, then plat\_core\_pos\_by\_mpidr() and 2270plat\_my\_core\_pos() should also be implemented suitably so that the topology 2271tree description matches the CPU indices returned by these APIs. These APIs 2272together form the platform interface for the PSCI topology framework. 2273 2274Function : plat\_setup\_psci\_ops() [mandatory] 2275~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2276 2277:: 2278 2279 Argument : uintptr_t, const plat_psci_ops ** 2280 Return : int 2281 2282This function may execute with the MMU and data caches enabled if the platform 2283port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only 2284called by the primary CPU. 2285 2286This function is called by PSCI initialization code. Its purpose is to let 2287the platform layer know about the warm boot entrypoint through the 2288``sec_entrypoint`` (first argument) and to export handler routines for 2289platform-specific psci power management actions by populating the passed 2290pointer with a pointer to BL31's private ``plat_psci_ops`` structure. 2291 2292A description of each member of this structure is given below. Please refer to 2293the Arm FVP specific implementation of these handlers in 2294`plat/arm/board/fvp/fvp\_pm.c`_ as an example. For each PSCI function that the 2295platform wants to support, the associated operation or operations in this 2296structure must be provided and implemented (Refer section 4 of 2297`Firmware Design`_ for the PSCI API supported in TF-A). To disable a PSCI 2298function in a platform port, the operation should be removed from this 2299structure instead of providing an empty implementation. 2300 2301plat\_psci\_ops.cpu\_standby() 2302.............................. 2303 2304Perform the platform-specific actions to enter the standby state for a cpu 2305indicated by the passed argument. This provides a fast path for CPU standby 2306wherein overheads of PSCI state management and lock acquistion is avoided. 2307For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, 2308the suspend state type specified in the ``power-state`` parameter should be 2309STANDBY and the target power domain level specified should be the CPU. The 2310handler should put the CPU into a low power retention state (usually by 2311issuing a wfi instruction) and ensure that it can be woken up from that 2312state by a normal interrupt. The generic code expects the handler to succeed. 2313 2314plat\_psci\_ops.pwr\_domain\_on() 2315................................. 2316 2317Perform the platform specific actions to power on a CPU, specified 2318by the ``MPIDR`` (first argument). The generic code expects the platform to 2319return PSCI\_E\_SUCCESS on success or PSCI\_E\_INTERN\_FAIL for any failure. 2320 2321plat\_psci\_ops.pwr\_domain\_off() 2322.................................. 2323 2324Perform the platform specific actions to prepare to power off the calling CPU 2325and its higher parent power domain levels as indicated by the ``target_state`` 2326(first argument). It is called by the PSCI ``CPU_OFF`` API implementation. 2327 2328The ``target_state`` encodes the platform coordinated target local power states 2329for the CPU power domain and its parent power domain levels. The handler 2330needs to perform power management operation corresponding to the local state 2331at each power level. 2332 2333For this handler, the local power state for the CPU power domain will be a 2334power down state where as it could be either power down, retention or run state 2335for the higher power domain levels depending on the result of state 2336coordination. The generic code expects the handler to succeed. 2337 2338plat\_psci\_ops.pwr\_domain\_suspend\_pwrdown\_early() [optional] 2339................................................................. 2340 2341This optional function may be used as a performance optimization to replace 2342or complement pwr_domain_suspend() on some platforms. Its calling semantics 2343are identical to pwr_domain_suspend(), except the PSCI implementation only 2344calls this function when suspending to a power down state, and it guarantees 2345that data caches are enabled. 2346 2347When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches 2348before calling pwr_domain_suspend(). If the target_state corresponds to a 2349power down state and it is safe to perform some or all of the platform 2350specific actions in that function with data caches enabled, it may be more 2351efficient to move those actions to this function. When HW_ASSISTED_COHERENCY 2352= 1, data caches remain enabled throughout, and so there is no advantage to 2353moving platform specific actions to this function. 2354 2355plat\_psci\_ops.pwr\_domain\_suspend() 2356...................................... 2357 2358Perform the platform specific actions to prepare to suspend the calling 2359CPU and its higher parent power domain levels as indicated by the 2360``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` 2361API implementation. 2362 2363The ``target_state`` has a similar meaning as described in 2364the ``pwr_domain_off()`` operation. It encodes the platform coordinated 2365target local power states for the CPU power domain and its parent 2366power domain levels. The handler needs to perform power management operation 2367corresponding to the local state at each power level. The generic code 2368expects the handler to succeed. 2369 2370The difference between turning a power domain off versus suspending it is that 2371in the former case, the power domain is expected to re-initialize its state 2372when it is next powered on (see ``pwr_domain_on_finish()``). In the latter 2373case, the power domain is expected to save enough state so that it can resume 2374execution by restoring this state when its powered on (see 2375``pwr_domain_suspend_finish()``). 2376 2377When suspending a core, the platform can also choose to power off the GICv3 2378Redistributor and ITS through an implementation-defined sequence. To achieve 2379this safely, the ITS context must be saved first. The architectural part is 2380implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed 2381sequence is implementation defined and it is therefore the responsibility of 2382the platform code to implement the necessary sequence. Then the GIC 2383Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper. 2384Powering off the Redistributor requires the implementation to support it and it 2385is the responsibility of the platform code to execute the right implementation 2386defined sequence. 2387 2388When a system suspend is requested, the platform can also make use of the 2389``gicv3_distif_save()`` helper to save the context of the GIC Distributor after 2390it has saved the context of the Redistributors and ITS of all the cores in the 2391system. The context of the Distributor can be large and may require it to be 2392allocated in a special area if it cannot fit in the platform's global static 2393data, for example in DRAM. The Distributor can then be powered down using an 2394implementation-defined sequence. 2395 2396plat\_psci\_ops.pwr\_domain\_pwr\_down\_wfi() 2397............................................. 2398 2399This is an optional function and, if implemented, is expected to perform 2400platform specific actions including the ``wfi`` invocation which allows the 2401CPU to powerdown. Since this function is invoked outside the PSCI locks, 2402the actions performed in this hook must be local to the CPU or the platform 2403must ensure that races between multiple CPUs cannot occur. 2404 2405The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` 2406operation and it encodes the platform coordinated target local power states for 2407the CPU power domain and its parent power domain levels. This function must 2408not return back to the caller. 2409 2410If this function is not implemented by the platform, PSCI generic 2411implementation invokes ``psci_power_down_wfi()`` for power down. 2412 2413plat\_psci\_ops.pwr\_domain\_on\_finish() 2414......................................... 2415 2416This function is called by the PSCI implementation after the calling CPU is 2417powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. 2418It performs the platform-specific setup required to initialize enough state for 2419this CPU to enter the normal world and also provide secure runtime firmware 2420services. 2421 2422The ``target_state`` (first argument) is the prior state of the power domains 2423immediately before the CPU was turned on. It indicates which power domains 2424above the CPU might require initialization due to having previously been in 2425low power states. The generic code expects the handler to succeed. 2426 2427plat\_psci\_ops.pwr\_domain\_suspend\_finish() 2428.............................................. 2429 2430This function is called by the PSCI implementation after the calling CPU is 2431powered on and released from reset in response to an asynchronous wakeup 2432event, for example a timer interrupt that was programmed by the CPU during the 2433``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific 2434setup required to restore the saved state for this CPU to resume execution 2435in the normal world and also provide secure runtime firmware services. 2436 2437The ``target_state`` (first argument) has a similar meaning as described in 2438the ``pwr_domain_on_finish()`` operation. The generic code expects the platform 2439to succeed. 2440 2441If the Distributor, Redistributors or ITS have been powered off as part of a 2442suspend, their context must be restored in this function in the reverse order 2443to how they were saved during suspend sequence. 2444 2445plat\_psci\_ops.system\_off() 2446............................. 2447 2448This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` 2449call. It performs the platform-specific system poweroff sequence after 2450notifying the Secure Payload Dispatcher. 2451 2452plat\_psci\_ops.system\_reset() 2453............................... 2454 2455This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` 2456call. It performs the platform-specific system reset sequence after 2457notifying the Secure Payload Dispatcher. 2458 2459plat\_psci\_ops.validate\_power\_state() 2460........................................ 2461 2462This function is called by the PSCI implementation during the ``CPU_SUSPEND`` 2463call to validate the ``power_state`` parameter of the PSCI API and if valid, 2464populate it in ``req_state`` (second argument) array as power domain level 2465specific local states. If the ``power_state`` is invalid, the platform must 2466return PSCI\_E\_INVALID\_PARAMS as error, which is propagated back to the 2467normal world PSCI client. 2468 2469plat\_psci\_ops.validate\_ns\_entrypoint() 2470.......................................... 2471 2472This function is called by the PSCI implementation during the ``CPU_SUSPEND``, 2473``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` 2474parameter passed by the normal world. If the ``entry_point`` is invalid, 2475the platform must return PSCI\_E\_INVALID\_ADDRESS as error, which is 2476propagated back to the normal world PSCI client. 2477 2478plat\_psci\_ops.get\_sys\_suspend\_power\_state() 2479................................................. 2480 2481This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` 2482call to get the ``req_state`` parameter from platform which encodes the power 2483domain level specific local states to suspend to system affinity level. The 2484``req_state`` will be utilized to do the PSCI state coordination and 2485``pwr_domain_suspend()`` will be invoked with the coordinated target state to 2486enter system suspend. 2487 2488plat\_psci\_ops.get\_pwr\_lvl\_state\_idx() 2489........................................... 2490 2491This is an optional function and, if implemented, is invoked by the PSCI 2492implementation to convert the ``local_state`` (first argument) at a specified 2493``pwr_lvl`` (second argument) to an index between 0 and 2494``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform 2495supports more than two local power states at each power domain level, that is 2496``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these 2497local power states. 2498 2499plat\_psci\_ops.translate\_power\_state\_by\_mpidr() 2500.................................................... 2501 2502This is an optional function and, if implemented, verifies the ``power_state`` 2503(second argument) parameter of the PSCI API corresponding to a target power 2504domain. The target power domain is identified by using both ``MPIDR`` (first 2505argument) and the power domain level encoded in ``power_state``. The power domain 2506level specific local states are to be extracted from ``power_state`` and be 2507populated in the ``output_state`` (third argument) array. The functionality 2508is similar to the ``validate_power_state`` function described above and is 2509envisaged to be used in case the validity of ``power_state`` depend on the 2510targeted power domain. If the ``power_state`` is invalid for the targeted power 2511domain, the platform must return PSCI\_E\_INVALID\_PARAMS as error. If this 2512function is not implemented, then the generic implementation relies on 2513``validate_power_state`` function to translate the ``power_state``. 2514 2515This function can also be used in case the platform wants to support local 2516power state encoding for ``power_state`` parameter of PSCI\_STAT\_COUNT/RESIDENCY 2517APIs as described in Section 5.18 of `PSCI`_. 2518 2519plat\_psci\_ops.get\_node\_hw\_state() 2520...................................... 2521 2522This is an optional function. If implemented this function is intended to return 2523the power state of a node (identified by the first parameter, the ``MPIDR``) in 2524the power domain topology (identified by the second parameter, ``power_level``), 2525as retrieved from a power controller or equivalent component on the platform. 2526Upon successful completion, the implementation must map and return the final 2527status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it 2528must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as 2529appropriate. 2530 2531Implementations are not expected to handle ``power_levels`` greater than 2532``PLAT_MAX_PWR_LVL``. 2533 2534plat\_psci\_ops.system\_reset2() 2535................................ 2536 2537This is an optional function. If implemented this function is 2538called during the ``SYSTEM_RESET2`` call to perform a reset 2539based on the first parameter ``reset_type`` as specified in 2540`PSCI`_. The parameter ``cookie`` can be used to pass additional 2541reset information. If the ``reset_type`` is not supported, the 2542function must return ``PSCI_E_NOT_SUPPORTED``. For architectural 2543resets, all failures must return ``PSCI_E_INVALID_PARAMETERS`` 2544and vendor reset can return other PSCI error codes as defined 2545in `PSCI`_. On success this function will not return. 2546 2547plat\_psci\_ops.write\_mem\_protect() 2548.................................... 2549 2550This is an optional function. If implemented it enables or disables the 2551``MEM_PROTECT`` functionality based on the value of ``val``. 2552A non-zero value enables ``MEM_PROTECT`` and a value of zero 2553disables it. Upon encountering failures it must return a negative value 2554and on success it must return 0. 2555 2556plat\_psci\_ops.read\_mem\_protect() 2557..................................... 2558 2559This is an optional function. If implemented it returns the current 2560state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering 2561failures it must return a negative value and on success it must 2562return 0. 2563 2564plat\_psci\_ops.mem\_protect\_chk() 2565................................... 2566 2567This is an optional function. If implemented it checks if a memory 2568region defined by a base address ``base`` and with a size of ``length`` 2569bytes is protected by ``MEM_PROTECT``. If the region is protected 2570then it must return 0, otherwise it must return a negative number. 2571 2572Interrupt Management framework (in BL31) 2573---------------------------------------- 2574 2575BL31 implements an Interrupt Management Framework (IMF) to manage interrupts 2576generated in either security state and targeted to EL1 or EL2 in the non-secure 2577state or EL3/S-EL1 in the secure state. The design of this framework is 2578described in the `IMF Design Guide`_ 2579 2580A platform should export the following APIs to support the IMF. The following 2581text briefly describes each api and its implementation in Arm standard 2582platforms. The API implementation depends upon the type of interrupt controller 2583present in the platform. Arm standard platform layer supports both 2584`Arm Generic Interrupt Controller version 2.0 (GICv2)`_ 2585and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the 2586FVP can be configured to use either GICv2 or GICv3 depending on the build flag 2587``FVP_USE_GIC_DRIVER`` (See FVP platform specific build options in 2588`User Guide`_ for more details). 2589 2590See also: `Interrupt Controller Abstraction APIs`__. 2591 2592.. __: platform-interrupt-controller-API.rst 2593 2594Function : plat\_interrupt\_type\_to\_line() [mandatory] 2595~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2596 2597:: 2598 2599 Argument : uint32_t, uint32_t 2600 Return : uint32_t 2601 2602The Arm processor signals an interrupt exception either through the IRQ or FIQ 2603interrupt line. The specific line that is signaled depends on how the interrupt 2604controller (IC) reports different interrupt types from an execution context in 2605either security state. The IMF uses this API to determine which interrupt line 2606the platform IC uses to signal each type of interrupt supported by the framework 2607from a given security state. This API must be invoked at EL3. 2608 2609The first parameter will be one of the ``INTR_TYPE_*`` values (see 2610`IMF Design Guide`_) indicating the target type of the interrupt, the second parameter is the 2611security state of the originating execution context. The return result is the 2612bit position in the ``SCR_EL3`` register of the respective interrupt trap: IRQ=1, 2613FIQ=2. 2614 2615In the case of Arm standard platforms using GICv2, S-EL1 interrupts are 2616configured as FIQs and Non-secure interrupts as IRQs from either security 2617state. 2618 2619In the case of Arm standard platforms using GICv3, the interrupt line to be 2620configured depends on the security state of the execution context when the 2621interrupt is signalled and are as follows: 2622 2623- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in 2624 NS-EL0/1/2 context. 2625- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ 2626 in the NS-EL0/1/2 context. 2627- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 2628 context. 2629 2630Function : plat\_ic\_get\_pending\_interrupt\_type() [mandatory] 2631~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2632 2633:: 2634 2635 Argument : void 2636 Return : uint32_t 2637 2638This API returns the type of the highest priority pending interrupt at the 2639platform IC. The IMF uses the interrupt type to retrieve the corresponding 2640handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt 2641pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, 2642``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. 2643 2644In the case of Arm standard platforms using GICv2, the *Highest Priority 2645Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of 2646the pending interrupt. The type of interrupt depends upon the id value as 2647follows. 2648 2649#. id < 1022 is reported as a S-EL1 interrupt 2650#. id = 1022 is reported as a Non-secure interrupt. 2651#. id = 1023 is reported as an invalid interrupt type. 2652 2653In the case of Arm standard platforms using GICv3, the system register 2654``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, 2655is read to determine the id of the pending interrupt. The type of interrupt 2656depends upon the id value as follows. 2657 2658#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt 2659#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. 2660#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. 2661#. All other interrupt id's are reported as EL3 interrupt. 2662 2663Function : plat\_ic\_get\_pending\_interrupt\_id() [mandatory] 2664~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2665 2666:: 2667 2668 Argument : void 2669 Return : uint32_t 2670 2671This API returns the id of the highest priority pending interrupt at the 2672platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt 2673pending. 2674 2675In the case of Arm standard platforms using GICv2, the *Highest Priority 2676Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the 2677pending interrupt. The id that is returned by API depends upon the value of 2678the id read from the interrupt controller as follows. 2679 2680#. id < 1022. id is returned as is. 2681#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* 2682 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. 2683 This id is returned by the API. 2684#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. 2685 2686In the case of Arm standard platforms using GICv3, if the API is invoked from 2687EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt 2688group 0 Register*, is read to determine the id of the pending interrupt. The id 2689that is returned by API depends upon the value of the id read from the 2690interrupt controller as follows. 2691 2692#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. 2693#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system 2694 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 2695 Register* is read to determine the id of the group 1 interrupt. This id 2696 is returned by the API as long as it is a valid interrupt id 2697#. If the id is any of the special interrupt identifiers, 2698 ``INTR_ID_UNAVAILABLE`` is returned. 2699 2700When the API invoked from S-EL1 for GICv3 systems, the id read from system 2701register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt 2702Register*, is returned if is not equal to GIC\_SPURIOUS\_INTERRUPT (1023) else 2703``INTR_ID_UNAVAILABLE`` is returned. 2704 2705Function : plat\_ic\_acknowledge\_interrupt() [mandatory] 2706~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2707 2708:: 2709 2710 Argument : void 2711 Return : uint32_t 2712 2713This API is used by the CPU to indicate to the platform IC that processing of 2714the highest pending interrupt has begun. It should return the raw, unmodified 2715value obtained from the interrupt controller when acknowledging an interrupt. 2716The actual interrupt number shall be extracted from this raw value using the API 2717`plat_ic_get_interrupt_id()`__. 2718 2719.. __: platform-interrupt-controller-API.rst#function-unsigned-int-plat-ic-get-interrupt-id-unsigned-int-raw-optional 2720 2721This function in Arm standard platforms using GICv2, reads the *Interrupt 2722Acknowledge Register* (``GICC_IAR``). This changes the state of the highest 2723priority pending interrupt from pending to active in the interrupt controller. 2724It returns the value read from the ``GICC_IAR``, unmodified. 2725 2726In the case of Arm standard platforms using GICv3, if the API is invoked 2727from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt 2728Acknowledge Register group 0*. If the API is invoked from S-EL1, the function 2729reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register 2730group 1*. The read changes the state of the highest pending interrupt from 2731pending to active in the interrupt controller. The value read is returned 2732unmodified. 2733 2734The TSP uses this API to start processing of the secure physical timer 2735interrupt. 2736 2737Function : plat\_ic\_end\_of\_interrupt() [mandatory] 2738~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2739 2740:: 2741 2742 Argument : uint32_t 2743 Return : void 2744 2745This API is used by the CPU to indicate to the platform IC that processing of 2746the interrupt corresponding to the id (passed as the parameter) has 2747finished. The id should be the same as the id returned by the 2748``plat_ic_acknowledge_interrupt()`` API. 2749 2750Arm standard platforms write the id to the *End of Interrupt Register* 2751(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` 2752system register in case of GICv3 depending on where the API is invoked from, 2753EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt 2754controller. 2755 2756The TSP uses this API to finish processing of the secure physical timer 2757interrupt. 2758 2759Function : plat\_ic\_get\_interrupt\_type() [mandatory] 2760~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2761 2762:: 2763 2764 Argument : uint32_t 2765 Return : uint32_t 2766 2767This API returns the type of the interrupt id passed as the parameter. 2768``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid 2769interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is 2770returned depending upon how the interrupt has been configured by the platform 2771IC. This API must be invoked at EL3. 2772 2773Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts 2774and Non-secure interrupts as Group1 interrupts. It reads the group value 2775corresponding to the interrupt id from the relevant *Interrupt Group Register* 2776(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. 2777 2778In the case of Arm standard platforms using GICv3, both the *Interrupt Group 2779Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* 2780(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured 2781as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. 2782 2783Crash Reporting mechanism (in BL31) 2784----------------------------------- 2785 2786NOTE: This section assumes that your platform is enabling the MULTI_CONSOLE_API 2787flag in its platform.mk. Not using this flag is deprecated for new platforms. 2788 2789BL31 implements a crash reporting mechanism which prints the various registers 2790of the CPU to enable quick crash analysis and debugging. By default, the 2791definitions in ``plat/common/aarch64/platform\_helpers.S`` will cause the crash 2792output to be routed over the normal console infrastructure and get printed on 2793consoles configured to output in crash state. ``console_set_scope()`` can be 2794used to control whether a console is used for crash output. 2795 2796In some cases (such as debugging very early crashes that happen before the 2797normal boot console can be set up), platforms may want to control crash output 2798more explicitly. For these, the following functions can be overridden by 2799platform code. They are executed outside of a C environment and without a stack. 2800 2801Function : plat\_crash\_console\_init 2802~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2803 2804:: 2805 2806 Argument : void 2807 Return : int 2808 2809This API is used by the crash reporting mechanism to initialize the crash 2810console. It must only use the general purpose registers x0 through x7 to do the 2811initialization and returns 1 on success. 2812 2813If you are trying to debug crashes before the console driver would normally get 2814registered, you can use this to register a driver from assembly with hardcoded 2815parameters. For example, you could register the 16550 driver like this: 2816 2817:: 2818 2819 .section .data.crash_console /* Reserve space for console structure */ 2820 crash_console: 2821 .zero 6 * 8 /* console_16550_t has 6 8-byte words */ 2822 func plat_crash_console_init 2823 ldr x0, =YOUR_16550_BASE_ADDR 2824 ldr x1, =YOUR_16550_SRCCLK_IN_HZ 2825 ldr x2, =YOUR_16550_TARGET_BAUD_RATE 2826 adrp x3, crash_console 2827 add x3, x3, :lo12:crash_console 2828 b console_16550_register /* tail call, returns 1 on success */ 2829 endfunc plat_crash_console_init 2830 2831If you're trying to debug crashes in BL1, you can call the console_xxx_core_init 2832function exported by some console drivers from here. 2833 2834Function : plat\_crash\_console\_putc 2835~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2836 2837:: 2838 2839 Argument : int 2840 Return : int 2841 2842This API is used by the crash reporting mechanism to print a character on the 2843designated crash console. It must only use general purpose registers x1 and 2844x2 to do its work. The parameter and the return value are in general purpose 2845register x0. 2846 2847If you have registered a normal console driver in ``plat_crash_console_init``, 2848you can keep the default implementation here (which calls ``console_putc()``). 2849 2850If you're trying to debug crashes in BL1, you can call the console_xxx_core_putc 2851function exported by some console drivers from here. 2852 2853Function : plat\_crash\_console\_flush 2854~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2855 2856:: 2857 2858 Argument : void 2859 Return : int 2860 2861This API is used by the crash reporting mechanism to force write of all buffered 2862data on the designated crash console. It should only use general purpose 2863registers x0 through x5 to do its work. The return value is 0 on successful 2864completion; otherwise the return value is -1. 2865 2866If you have registered a normal console driver in ``plat_crash_console_init``, 2867you can keep the default implementation here (which calls ``console_flush()``). 2868 2869If you're trying to debug crashes in BL1, you can call the console_xx_core_flush 2870function exported by some console drivers from here. 2871 2872Extternal Abort handling and RAS Support 2873---------------------------------------- 2874 2875Function : plat_ea_handler 2876~~~~~~~~~~~~~~~~~~~~~~~~~~ 2877 2878:: 2879 2880 Argument : int 2881 Argument : uint64_t 2882 Argument : void * 2883 Argument : void * 2884 Argument : uint64_t 2885 Return : void 2886 2887This function is invoked by the RAS framework for the platform to handle an 2888External Abort received at EL3. The intention of the function is to attempt to 2889resolve the cause of External Abort and return; if that's not possible, to 2890initiate orderly shutdown of the system. 2891 2892The first parameter (``int ea_reason``) indicates the reason for External Abort. 2893Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``. 2894 2895The second parameter (``uint64_t syndrome``) is the respective syndrome 2896presented to EL3 after having received the External Abort. Depending on the 2897nature of the abort (as can be inferred from the ``ea_reason`` parameter), this 2898can be the content of either ``ESR_EL3`` or ``DISR_EL1``. 2899 2900The third parameter (``void *cookie``) is unused for now. The fourth parameter 2901(``void *handle``) is a pointer to the preempted context. The fifth parameter 2902(``uint64_t flags``) indicates the preempted security state. These parameters 2903are received from the top-level exception handler. 2904 2905If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this 2906function iterates through RAS handlers registered by the platform. If any of the 2907RAS handlers resolve the External Abort, no further action is taken. 2908 2909If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers 2910could resolve the External Abort, the default implementation prints an error 2911message, and panics. 2912 2913Function : plat_handle_uncontainable_ea 2914~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2915 2916:: 2917 2918 Argument : int 2919 Argument : uint64_t 2920 Return : void 2921 2922This function is invoked by the RAS framework when an External Abort of 2923Uncontainable type is received at EL3. Due to the critical nature of 2924Uncontainable errors, the intention of this function is to initiate orderly 2925shutdown of the system, and is not expected to return. 2926 2927This function must be implemented in assembly. 2928 2929The first and second parameters are the same as that of ``plat_ea_handler``. 2930 2931The default implementation of this function calls 2932``report_unhandled_exception``. 2933 2934Function : plat_handle_double_fault 2935~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2936 2937:: 2938 2939 Argument : int 2940 Argument : uint64_t 2941 Return : void 2942 2943This function is invoked by the RAS framework when another External Abort is 2944received at EL3 while one is already being handled. I.e., a call to 2945``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of 2946this function is to initiate orderly shutdown of the system, and is not expected 2947recover or return. 2948 2949This function must be implemented in assembly. 2950 2951The first and second parameters are the same as that of ``plat_ea_handler``. 2952 2953The default implementation of this function calls 2954``report_unhandled_exception``. 2955 2956Function : plat_handle_el3_ea 2957~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2958 2959:: 2960 2961 Return : void 2962 2963This function is invoked when an External Abort is received while executing in 2964EL3. Due to its critical nature, the intention of this function is to initiate 2965orderly shutdown of the system, and is not expected recover or return. 2966 2967This function must be implemented in assembly. 2968 2969The default implementation of this function calls 2970``report_unhandled_exception``. 2971 2972Build flags 2973----------- 2974 2975There are some build flags which can be defined by the platform to control 2976inclusion or exclusion of certain BL stages from the FIP image. These flags 2977need to be defined in the platform makefile which will get included by the 2978build system. 2979 2980- **NEED\_BL33** 2981 By default, this flag is defined ``yes`` by the build system and ``BL33`` 2982 build option should be supplied as a build option. The platform has the 2983 option of excluding the BL33 image in the ``fip`` image by defining this flag 2984 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` 2985 are used, this flag will be set to ``no`` automatically. 2986 2987C Library 2988--------- 2989 2990To avoid subtle toolchain behavioral dependencies, the header files provided 2991by the compiler are not used. The software is built with the ``-nostdinc`` flag 2992to ensure no headers are included from the toolchain inadvertently. Instead the 2993required headers are included in the TF-A source tree. The library only 2994contains those C library definitions required by the local implementation. If 2995more functionality is required, the needed library functions will need to be 2996added to the local implementation. 2997 2998Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have 2999been written specifically for TF-A. Fome implementation files have been obtained 3000from `FreeBSD`_, others have been written specifically for TF-A as well. The 3001files can be found in ``include/lib/libc`` and ``lib/libc``. 3002 3003SCC can be found in `http://www.simple-cc.org/`_. A copy of the `FreeBSD`_ 3004sources can be obtained from `http://github.com/freebsd/freebsd`_. 3005 3006Storage abstraction layer 3007------------------------- 3008 3009In order to improve platform independence and portability an storage abstraction 3010layer is used to load data from non-volatile platform storage. 3011 3012Each platform should register devices and their drivers via the Storage layer. 3013These drivers then need to be initialized by bootloader phases as 3014required in their respective ``blx_platform_setup()`` functions. Currently 3015storage access is only required by BL1 and BL2 phases. The ``load_image()`` 3016function uses the storage layer to access non-volatile platform storage. 3017 3018It is mandatory to implement at least one storage driver. For the Arm 3019development platforms the Firmware Image Package (FIP) driver is provided as 3020the default means to load data from storage (see the "Firmware Image Package" 3021section in the `User Guide`_). The storage layer is described in the header file 3022``include/drivers/io/io_storage.h``. The implementation of the common library 3023is in ``drivers/io/io_storage.c`` and the driver files are located in 3024``drivers/io/``. 3025 3026Each IO driver must provide ``io_dev_*`` structures, as described in 3027``drivers/io/io_driver.h``. These are returned via a mandatory registration 3028function that is called on platform initialization. The semi-hosting driver 3029implementation in ``io_semihosting.c`` can be used as an example. 3030 3031The Storage layer provides mechanisms to initialize storage devices before 3032IO operations are called. The basic operations supported by the layer 3033include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. 3034Drivers do not have to implement all operations, but each platform must 3035provide at least one driver for a device capable of supporting generic 3036operations such as loading a bootloader image. 3037 3038The current implementation only allows for known images to be loaded by the 3039firmware. These images are specified by using their identifiers, as defined in 3040[include/plat/common/platform\_def.h] (or a separate header file included from 3041there). The platform layer (``plat_get_image_source()``) then returns a reference 3042to a device and a driver-specific ``spec`` which will be understood by the driver 3043to allow access to the image data. 3044 3045The layer is designed in such a way that is it possible to chain drivers with 3046other drivers. For example, file-system drivers may be implemented on top of 3047physical block devices, both represented by IO devices with corresponding 3048drivers. In such a case, the file-system "binding" with the block device may 3049be deferred until the file-system device is initialised. 3050 3051The abstraction currently depends on structures being statically allocated 3052by the drivers and callers, as the system does not yet provide a means of 3053dynamically allocating memory. This may also have the affect of limiting the 3054amount of open resources per driver. 3055 3056-------------- 3057 3058*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.* 3059 3060.. _include/plat/common/platform.h: ../include/plat/common/platform.h 3061.. _include/plat/arm/common/plat\_arm.h: ../include/plat/arm/common/plat_arm.h%5D 3062.. _User Guide: user-guide.rst 3063.. _include/plat/common/common\_def.h: ../include/plat/common/common_def.h 3064.. _include/plat/arm/common/arm\_def.h: ../include/plat/arm/common/arm_def.h 3065.. _plat/common/aarch64/platform\_mp\_stack.S: ../plat/common/aarch64/platform_mp_stack.S 3066.. _plat/common/aarch64/platform\_up\_stack.S: ../plat/common/aarch64/platform_up_stack.S 3067.. _For example, define the build flag in platform.mk: PLAT_PL061_MAX_GPIOS%20:=%20160 3068.. _Power Domain Topology Design: psci-pd-tree.rst 3069.. _include/common/bl\_common.h: ../include/common/bl_common.h 3070.. _include/lib/aarch32/arch.h: ../include/lib/aarch32/arch.h 3071.. _Firmware Design: firmware-design.rst 3072.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf 3073.. _plat/arm/board/fvp/fvp\_pm.c: ../plat/arm/board/fvp/fvp_pm.c 3074.. _IMF Design Guide: interrupt-framework-design.rst 3075.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html 3076.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html 3077.. _FreeBSD: http://www.freebsd.org 3078.. _SCC: http://www.simple-cc.org/ 3079