| 68d13a2e | 25-May-2017 |
Krishna Sitaraman <ksitaraman@nvidia.com> |
Tegra194: Update checks for c-state stats
This patch adds proper checks for the cpu c-stats. It checks both
cpu id and stat id before sending the nvg request to ccplex.
Change-Id: I732957d1e10d6ce6
Tegra194: Update checks for c-state stats
This patch adds proper checks for the cpu c-stats. It checks both
cpu id and stat id before sending the nvg request to ccplex.
Change-Id: I732957d1e10d6ce6cffb2c6f5963ca614aadd948
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
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|
| 6907891d | 03-Aug-2017 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra194: smmu: fix mask for board revision id
Need to use bitwise & instead of condition &&.
Change-Id: I8f70aac95d116188ba972f3d38b02e1d3dd32acb
Signed-off-by: Pritesh Raithatha <praithatha@nvidi
Tegra194: smmu: fix mask for board revision id
Need to use bitwise & instead of condition &&.
Change-Id: I8f70aac95d116188ba972f3d38b02e1d3dd32acb
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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|
| 13dcbc6f | 25-Jul-2017 |
Steven Kao <skao@nvidia.com> |
Tegra194: smmu: ISO support
The FPGA configuration is encoded in the high byte of
MISCREG_EMU_REVID. Configs GPU and MAX (encoded as
2 and 3) support the ISO SMMU, while BASE (encoded as 1)
does not
Tegra194: smmu: ISO support
The FPGA configuration is encoded in the high byte of
MISCREG_EMU_REVID. Configs GPU and MAX (encoded as
2 and 3) support the ISO SMMU, while BASE (encoded as 1)
does not. This patch implements this encoding and returns
the proper number of SMMU instances.
Change-Id: I024286b6091120c7602f63065d20ce48bcfd13fe
Signed-off-by: Steven Kao <skao@nvidia.com>
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|
| b6e1109f | 11-Jul-2017 |
Vignesh Radhakrishnan <vigneshr@nvidia.com> |
Tegra194: Initialize smmu on system suspend exit
System suspend sequence involves initializing the SMMU
as a part of the system suspend exit, which is currently
not present for Tegra194 platform.
T
Tegra194: Initialize smmu on system suspend exit
System suspend sequence involves initializing the SMMU
as a part of the system suspend exit, which is currently
not present for Tegra194 platform.
Thus call tegra_smmu_init() as a part of system suspend
exit.
Change-Id: I3086301743019e05a40fd221372e7f8713f286ae
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
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|
| 79b65666 | 30-Jun-2017 |
Krishna Sitaraman <ksitaraman@nvidia.com> |
Tegra194: Update cpu core-id calculation
This patch updates the cpu core id calculation to match with
internal numbering method used by the MTS.
Change-Id: I5fbe9c8685c23017edc796e114d07c5e979e0d3d
Tegra194: Update cpu core-id calculation
This patch updates the cpu core id calculation to match with
internal numbering method used by the MTS.
Change-Id: I5fbe9c8685c23017edc796e114d07c5e979e0d3d
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
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|
| 2cd2e399 | 22-Jun-2017 |
Steven Kao <skao@nvidia.com> |
Tegra194: read-modify-write ACTLR_ELx registers
This patch changes direct writes to ACTLR_ELx registers to use
read-modify-write instead.
Change-Id: I536dce75c01356ce054dd2edee80875e56164439
Signed
Tegra194: read-modify-write ACTLR_ELx registers
This patch changes direct writes to ACTLR_ELx registers to use
read-modify-write instead.
Change-Id: I536dce75c01356ce054dd2edee80875e56164439
Signed-off-by: Steven Kao <skao@nvidia.com>
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|
| b0a86254 | 25-May-2017 |
Vignesh Radhakrishnan <vigneshr@nvidia.com> |
Tegra194: Enable fake system suspend
Fake system suspend for Tegra194, calls the routine
tegra_secure_entrypoint() instead of calling WFI.
In essence, this is a debug mode that ensures
that the code
Tegra194: Enable fake system suspend
Fake system suspend for Tegra194, calls the routine
tegra_secure_entrypoint() instead of calling WFI.
In essence, this is a debug mode that ensures
that the code path of kernel->ATF and back to kernel
is executed without depending on other components
involved in the system suspend path.
This is for ensuring that verification of system suspend
can be done on pre-silicon platforms without depending on
the rest of the layers being enabled.
Change-Id: I18572b169b7ef786f9029600dad9ef5728634f2b
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>
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|
| cff9b9c2 | 22-Jun-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: convert 'target_cpu' and 'target_cluster' to 32-bits
This patch converts the 'target_cpu' and 'target_cluster' variables from
the tegra_soc_pwr_domain_on() handler to 32-bits. This fixes t
Tegra194: convert 'target_cpu' and 'target_cluster' to 32-bits
This patch converts the 'target_cpu' and 'target_cluster' variables from
the tegra_soc_pwr_domain_on() handler to 32-bits. This fixes the signed
comparison warning flagged by the compiler.
Change-Id: Idfd7ad2a62749bb0dd032eb9eb5f4b28df32bba0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 719fdb6e | 31-May-2017 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: platform support for memctrl/smmu drivers
This patch adds platform support for the Memory Controller and
SMMU drivers, for the Tegra194 SoC.
Change-Id: Id8b482de70f1f93bedbca8d124575c39b4
Tegra194: platform support for memctrl/smmu drivers
This patch adds platform support for the Memory Controller and
SMMU drivers, for the Tegra194 SoC.
Change-Id: Id8b482de70f1f93bedbca8d124575c39b469927f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 14105374 | 24-Jan-2017 |
Krishna Sitaraman <ksitaraman@nvidia.com> |
Tegra194: Support for cpu suspend
This patch adds support for cpu suspend in T19x soc.
Change-Id: I8ef1d3e03ee9c528dec34eaff6dcbbfa43941484
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com> |
| 1520b5d6 | 23-Oct-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: Refactor common platform code [5/5]
Removes unused source code for BL2 and BL31 in platform.mk.
Clean-up unused header files, syntax fixes, and alphabetical
sorting post-refactoring
Signed-o
intel: Refactor common platform code [5/5]
Removes unused source code for BL2 and BL31 in platform.mk.
Clean-up unused header files, syntax fixes, and alphabetical
sorting post-refactoring
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ie5ea9b4d3abdb0187cddeb04d2fcfb51fbe5c4dd
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|
| c76d4239 | 23-Oct-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: Refactor common platform code [4/5]
Pull out SiP & PSCI service driver into socfpga common directory.
Remove deassert_peripheral_reset from cold reset procedure as it is not
needed.
Signed-o
intel: Refactor common platform code [4/5]
Pull out SiP & PSCI service driver into socfpga common directory.
Remove deassert_peripheral_reset from cold reset procedure as it is not
needed.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I1a0390fca6db4c89919a2a038de2a9d96c3ae4fd
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|
| d09adcba | 23-Oct-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: Refactor common platform code [3/5]
Pull out mailbox driver into common area as they can be shared between
intel's socfpga platform
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.h
intel: Refactor common platform code [3/5]
Pull out mailbox driver into common area as they can be shared between
intel's socfpga platform
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4064de1ec668931d77abcb7804f6952b70d33716
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|
| e9b5e360 | 23-Oct-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: Refactor common platform code [2/5]
Share socfpga private definitions and storage driver between Agilex and
Stratix 10 platform.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.hali
intel: Refactor common platform code [2/5]
Share socfpga private definitions and storage driver between Agilex and
Stratix 10 platform.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I6da147f4d2df4a97c505d4bbcffadf63bc3bf4a5
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|
| 328718f2 | 23-Oct-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: Refactor common platform code [1/5]
Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.
Share platform_def header between both
intel: Refactor common platform code [1/5]
Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.
Share platform_def header between both Agilex and Stratix10 and store
platform specific definitions in socfpga_plat_def.h
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d
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|
| 48393e30 | 27-Nov-2019 |
Paul Kocialkowski <paul.kocialkowski@bootlin.com> |
rockchip: px30: Add support for UART3 as serial output
Add the UART3 base definition for serial output, which is used on some
PX30 SoM boards.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bo
rockchip: px30: Add support for UART3 as serial output
Add the UART3 base definition for serial output, which is used on some
PX30 SoM boards.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Change-Id: I8490b15c9f129a33c01cb78bd78675014bc7b015
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|
| 697d18ae | 18-Nov-2019 |
Lionel Debieve <lionel.debieve@st.com> |
plat/st: Fix incorrect return value
Change the return code in boot_api.h which impacts the
authentication result.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I2c3aadb98dd261ae5
plat/st: Fix incorrect return value
Change the return code in boot_api.h which impacts the
authentication result.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I2c3aadb98dd261ae5ad73978fc74a8a8cfa59b82
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>
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|
| c6dc8504 | 26-Nov-2019 |
Stefan Mavrodiev <stefan@olimex.com> |
allwinner: power: Add DLDO4 power rail
A64-OLinuXino family boards (maybe others too) uses PG for USB vbus
enable/disable. However PG is supplied by DLDO4, which is not present
in the list of known
allwinner: power: Add DLDO4 power rail
A64-OLinuXino family boards (maybe others too) uses PG for USB vbus
enable/disable. However PG is supplied by DLDO4, which is not present
in the list of known regulators. This patch adds DLD04 to it.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Change-Id: I31d3bb3e0004ccf5b282d08b530ee44979da0466
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|
| d537ee79 | 25-Nov-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes I5693ad56,I9ddc077a into integration
* changes:
mediatek: mt8183: Fix AARCH64 init fail on CPU0
mediatek: mt8183: refine GIC driver for low power scenarios |
| c6e0a64d | 31-Oct-2019 |
James Liao <jamesjj.liao@mediatek.com> |
mediatek: mt8183: Fix AARCH64 init fail on CPU0
CPU0 is default on, so it doesn't need to run pwr_domain_on() at
boot. CPU0 AARCH64 will be set in pwr_domain_suspend(), but it may
encounter race con
mediatek: mt8183: Fix AARCH64 init fail on CPU0
CPU0 is default on, so it doesn't need to run pwr_domain_on() at
boot. CPU0 AARCH64 will be set in pwr_domain_suspend(), but it may
encounter race condition with other CPUs.
Now AARCH64 will be set with cluster on in pwr_domain_on(), and
all CPUs on this cluster will be set together. It doesn't need to
set AARCH64 again in pwr_domain_suspend(), so the race condition
can be avoided.
Change-Id: I5693ad56e4901f82badb0fc0d8d13e4c9acfe648
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
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|
| 4450a518 | 04-Oct-2019 |
kenny liang <kenny.liang@mediatek.com> |
mediatek: mt8183: refine GIC driver for low power scenarios
Implement rdist save/resore functions to support low power scenarios.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I9
mediatek: mt8183: refine GIC driver for low power scenarios
Implement rdist save/resore functions to support low power scenarios.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I9ddc077a04f843275fbe2e868cdd0bd00d622de7
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|
| 82262970 | 22-Nov-2019 |
joanna.farley <joanna.farley@arm.com> |
Merge "mediatek: mt8183: switch PLL/CLKSQ/ck_off/axi_26m control to SPM" into integration |
| 0ff3fb32 | 20-Nov-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "Fix multithreaded FVP power domain tree" into integration |
| d7b4cd41 | 18-Sep-2019 |
Justin Chadwell <justin.chadwell@arm.com> |
Enable -Wlogical-op always
-Wlogical-op prevents common errors with using numerical constants where
a boolean one is expected as well as when the operands of a logical
operator are the same. While t
Enable -Wlogical-op always
-Wlogical-op prevents common errors with using numerical constants where
a boolean one is expected as well as when the operands of a logical
operator are the same. While these are perfectly valid behavior, they
can be a sign that something is slightly off.
This patch adds this warning to gcc and it's closest equivalent to
clang, while also fixing any warnings that enabling them causes.
Change-Id: Iabadfc1e6ee0c44eef6685a23b0aed8abef8ce89
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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| b7f6525d | 17-Sep-2019 |
Justin Chadwell <justin.chadwell@arm.com> |
Enable -Wshadow always
Variable shadowing is, according to the C standard, permitted and valid
behaviour. However, allowing a local variable to take the same name as a
global one can cause confusion
Enable -Wshadow always
Variable shadowing is, according to the C standard, permitted and valid
behaviour. However, allowing a local variable to take the same name as a
global one can cause confusion and can make refactoring and bug hunting
more difficult.
This patch moves -Wshadow from WARNING2 into the general warning group
so it is always used. It also fixes all warnings that this introduces
by simply renaming the local variable to a new name
Change-Id: I6b71bdce6580c6e58b5e0b41e4704ab0aa38576e
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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|