refactor(tegra): deprecate tegra186 platform

The Tegra186 platform has reached EOL. The formal announcement is at
https://forums.developer.nvidia.com/t/upstream-tf-a-mmu-issues-on-tegra186/350096.

refactor(tegra): deprecate tegra186 platform

The Tegra186 platform has reached EOL. The formal announcement is at
https://forums.developer.nvidia.com/t/upstream-tf-a-mmu-issues-on-tegra186/350096.

This patch removes the support for this platform as a
result.

Reported-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iec4668c3bd34000bbc2da685d0be4a4e06cf05d0

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refactor(tegra): deprecate tegra210 platform

The Tegra210 platform has reached EOL. The formal announcement is at
https://forums.developer.nvidia.com/t/upstream-tf-a-fails-to-boot-on-tegra210/350094

refactor(tegra): deprecate tegra210 platform

The Tegra210 platform has reached EOL. The formal announcement is at
https://forums.developer.nvidia.com/t/upstream-tf-a-fails-to-boot-on-tegra210/350094.

This patch removes the support for this platform as a result.

Reported-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Id894f892ade438b5e15a6fcb05509691ef2257d8

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Merge changes from topic "tc-upstreaming-14Apr" into integration

* changes:
fix(tc): fix the platform topology
feat(tc): support buildroot ddk runtime integration

Merge changes from topic "mb/fwu-sec-fix" into integration

* changes:
fix(arm): harden FWU address range checks
fix(bl1): harden FWU copy/auth overflow checks

fix(versal2): use 64-bit macros for BL31 checks

BL31_BASE and BL31_LIMIT are used for BL31 address range
validation during platform checks.

Using U() produces 32-bit constants, which can truncate
u

fix(versal2): use 64-bit macros for BL31 checks

BL31_BASE and BL31_LIMIT are used for BL31 address range
validation during platform checks.

Using U() produces 32-bit constants, which can truncate
upper address bits and cause incorrect comparisons on
AArch64 systems.

Update these macros to use UL() so the constants are
64-bit and type-consistent.

Change-Id: Idae2d3e3874258a60b859b65e09c2d03693c086a
Signed-off-by: Sai Varun Venkatapuram <saivarun.venkatapuram@amd.com>

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fix(qemu): produce manifest entry inside transfer list

When SPD is configured as SPMD, BL2 is now responsible for creating
`TL_TAG_DT_*_MANIFEST` before handing off the control to bl31, where
it wil

fix(qemu): produce manifest entry inside transfer list

When SPD is configured as SPMD, BL2 is now responsible for creating
`TL_TAG_DT_*_MANIFEST` before handing off the control to bl31, where
it will look up the transfer list and prepare the transition context
for SPMC (see `find_and_prepare_sp_context`).

This adds the logic for qemu platforms to populate the transfer list
entry and content in BL2 setup phase.

Change-Id: I95e17e4fd7e3ecfbae18568ec3bfe35d587399eb
Signed-off-by: Kun Qin <kuqin@microsoft.com>

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fix(qemu-sbsa): fix build break when SPM set to SPMD

Current build will break if SPM set to SPMD as it will fail to resolve
the `read_uuid` function from `qemu_io_register_sp_pkg`.

This change adds

fix(qemu-sbsa): fix build break when SPM set to SPMD

Current build will break if SPM set to SPMD as it will fail to resolve
the `read_uuid` function from `qemu_io_register_sp_pkg`.

This change adds the missing file for QEMU sbsa.

Change-Id: I3472f57f06e7cb12132d94cb52d36905ce697d18
Signed-off-by: Kun Qin <kuqin@microsoft.com>

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fix(tc): fix the platform topology

The platform topology is used by PSCI for power state machine
management. The TC platform has the affinity levels:

- CPU : affinity level 0
- Cluster : af

fix(tc): fix the platform topology

The platform topology is used by PSCI for power state machine
management. The TC platform has the affinity levels:

- CPU : affinity level 0
- Cluster : affinity level 1
- System : affinity level 2

Correct PLAT_MAX_PWR_LVL and tc_pd_tree_desc to reflect the three levels
of affinity.

We also need to calculate the right number for power domains, in the end
the PSCI will allocate corresponding structures for maintain these power
domains.

After these extending, add tc_security.c into building list to dismiss
building failure.

Change-Id: I575f84c165fde1c8065437f7d1ec261bb0c7b57a
Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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feat(tc): support buildroot ddk runtime integration

- Updated the data fs load address to align with the new memory
layout requirements.
- Defined and integrated the Buildroot memory layout into RAM

feat(tc): support buildroot ddk runtime integration

- Updated the data fs load address to align with the new memory
layout requirements.
- Defined and integrated the Buildroot memory layout into RAM.

Change-Id: If6216150f4a0e97acda6ec4dbf5782ffc48bae23
Signed-off-by: Quoc Khanh Le <quockhanh.le@arm.com>
Signed-off-by: Mohanprasath Ramamoorthy <mohanprasath.ramamoorthy@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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fix(qti): don't fail to write dload mode register

On the Kodiak platform, setting download mode fails with "failed to set
download mode: -22". This is because the memmap address of
TCSR_BOOT_MISC_D

fix(qti): don't fail to write dload mode register

On the Kodiak platform, setting download mode fails with "failed to set
download mode: -22". This is because the memmap address of
TCSR_BOOT_MISC_DETECT is not in qti_secure_io_allowed_regs, so the call
to QTI_SIP_SVC_SECURE_IO_WRITE_ID fails. Add the address to the array to
prevent this error.

Change-Id: Icb5db579a5354c86d6c6f7a870d1a57fe5f16f3d
Signed-off-by: hliney <hliney@qti.qualcomm.com>

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feat(k3low): optimize firewall configuration to minimize boot time

Currently, ROM configured firewalls are removed during SOC init for
AM62L by iterating over all regions of the firewalls and then t

feat(k3low): optimize firewall configuration to minimize boot time

Currently, ROM configured firewalls are removed during SOC init for
AM62L by iterating over all regions of the firewalls and then taking
action if they are active. In this process, we end up making an
unnecessarily large number of TISCI calls, which negatively impacts the
boot time.

Instead, pre-determine the list of firewall IDs and respective regions
configured by ROM, and add a static table to only re-configure those
regions. This greatly reduces the number of TISCI calls we are making,
and hence minimizes boot time impact.

While re-configuring, set a permissive background firewall enabling
access to everyone. This is equivalent to keeping them disabled.
However, when going into low-power modes, TIFS doesn't save context for
disabled firewalls. It only concerns itself with enabled firewalls.
Hence, if we disable them instead, ROM comes up again in the resume
sequence to make the same configurations. By keeping the firewalls
enabled, TIFS will save their context during suspend, and handle their
restoration during resume, thereby undoing anything ROM had done in
resume. This is neater and faster than TF-A itself handling the firewall
configuration again in resume.

Change-Id: I9ba7fa112a8d10f08f887fbb5a13e33177d60a80
Signed-off-by: T Pratham <t-pratham@ti.com>

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Merge changes from topic "mb/partition-uuid-lookup" into integration

* changes:
feat(arm): prefer GUID-based GPT partition lookup
feat(guid-partition): add type+index GPT lookup

Merge "feat(qti): port SMMU driver from QTISECLIB" into integration

feat(qti): port SMMU driver from QTISECLIB

Port the SMMU driver from QTISECLIB and format it to
prepare for upstreaming. SMMU driver in TF-A is necessary
for configuration of access control and othe

feat(qti): port SMMU driver from QTISECLIB

Port the SMMU driver from QTISECLIB and format it to
prepare for upstreaming. SMMU driver in TF-A is necessary
for configuration of access control and other config
registers as listed in smmu_cfg.h on boot.

Change-Id: I938ca39c0d268b59002cef14b71e6ba9d78a30b5
Signed-off-by: Hailey Liney <hliney@qti.qualcomm.com>

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Merge changes from topics "mb/drtm-sec-fix", "mb/sec-fixes" into integration

* changes:
fix(drtm): validate NWd DCE region size to prevent overflow
fix(arm): bound backup GPT spec length
fix(j

Merge changes from topics "mb/drtm-sec-fix", "mb/sec-fixes" into integration

* changes:
fix(drtm): validate NWd DCE region size to prevent overflow
fix(arm): bound backup GPT spec length
fix(juno): raise BL2 max size for hardened IO checks
fix(io): validate FIP ToC bounds and catch short reads
feat(lib): add u64 overflow helper

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Merge "feat(rk3568): add early CPU reset mechanism to enable crypto function" into integration

fix(arm): harden FWU address range checks

Validate FWU ranges before computing end addresses to avoid
integer overflow and malformed map entries bypassing bounds
checks, which could lead to out-of-r

fix(arm): harden FWU address range checks

Validate FWU ranges before computing end addresses to avoid
integer overflow and malformed map entries bypassing bounds
checks, which could lead to out-of-range accesses.

Change-Id: I141752164935157ffa1b1488b1b90bb00fc559f8
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "fix(rcar3): change the migrate information for OPTEE-OS" into integration

fix(versal-net): use 64-bit macros for BL31 checks

BL31_BASE and BL31_LIMIT are used for BL31 address range
validation during platform checks.

Using U() produces 32-bit constants, which can truncat

fix(versal-net): use 64-bit macros for BL31 checks

BL31_BASE and BL31_LIMIT are used for BL31 address range
validation during platform checks.

Using U() produces 32-bit constants, which can truncate
upper address bits and cause incorrect comparisons on
AArch64 systems.

Update these macros to use UL() so the constants are
64-bit and type-consistent.

Change-Id: I717cf89a8ab9569ead2b9d120b9bbadd5593e381
Signed-off-by: Sai Varun Venkatapuram <saivarun.venkatapuram@amd.com>

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fix(versal): use 64-bit macros for BL31 checks

BL31_BASE and BL31_LIMIT are used for BL31 address range
validation during platform checks.

Using U() produces 32-bit constants, which can truncate
up

fix(versal): use 64-bit macros for BL31 checks

BL31_BASE and BL31_LIMIT are used for BL31 address range
validation during platform checks.

Using U() produces 32-bit constants, which can truncate
upper address bits and cause incorrect comparisons on
AArch64 systems.

Update these macros to use UL() so the constants are
64-bit and type-consistent.

Change-Id: I40c8c099a5663a1e8b410cd22157204de8c2e696
Signed-off-by: Sai Varun Venkatapuram <saivarun.venkatapuram@amd.com>

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Merge "fix(armada): mv_ddr path may not be a git repo" into integration

Merge changes from topic "feat_rme" into integration

* changes:
fix(firme): granule management service
feat(gpt): move gpt support under ENABLE_FEAT_RME
feat(rmmd): replace ENABLE_RME with ENA

Merge changes from topic "feat_rme" into integration

* changes:
fix(firme): granule management service
feat(gpt): move gpt support under ENABLE_FEAT_RME
feat(rmmd): replace ENABLE_RME with ENABLE_RMM
feat(rme): split off ENABLE_FEAT_RME

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feat(versal-net): add build macro support for IPI_ID_APU

Add build-time macro support for PLAT_IPI_ID_APU to allow
the APU IPI channel to be explicitly selected at build time,
as per the design. Thi

feat(versal-net): add build macro support for IPI_ID_APU

Add build-time macro support for PLAT_IPI_ID_APU to allow
the APU IPI channel to be explicitly selected at build time,
as per the design. This change aligns PLAT_IPI_ID_APU handling
with existing IPI ID macros, enabling platforms to define the
APU IPI ID via a build flag instead of hardcoding it in platform
code. This improves configurability and consistency across
platform.

Change-Id: I9b2be16a73cc1c6dcf273c2531af8aaf01695cd1
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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Merge changes from topic "st_fixes" into integration

* changes:
refactor(st): use %c to display board info
fix(st): update stm32image tool to address Coverity issues
fix(stm32mp2-fdts): fix LP

Merge changes from topic "st_fixes" into integration

* changes:
refactor(st): use %c to display board info
fix(st): update stm32image tool to address Coverity issues
fix(stm32mp2-fdts): fix LPDDR4 16bits swizzle
fix(st-ddr): add missing newline
fix(st-ddr): fix coverity static analysis issues
fix(st-rif): do not assign an unused value for node when parsing config
fix(st-pmic): initialize some structs in dt_pmic2_i2c_config
fix(st-pmic): check stpmic2_is_buck1_high_voltage return
fix(stm32mp2): remove unused macro PLAT_NB_GPIO_REGUS
feat(st-clock): keep TAMP_BKP_REG_CLK always on
fix(st-clock): check fdt_subnode_offset return
fix(st-clock): remove some variables default assignment
fix(st-clock): do not return NULL in _clk_get
fix(st-clock): do not include platform_def.h
feat(st-clock): add trace for unknown clock identifier
feat(st-clock): add ck_sys_dbg clock for STM32MP2
refactor(dt-bindings): remove CMD_CLK macros
fix(st-clock): remove CLK_CFG/CMD_CLK support for st,kerclk
fix(st-clock): increase startup timeout for oscillators for STM32MP2
fix(st-clock): increase startup timeout for oscillators for STM32MP1
refactor(st-clock): move oscillators ops from clk-stm32-core to drivers
feat(st-clock): add barriers in clock driver

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feat(gpt): move gpt support under ENABLE_FEAT_RME

Granule Protection Tables (GPT) library support is enabled only when
ENABLE_RMM is set (previously this build option was ENABLE_RME). Since
RME rela

feat(gpt): move gpt support under ENABLE_FEAT_RME

Granule Protection Tables (GPT) library support is enabled only when
ENABLE_RMM is set (previously this build option was ENABLE_RME). Since
RME related support is now enabled using feature detection option
ENABLE_FEAT_RME, this patch moves GPT support under ENABLE_FEAT_RME.

This change brings in below benefits:
- single TF-A build that works for RME and non-RME systems, when
build with ENABLE_FEAT_RME=2 (FEAT_STATE_CHECK)
- RMM loading is optional on RME systems
- SiP calls that leverages RME features to change the PAS of a memory
range from non-secure to secure is supported without need to enable
Realm PAS or RMM.
- FIRME Granule Management Interface (GMI) ABIs that handles
FEAT_RME_GPC2/FEAT_RME_GDI can be enabled without need to enable RMM

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I88d9d4e0491af2b4ae0307c018f2d4a71ee6693f

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