feat(cpus): add support for LSC25 E-core CPU

Add basic CPU library code to support the Large Screen Compute 2025
E-core CPU.

Change-Id: Ibda2e8441d3a3e35941448b483d07e17db2ef234
Signed-off-by: Ryan

feat(cpus): add support for LSC25 E-core CPU

Add basic CPU library code to support the Large Screen Compute 2025
E-core CPU.

Change-Id: Ibda2e8441d3a3e35941448b483d07e17db2ef234
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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feat(cpus): add support for LSC25 P-core CPU

Add basic CPU library code to support the Large Screen Compute 2025
P-core CPU.

Change-Id: Icfd2fdbaed577e64cb2db028416a6eca5ba2cfcf
Signed-off-by: Ryan

feat(cpus): add support for LSC25 P-core CPU

Add basic CPU library code to support the Large Screen Compute 2025
P-core CPU.

Change-Id: Icfd2fdbaed577e64cb2db028416a6eca5ba2cfcf
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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feat(fvp): load SP_PKGs with TRANSFER_LIST

To enable loading of SP_PKGs when using the TRANSFER_LIST build option,
this patch loads TB_FW_CONFIG in BL1 and populates sp_mem_params_descs
in arm_trans

feat(fvp): load SP_PKGs with TRANSFER_LIST

To enable loading of SP_PKGs when using the TRANSFER_LIST build option,
this patch loads TB_FW_CONFIG in BL1 and populates sp_mem_params_descs
in arm_transfer_list_dyn_cfg_init().

Since there is no standard tag_id defined for TB_FW_CONFIG in the
transfer list, define PLAT_ARM_TB_FW_CONFIG_TL_TAG as a platform-specific
identifier to load TB_FW_CONFIG.

With this change, BL2 can load the SP_PKGs specified in TB_FW_CONFIG.

Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I2470c1ef3bf2bf921d0de1fff541565df13eaee4

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fix(allwinner): avoid crash when running without DTB

For determining the PMIC type and the bus its connected to, we use the
DTB that is appended to the U-Boot binary, by looking for it in DRAM.
And

fix(allwinner): avoid crash when running without DTB

For determining the PMIC type and the bus its connected to, we use the
DTB that is appended to the U-Boot binary, by looking for it in DRAM.
And while we bail out correctly if we don't find it there, we later try
to use the DTB pointer - without checking.

Add a check in sunxi_pmic_setup(), to only proceed if we have found a
DTB before, and exit early otherwise.

This fixes more experimental setups, where TF-A is run without U-Boot.

Change-Id: I9a7677be057a84fe6bee093d098be758970eec81
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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fix(intel): remove invalid SDM SMMU Stream ID register from bypass list

The register is SDM-owned and not accessible by HPS.
It was added by mistakein v2.7.0.
Removing it ensures correct access cont

fix(intel): remove invalid SDM SMMU Stream ID register from bypass list

The register is SDM-owned and not accessible by HPS.
It was added by mistakein v2.7.0.
Removing it ensures correct access control.

Change-Id: I76d27e5b53bfb115ace6011dbb79f2fac049bb4e
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): prevent invalid register rejection on non-A5F4 devices

Move TSN_TBU_STREAM_CTRL_REG_3_TSN0/1/2 handling outside the
main switch to ensure non-A5F4 devices (e.g., A5F0) evaluate
other val

fix(intel): prevent invalid register rejection on non-A5F4 devices

Move TSN_TBU_STREAM_CTRL_REG_3_TSN0/1/2 handling outside the
main switch to ensure non-A5F4 devices (e.g., A5F0) evaluate
other valid registers.

Previously, TSN cases were inside the switch and followed
by a `break` if not A5F4, causing early exit and -1 return.
Valid registers (e.g., ECC_INTMASK_x)were rejected, blocking boot.

Now, A5F4 TSN registers are handled conditionally
and fallthrough is clean for all other devices.

Change-Id: I1339e0e3951ccb68f02dc437f25db6c27d2a0877
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): allow kernel access to TSN TBU stream control registers

Added TSN_TBU_STREAM_CTRL_REG_3_TSN0/1/2 to ATF's secure range check
to permit setting the 31st bit from kernel space.

Change-Id:

fix(intel): allow kernel access to TSN TBU stream control registers

Added TSN_TBU_STREAM_CTRL_REG_3_TSN0/1/2 to ATF's secure range check
to permit setting the 31st bit from kernel space.

Change-Id: I74bd296c4c050fb61d4df5c1bd5b57449b3a13e3
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(fvp): use global option for setting PLAT_ARM_MAX_BL2_SIZE

Use global option TRUSTED_BOARD_BOOT for setting PLAT_ARM_MAX_BL2_SIZE.

Change-Id: Ia360b36535d2039de8e41da90dd4c8478adb6d54
Signed-off

fix(fvp): use global option for setting PLAT_ARM_MAX_BL2_SIZE

Use global option TRUSTED_BOARD_BOOT for setting PLAT_ARM_MAX_BL2_SIZE.

Change-Id: Ia360b36535d2039de8e41da90dd4c8478adb6d54
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "chore(fvp): bump maximum permitted Trusted SRAM size" into integration

Merge "fix(versal2): align comment about invalid console selection" into integration

chore(fvp): bump maximum permitted Trusted SRAM size

Bump the size of the Trusted SRAM in FVP builds, as we are now exceeding
the 256KB limit in a meaningful number of builds.

Change-Id: Iefd584172

chore(fvp): bump maximum permitted Trusted SRAM size

Bump the size of the Trusted SRAM in FVP builds, as we are now exceeding
the 256KB limit in a meaningful number of builds.

Change-Id: Iefd58417297507eaa9b24e55fc36de67bd16b716
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge changes from topic "gr/cov_fixes" into integration

* changes:
fix(libc): fix coverity overflowed constant
fix(libc): fix coverity overflowed constant
fix(psci): fix coverity issue with o

Merge changes from topic "gr/cov_fixes" into integration

* changes:
fix(libc): fix coverity overflowed constant
fix(libc): fix coverity overflowed constant
fix(psci): fix coverity issue with out-of-bounds read
fix(fvp): fix coverity issue unsigned_compare

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fix(qti): uart platform base address for SC7180

Following merge of [1] , SC7180 platform broke because of mismatched
UART base address. Restore to the proper value.

[1] https://review.trustedfirmwa

fix(qti): uart platform base address for SC7180

Following merge of [1] , SC7180 platform broke because of mismatched
UART base address. Restore to the proper value.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/43574/5/plat/qti/sc7180/inc/platform_def.h

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Change-Id: I4d34db01720ce289a87bccf0338205b4861e11cb

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feat(rdv3): enable numa aware per-cpu for RD-V3-Cfg2

RD-V3-Cfg2 being quad chip can make use of NUMA allocation within the
per-cpu framework. With NUMA allocation, the platform can distribute
per-cp

feat(rdv3): enable numa aware per-cpu for RD-V3-Cfg2

RD-V3-Cfg2 being quad chip can make use of NUMA allocation within the
per-cpu framework. With NUMA allocation, the platform can distribute
per-cpu objects within a memory that is local to a particular node.
RD-V3-Cfg2 in this case has the per-cpu objects distributed across
different SRAMs present on the system.

introduce platform-specific helper functions to enhance the per_cpu
framework. Adds a helper function to zero init per_cpu sections,
ensuring clean initialization of per-cpu data. Introduces a function
to obtain the base address of per_cpu sections, facilitating efficient
access to per-CPU data structures. Enhances the per_cpu framework's
capability to handle platform-specific requirements.

These additions are crucial for maintaining the integrity and
performance of per-cpu operations.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I550c6b5c59f80fbe2b746a1261cda857f4fb1990

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fix(versal2): align comment about invalid console selection

Error message should be aligned actual symbol used for console section
which has been changed by commit 2333ab4cd214 ("fix(versal2): renam

fix(versal2): align comment about invalid console selection

Error message should be aligned actual symbol used for console section
which has been changed by commit 2333ab4cd214 ("fix(versal2): rename
console build arg to generic").

Change-Id: I230892875a6343ca8ffc55e0fac251f6586cf3f4
Signed-off-by: Michal Simek <michal.simek@amd.com>

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fix(fvp): skip SP discovery through FFA_PARTITION_INFO_GET_REGS

The initialization function implemented for the dummy LSP of FVP port
invokes FFA_PARTITION_INFO_GET_REGS to obtain partition properti

fix(fvp): skip SP discovery through FFA_PARTITION_INFO_GET_REGS

The initialization function implemented for the dummy LSP of FVP port
invokes FFA_PARTITION_INFO_GET_REGS to obtain partition properties of
Secure Partitions managed by SPMC. This happens even before the normal
world is booted.

Hafnium SPMC mistakes this as a FF-A invocation from NWd. As per FF-A
version negotiation protocol, Hafnium locks the version of NWd to v1.3
whereas the NWd never got an opportunity to register its own framework
version.

This patch performs early exit from the helper utility to give NWd
endpoint/Hypervisor an opportunity to register its FF-A version with
SPM. We intentionally do not remove the helper utility as it will be
used in a different patchset for a new anticipated feature.

Change-Id: I54087bd2ad53355afeb024c0e4df6a5ba7ab125a
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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fix(fvp): fix coverity issue unsigned_compare

Fixes less than zero comparison for unsigned value.

Issue Description:
CID 447712: (#1 of 1): Macro compares unsigned to 0 (NO_EFFECT)
unsigned_compare

fix(fvp): fix coverity issue unsigned_compare

Fixes less than zero comparison for unsigned value.

Issue Description:
CID 447712: (#1 of 1): Macro compares unsigned to 0 (NO_EFFECT)
unsigned_compare: This less-than-zero comparison of an
unsigned value is never true. power_level < 0ULL.

Change-Id: Ia06f8729ac78b05046402e29e30f55c5f0b9e215
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "upstream_integrate_ddr_fw" into integration

* changes:
feat(s32g274ardb): add custom DDR FW UUID entry
fix(fiptool): skip Layerscape makefile for S32 build

Merge changes from topic "qti-rb3gen2" into integration

* changes:
docs(maintainers): update QTI platform maintainers
docs(qti): add RB3Gen2 platform documentation
docs(qti): move documentatio

Merge changes from topic "qti-rb3gen2" into integration

* changes:
docs(maintainers): update QTI platform maintainers
docs(qti): add RB3Gen2 platform documentation
docs(qti): move documentation under docs/plat/qti/
feat(kodiak): add support for RB3Gen2 platform
feat(qti): introduce basic XPU driver
refactor(qti): introduce SoC codename as Kodiak
feat(qti): add TF-A BL2 common platform framework
refactor(qti): refactor RNG as a proper driver
fix(qti): fix config PLAT_XLAT_TABLES_DYNAMIC
feat(qti): add BL32 support
refactor(qti): make UART config independent
refactor(qti): make CNTFRQ config independent
fix(qti): fix build without coreboot

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fix(morello): don't define get_mem_client_mode() when it won't be used

Prevents an unused function warning.

Change-Id: I6e44c7f1deef9e41103fda78eaefabb378d400f6
Signed-off-by: Boyan Karatotev <boya

fix(morello): don't define get_mem_client_mode() when it won't be used

Prevents an unused function warning.

Change-Id: I6e44c7f1deef9e41103fda78eaefabb378d400f6
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(rdn2): don't use V1 as a label

V1 can also be a SIMD register and the assembler can get confused. Don't
use that name.

Change-Id: Id4320cbfb6ae157f53c7ca5452fd88afcaec452f
Signed-off-by: Boyan

fix(rdn2): don't use V1 as a label

V1 can also be a SIMD register and the assembler can get confused. Don't
use that name.

Change-Id: Id4320cbfb6ae157f53c7ca5452fd88afcaec452f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(s32g274ardb): add custom DDR FW UUID entry

Integrate support to add DDR FW to the final
FIP image via `fiptool`.

Add mechanism to allow platform specific image
UUID. Add DDR FW entries to toc_

feat(s32g274ardb): add custom DDR FW UUID entry

Integrate support to add DDR FW to the final
FIP image via `fiptool`.

Add mechanism to allow platform specific image
UUID. Add DDR FW entries to toc_entries and create
`plat_fiptool.mk` in order to enable the integration
of the DDR FW binary into the FIP image using
`fiptool` command.

Change-Id: I10c000025378206411ab70dbc5b2e745ffb01e5d
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2

Currently, the FEAT_EBEP feature presence check is only used for UNDEF
injection into lower ELs. However, this feature also aff

fix(cpufeat): extend FEAT_EBEP handling to delegate PMU control to EL2

Currently, the FEAT_EBEP feature presence check is only used for UNDEF
injection into lower ELs. However, this feature also affects the access
behavior of MDCR_EL2. Specifically, if the PMEE bits in MDCR_EL3 are not
set to 0b01, then the MDCR_EL2.PMEE bits cannot be configured by EL2.

This patch extends the use of FEAT_EBEP to delegate PMU IRQ and
profiling exception control to EL2 by setting MDCR_EL3.PMEE = 0b01.This
ensures that lower ELs can manage PMU configuration.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib7e1d5c72f017b8ffc2131fc57309dd9d811c973

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Merge "feat(mt8196): enable MTE2" into integration

Merge changes from topic "little-build-fixes" into integration

* changes:
fix(build): don't rely on Event Log build tree
fix(build): link Event Log library directly
fix(build): scan symbols un

Merge changes from topic "little-build-fixes" into integration

* changes:
fix(build): don't rely on Event Log build tree
fix(build): link Event Log library directly
fix(build): scan symbols until all are resolved
fix(build): add include directory dependencies

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