| c63f1451 | 24-Mar-2021 |
christine.zhu <christine.zhu@mediatek.corp-partner.google.com> |
mediatek: mt8195: initialize GIC
MT8192 GIC driver can be shared with MT8195. Move GIC driver to common
and do the initialization.
Signed-off-by: christine.zhu <christine.zhu@mediatek.corp-partner.
mediatek: mt8195: initialize GIC
MT8192 GIC driver can be shared with MT8195. Move GIC driver to common
and do the initialization.
Signed-off-by: christine.zhu <christine.zhu@mediatek.corp-partner.google.com>
Change-Id: I63f3e668b5ca6df8bcf17b5cd4d53fa84f330fed
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| 174a1cfe | 19-Mar-2021 |
Yidi Lin <yidi.lin@mediatek.com> |
Initialize platform for MediaTek MT8195
- Add basic platform setup
- Add MT8195 documentation at docs/plat/
- Add generic CPU helper functions
- Add basic register address
Change-Id: I7978e2f32e589
Initialize platform for MediaTek MT8195
- Add basic platform setup
- Add MT8195 documentation at docs/plat/
- Add generic CPU helper functions
- Add basic register address
Change-Id: I7978e2f32e58900e5cf93f741ee8eaf8b8e3b842
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
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| 65070a52 | 22-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes Ib0a2ce81,I5332fb52 into integration
* changes:
plat/qemu: add cortex-a72 support to 'virt' platform
plat/qemu: include gicv2.mk |
| 78c7beb4 | 31-Mar-2021 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
plat: send an sgi to communicate to linux
Upon recieving the interrupt send an SGI.
The sgi number is communicated by linux.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Change
plat: send an sgi to communicate to linux
Upon recieving the interrupt send an SGI.
The sgi number is communicated by linux.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Change-Id: Ib8f07ff7132ba5ac202b546914efb16d04820ed3
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
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| 8b48bfb8 | 17-Mar-2021 |
Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> |
plat: xilinx: Error management support
Add support for the trapping the IPI in TF-A.
Register handler for the irq no 62 which is the IPI interrupt.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.d
plat: xilinx: Error management support
Add support for the trapping the IPI in TF-A.
Register handler for the irq no 62 which is the IPI interrupt.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Change-Id: I9c04fdae7be3dda6a34a9b196274c0b5fdf39223
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
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| a262546f | 22-Apr-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "mediatek: mt8192: devapc: Add devapc driver" into integration |
| a05b3ad0 | 22-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "my-topic-name" into integration
* changes:
plat: imx8mm: Add in BL2 with FIP
plat: imx8mm: Enable Trusted Boot |
| dfe64665 | 21-Apr-2021 |
bipin.ravi <bipin.ravi@arm.com> |
Merge "Add "_arm" suffix to Makalu ELP CPU lib" into integration |
| e9cd36f5 | 21-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes Id7bdbc9b,Ia813e051,I2c437380,I736724cc,I454fb40a, ... into integration
* changes:
renesas: rzg: Add support to identify EK874 RZ/G2E board
drivers: renesas: common: watchdog: Add
Merge changes Id7bdbc9b,Ia813e051,I2c437380,I736724cc,I454fb40a, ... into integration
* changes:
renesas: rzg: Add support to identify EK874 RZ/G2E board
drivers: renesas: common: watchdog: Add support for RZ/G2E
drivers: renesas: rzg: Add QoS support for RZ/G2E
drivers: renesas: rzg: Add PFC support for RZ/G2E
drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC
renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N board
drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoC
drivers: renesas: rzg: Add QoS support for RZ/G2N
drivers: renesas: rzg: Add PFC support for RZ/G2N
drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC
renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H board
drivers: renesas: common: emmc: Select eMMC channel for RZ/G2H SoC
drivers: renesas: rzg: Add QoS support for RZ/G2H
drivers: renesas: rzg: Add PFC support for RZ/G2H
drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC
drivers: renesas: rzg: Switch using common ddr code
drivers: renesas: ddr: Move to common
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| d8dc8c9e | 21-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "plat: xilinx: zynqmp: Configure counter frequency during initialization" into integration |
| 62fbb315 | 10-Feb-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
stm32mp1: enable PIE for BL32
In order to prepare future support of FIP, BL32 (SP_min) is compiled
as Position Independent Executable.
Change-Id: I15e7cc433fb03e1833002f4fe2eaecb6ed42eb47
Signed-of
stm32mp1: enable PIE for BL32
In order to prepare future support of FIP, BL32 (SP_min) is compiled
as Position Independent Executable.
Change-Id: I15e7cc433fb03e1833002f4fe2eaecb6ed42eb47
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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| d2130da2 | 16-Apr-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
stm32mp1: set BL sizes regardless of flags
BL2 size is set to 100kB, and BL32 to 72kB, regardless of OP-TEE
or stack protector flags.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-I
stm32mp1: set BL sizes regardless of flags
BL2 size is set to 100kB, and BL32 to 72kB, regardless of OP-TEE
or stack protector flags.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Id7411bd55a4140718d64a647d81037720615fc81
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| 9f0ddae3 | 26-Mar-2021 |
Rajan Vaja <rajan.vaja@xilinx.com> |
plat: xilinx: zynqmp: Configure counter frequency during initialization
Counter frequency for generic timer of Arm-A53 based Application
Processing Unit(APU) is not configuring in case if First Stag
plat: xilinx: zynqmp: Configure counter frequency during initialization
Counter frequency for generic timer of Arm-A53 based Application
Processing Unit(APU) is not configuring in case if First Stage Boot
Loader(FSBL) does not initialize counter frequency. This happens
when FSBL is running from Arm-R5 based Real-time Processing Unit(RPU).
Because of that generic timer driver functionality is not working.
So configure counter frequency during initialization.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Icfccd59d7d2340fba25ebfb2ef6a813af4290896
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|
| 654bd99d | 19-Feb-2021 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
plat: xilinx: versal: Add the IPI CRC checksum macro support
Add support for CRC checksum for IPI data when the macro
IPI_CRC_CHECK is enabled.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.ab
plat: xilinx: versal: Add the IPI CRC checksum macro support
Add support for CRC checksum for IPI data when the macro
IPI_CRC_CHECK is enabled.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I3c25c715885759076055c6505471339b5d6edcd5
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|
| d7758354 | 19-Feb-2021 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
plat: xilinx: common: Rename the IPI CRC checksum macro
Rename the macro ZYNQMP_IPI_CRC_CHECK to IPI_CRC_CHECK and
move the related defines to the common include.
Signed-off-by: Venkatesh Yadav Abb
plat: xilinx: common: Rename the IPI CRC checksum macro
Rename the macro ZYNQMP_IPI_CRC_CHECK to IPI_CRC_CHECK and
move the related defines to the common include.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I6d30b081ac607572a0b23e10ca8031bc90489e58
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| 97bc7f0d | 20-Apr-2021 |
johpow01 <john.powell@arm.com> |
Add "_arm" suffix to Makalu ELP CPU lib
ELP processors can sometimes have different MIDR values or features so
we are adding the "_arm" suffix to differentiate the reference
implementation from othe
Add "_arm" suffix to Makalu ELP CPU lib
ELP processors can sometimes have different MIDR values or features so
we are adding the "_arm" suffix to differentiate the reference
implementation from other future versions.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ieea444288587c7c18a397d279ee4b22b7ad79e20
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|
| 207ef629 | 20-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "arm_ethosn_npu_sip" into integration
* changes:
Add SiP service to configure Arm Ethos-N NPU
plat/arm/juno: Add support to use hw_config in BL31 |
| bcf43f04 | 19-Mar-2021 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
renesas: rzg: Add support to identify EK874 RZ/G2E board
Add support to identify Silicon Linux RZ/G2E evaluation kit (EK874).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
renesas: rzg: Add support to identify EK874 RZ/G2E board
Add support to identify Silicon Linux RZ/G2E evaluation kit (EK874).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Id7bdbc9b0d25aa9af496d58d4bd5055579edc104
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| 30663f34 | 19-Mar-2021 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC
DRAM initialization on RZ/G2E SoC is identical to R-Car E3 so re-use the
same.
Signed-off-by: Lad Prabhakar <prabhakar.ma
drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC
DRAM initialization on RZ/G2E SoC is identical to R-Car E3 so re-use the
same.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I454fb40af4f8ce6c4c0d2a53edb307326efd02df
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| a4d86f67 | 19-Mar-2021 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N board
Add support to identify HopeRun HiHope RZ/G2N board.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewe
renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N board
Add support to identify HopeRun HiHope RZ/G2N board.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ib47aba84b63488247f6e9da1f5878140129766ce
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| b939cbbb | 19-Apr-2021 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC
Add support for initializing DRAM on RZ/G2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
R
drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC
Add support for initializing DRAM on RZ/G2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Id09a367b92b11a5da88f2dce6887677cc935d0c0
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| ec3e2f67 | 21-Dec-2020 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H board
Add support to identify HopeRun HiHope RZ/G2H board.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewe
renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H board
Add support to identify HopeRun HiHope RZ/G2H board.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I6b28350ef50595fea9a1b1b7353fcabaeb935970
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| fe5929c1 | 19-Apr-2021 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC
Add support for initializing DRAM on RZ/G2H SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
R
drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC
Add support for initializing DRAM on RZ/G2H SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Iae23f1093f65a9efd065d37b7d6e9340ff6350b9
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| 778db0e9 | 10-Mar-2021 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
drivers: renesas: rzg: Switch using common ddr code
Switch using common ddr driver code from renesas/common/ddr directory
for RZ/G2M SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.r
drivers: renesas: rzg: Switch using common ddr code
Switch using common ddr driver code from renesas/common/ddr directory
for RZ/G2M SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I807dcb0bc5186bd32bc1c577945d28634bb10e1f
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| faf5587c | 09-Mar-2021 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
drivers: renesas: ddr: Move to common
Move ddr driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Lad Prabhakar <prabhakar.
drivers: renesas: ddr: Move to common
Move ddr driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I9aef73d3e9a027a127ce7483b72d339559866727
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