| bba9fdee | 15-Dec-2021 |
Yann Gautier <yann.gautier@st.com> |
feat(stm32mp1): add regulator framework compilation
Add required macro PLAT_NB_RDEVS in platform code, and update
platform.mk to compile regulator framework.
Change-Id: I9dc7a0a4c4f5a23d9bedda368d4
feat(stm32mp1): add regulator framework compilation
Add required macro PLAT_NB_RDEVS in platform code, and update
platform.mk to compile regulator framework.
Change-Id: I9dc7a0a4c4f5a23d9bedda368d407612c9cd21cd
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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| 0c16e7d2 | 17-Sep-2020 |
Yann Gautier <yann.gautier@st.com> |
refactor(stm32mp1): re-order drivers init
SYSCFG can be initialized later, after console is up, to display the
warnings or messages it could issue.
PMIC should be initialized earlier, before SYSCFG
refactor(stm32mp1): re-order drivers init
SYSCFG can be initialized later, after console is up, to display the
warnings or messages it could issue.
PMIC should be initialized earlier, before SYSCFG init.
Change-Id: Icc3a1366083a1b1fde7f0e173645449b4c04c49b
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 33667d29 | 30-Aug-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(st): use newly introduced clock framework
Replace calls to stm32mp_clk_enable() / stm32mp_clk_disable() /
stm32mp_clk_get_rate() with clk_enable() / clk_disable() /
clk_get_rate().
Change-Id:
feat(st): use newly introduced clock framework
Replace calls to stm32mp_clk_enable() / stm32mp_clk_disable() /
stm32mp_clk_get_rate() with clk_enable() / clk_disable() /
clk_get_rate().
Change-Id: I15d2ce57b9499211fa522a1b53eeee9cf584c111
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
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| 847c6bc8 | 13-Oct-2020 |
Gabriel Fernandez <gabriel.fernandez@st.com> |
feat(clk): add a minimal clock framework
This is mainly a clock interface with clk_ops callbacks.
Those callbacks are: enable, disable, get_rate, set_parent,
and is_enabled.
This framework is compil
feat(clk): add a minimal clock framework
This is mainly a clock interface with clk_ops callbacks.
Those callbacks are: enable, disable, get_rate, set_parent,
and is_enabled.
This framework is compiled for STM32MP1.
Change-Id: I5119a2aeaf103ceaae7a60d9e423caf0c148d794
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
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| 2c791499 | 20-Dec-2021 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
feat(versal): add UART1 as console
Currently only UART0 is handled as console device, fix the
code to support UART1 as console also.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xili
feat(versal): add UART1 as console
Currently only UART0 is handled as console device, fix the
code to support UART1 as console also.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ifcd3c331cf6ce4afb0074357c92fc4addb9438b6
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| ea66e4af | 20-Dec-2021 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
feat(zynqmp): add uart1 as console
Currently only UART0 is handled as console device, fix the
code to support UART1 as console also.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xili
feat(zynqmp): add uart1 as console
Currently only UART0 is handled as console device, fix the
code to support UART1 as console also.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I08f69b65b78b967ceb7159f4a467aa5982b1f791
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| 24dd5a7b | 22-Nov-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add reboot function for PSCI
Add system_reset function in PSCI operations.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-
feat(plat/mediatek/mt8186): add reboot function for PSCI
Add system_reset function in PSCI operations.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I41001484f6244bd6ae7dedcfb6ce71cd6c035a1e
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| a68346a7 | 22-Nov-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mdeiatek/mt8186): add power-off function for PSCI
Add support for system-off.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic734696aab
feat(plat/mdeiatek/mt8186): add power-off function for PSCI
Add support for system-off.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic734696aab1b71ae85bca6ed08e544a522ce5c95
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| 572f8adb | 25-Nov-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): apply erratas for MT8186
MT8186 uses Cortex A76 CPU, so we apply these erratas.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Ch
feat(plat/mediatek/mt8186): apply erratas for MT8186
MT8186 uses Cortex A76 CPU, so we apply these erratas.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I84741535fbe429f664092f624c2da653532204cd
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| 06cb65ef | 14-Nov-2021 |
Garmin.Chang <Garmin.Chang@mediatek.com> |
feat(plat/mediatek/mt8186): add MCDI drivers
Add MCDI related drivers to handle CPU powered on/off in CPU suspend.
TEST=build pass
BUG=b:202871018
Change-Id: I85aaaf3a0e992a39d17c58f3d9d5ff1b5770f
feat(plat/mediatek/mt8186): add MCDI drivers
Add MCDI related drivers to handle CPU powered on/off in CPU suspend.
TEST=build pass
BUG=b:202871018
Change-Id: I85aaaf3a0e992a39d17c58f3d9d5ff1b5770f748
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
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| 1da57e54 | 08-Nov-2021 |
Garmin.Chang <Garmin.Chang@mediatek.com> |
feat(plat/mediatek/mt8186): add CPU hotplug
Implement PSCI platform operations to support CPU hotplug and MCDI.
TEST=bringup 8 CPUs successfully on kernel stage.
BUG=b:202871018
Change-Id: Ibd5423
feat(plat/mediatek/mt8186): add CPU hotplug
Implement PSCI platform operations to support CPU hotplug and MCDI.
TEST=bringup 8 CPUs successfully on kernel stage.
BUG=b:202871018
Change-Id: Ibd5423b70b3ca3f91edaa48d7ca5bc094e751510
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
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| 6e5d76ba | 12-Nov-2021 |
Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add RTC drivers
Add RTC drivers for EOSC calibration.
TEST=build pass
BUG=b:202871018
Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com>
Change
feat(plat/mediatek/mt8186): add RTC drivers
Add RTC drivers for EOSC calibration.
TEST=build pass
BUG=b:202871018
Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com>
Change-Id: Ib48c07204c4a614072ba710c042794b59e8a902a
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| 0fe7ae9c | 09-Nov-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
fix(plat/mediatek/mt8186): extend MMU region size
In mt8186 suspend/resume flow, ATF has to communicate with a subsys by
read/write the subsys registers. However, the register region of subsys
doesn
fix(plat/mediatek/mt8186): extend MMU region size
In mt8186 suspend/resume flow, ATF has to communicate with a subsys by
read/write the subsys registers. However, the register region of subsys
doesn't include in the MMU mapping region. It triggers MMU faults.
This patch extends the MMU region 0 size to cover all mt8186 HW modules.
This patch also remove MMU region 1 because region 0 covers region 1.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I520c51338578bd68756cd02603ce6783f93daf51
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| 95ea87ff | 01-Nov-2021 |
Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add DCM driver
DCM means dynamic clock management, and it can dynamically
slow down or gate clocks during CPU or bus idle.
1. Add MCUSYS related DCM drivers.
2. Enable M
feat(plat/mediatek/mt8186): add DCM driver
DCM means dynamic clock management, and it can dynamically
slow down or gate clocks during CPU or bus idle.
1. Add MCUSYS related DCM drivers.
2. Enable MCUSYS related DCM by default.
TEST=build pass
BUG=b:202871018
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: Idc669364c89cde0974d2940bd12987ee833d1965
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| af5a0c40 | 15-Oct-2021 |
Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add pinctrl support
Add MT8186 pinctrl support.
TEST=build pass
BUG=b:202871018
Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com>
Change-Id: I5b
feat(plat/mediatek/mt8186): add pinctrl support
Add MT8186 pinctrl support.
TEST=build pass
BUG=b:202871018
Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com>
Change-Id: I5b9c1c60a91c74c7d3f45c78a9403544373fa90f
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| 109b91e3 | 12-Oct-2021 |
Zhengnan Chen <zhengnan.chen@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add sys_cirq support
Add 8186 sys_cirq info.
TEST=build pass
BUG=b:202871018
Signed-off-by: Zhengnan Chen <zhengnan.chen@mediatek.corp-partner.google.com>
Change-Id: Ib
feat(plat/mediatek/mt8186): add sys_cirq support
Add 8186 sys_cirq info.
TEST=build pass
BUG=b:202871018
Signed-off-by: Zhengnan Chen <zhengnan.chen@mediatek.corp-partner.google.com>
Change-Id: Ib8a1c4e995288bf5f7981ea65f27727715fe5787
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| 206f125c | 11-Oct-2021 |
Christine Zhu <christine.zhu@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): initialize GIC
Initialize GIC for mt8186.
TEST=build pass
BUG=b:202871018
Signed-off-by: Christine Zhu <christine.zhu@mediatek.corp-partner.google.com>
Change-Id: I8d02
feat(plat/mediatek/mt8186): initialize GIC
Initialize GIC for mt8186.
TEST=build pass
BUG=b:202871018
Signed-off-by: Christine Zhu <christine.zhu@mediatek.corp-partner.google.com>
Change-Id: I8d029983c7ce48fa116fafa7fa78c65349308014
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| 5aab27dc | 06-Oct-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add SiP service
Add the basic SiP service.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4dcc7383237bb6c1f2494920cde
feat(plat/mediatek/mt8186): add SiP service
Add the basic SiP service.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4dcc7383237bb6c1f2494920cde21197754f6367
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| 5bc88ec6 | 06-Oct-2021 |
James Lo <james.lo@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add pwrap and pmic driver
1. Add 8186 pwrap driver to access pmic.
2. Add 6366 pmic driver to support clean PWRHOLD.
TEST=build pass
BUG=b:202871018
Signed-off-by: Jame
feat(plat/mediatek/mt8186): add pwrap and pmic driver
1. Add 8186 pwrap driver to access pmic.
2. Add 6366 pmic driver to support clean PWRHOLD.
TEST=build pass
BUG=b:202871018
Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com>
Change-Id: I3bc90460a6a55dff8d3293e04482abcad789bbb2
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| d73e15e6 | 06-Oct-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): initialize delay_timer
Initialize delay_timer for delay functions.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ib8f
feat(plat/mediatek/mt8186): initialize delay_timer
Initialize delay_timer for delay functions.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ib8f52d1c674537795cc478015c83cca0f872df60
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| a6a0af57 | 06-Oct-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): initialize systimer
Add systimer to support timer function.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I505f7d0944
feat(plat/mediatek/mt8186): initialize systimer
Add systimer to support timer function.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I505f7d094410d178e4203e3a9294b851a30ba150
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| 1b17e34c | 03-Oct-2021 |
Penny Jan <penny.jan@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add EMI MPU basic driver
EMI MPU stands for external memory interface memory protect unit.
MT8186 supports 32 regions and 16 domains.
We add basic driver currently, and w
feat(plat/mediatek/mt8186): add EMI MPU basic driver
EMI MPU stands for external memory interface memory protect unit.
MT8186 supports 32 regions and 16 domains.
We add basic driver currently, and will add more settings for
EMI MPU in next patch.
TEST=build pass
BUG=b:202871018
Signed-off-by: Penny Jan <penny.jan@mediatek.corp-partner.google.com>
Change-Id: Ia9e5030164e40e060a05e8f91d2ac88258c2e98e
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| c2d75fa7 | 22-Dec-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(errata): workaround for Cortex X2 erratum 2083908" into integration |
| f480c9c4 | 17-Dec-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(stm32mp1): correct include order" into integration |
| ff7675eb | 17-Dec-2021 |
Yann Gautier <yann.gautier@st.com> |
fix(stm32mp1): correct include order
Warnings about header files include order were triggered by CI.
Correct the include order to mathc CI requirements.
Change-Id: Iaca959add924e0e1fa2e56fab2348f0e
fix(stm32mp1): correct include order
Warnings about header files include order were triggered by CI.
Correct the include order to mathc CI requirements.
Change-Id: Iaca959add924e0e1fa2e56fab2348f0ee36e5fa7
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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