1# 2# Copyright (c) 2021, MediaTek Inc. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7MTK_PLAT := plat/mediatek 8MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} 9 10PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ 11 -I${MTK_PLAT}/common/drivers/gic600/ \ 12 -I${MTK_PLAT}/common/drivers/gpio/ \ 13 -I${MTK_PLAT}/common/drivers/timer/ \ 14 -I${MTK_PLAT_SOC}/drivers/dcm/ \ 15 -I${MTK_PLAT_SOC}/drivers/emi_mpu/ \ 16 -I${MTK_PLAT_SOC}/drivers/gpio/ \ 17 -I${MTK_PLAT_SOC}/drivers/pmic/ \ 18 -I${MTK_PLAT_SOC}/include/ 19 20GICV3_SUPPORT_GIC600 := 1 21include drivers/arm/gic/v3/gicv3.mk 22include lib/xlat_tables_v2/xlat_tables.mk 23 24PLAT_BL_COMMON_SOURCES := ${GICV3_SOURCES} \ 25 ${XLAT_TABLES_LIB_SRCS} \ 26 plat/common/aarch64/crash_console_helpers.S \ 27 plat/common/plat_psci_common.c 28 29 30BL31_SOURCES += common/desc_image_load.c \ 31 drivers/delay_timer/delay_timer.c \ 32 drivers/gpio/gpio.c \ 33 drivers/delay_timer/generic_delay_timer.c \ 34 drivers/ti/uart/aarch64/16550_console.S \ 35 lib/bl_aux_params/bl_aux_params.c \ 36 lib/cpus/aarch64/cortex_a55.S \ 37 lib/cpus/aarch64/cortex_a76.S \ 38 plat/common/plat_gicv3.c \ 39 ${MTK_PLAT}/common/drivers/gic600/mt_gic_v3.c \ 40 ${MTK_PLAT}/common/drivers/gpio/mtgpio_common.c \ 41 ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init.c \ 42 ${MTK_PLAT}/common/mtk_plat_common.c \ 43 ${MTK_PLAT}/common/mtk_sip_svc.c \ 44 ${MTK_PLAT}/common/params_setup.c \ 45 ${MTK_PLAT}/common/drivers/timer/mt_timer.c \ 46 ${MTK_PLAT}/common/mtk_cirq.c \ 47 ${MTK_PLAT_SOC}/aarch64/platform_common.c \ 48 ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ 49 ${MTK_PLAT_SOC}/bl31_plat_setup.c \ 50 ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \ 51 ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c \ 52 ${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \ 53 ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \ 54 ${MTK_PLAT_SOC}/drivers/pmic/pmic.c \ 55 ${MTK_PLAT_SOC}/plat_pm.c \ 56 ${MTK_PLAT_SOC}/plat_sip_calls.c \ 57 ${MTK_PLAT_SOC}/plat_topology.c 58 59# Configs for A76 and A55 60HW_ASSISTED_COHERENCY := 1 61USE_COHERENT_MEM := 0 62CTX_INCLUDE_AARCH32_REGS := 0 63ERRATA_A55_1530923 := 1 64ERRATA_A55_1221012 := 1 65 66# indicate the reset vector address can be programmed 67PROGRAMMABLE_RESET_ADDRESS := 1 68 69COLD_BOOT_SINGLE_CPU := 1 70 71MACH_MT8186 := 1 72$(eval $(call add_define,MACH_MT8186)) 73 74include lib/coreboot/coreboot.mk 75