1 /* 2 * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <stdio.h> 11 12 #include <libfdt.h> 13 14 #include <platform_def.h> 15 16 #include <arch.h> 17 #include <arch_helpers.h> 18 #include <common/debug.h> 19 #include <common/fdt_wrappers.h> 20 #include <drivers/clk.h> 21 #include <drivers/delay_timer.h> 22 #include <drivers/generic_delay_timer.h> 23 #include <drivers/st/stm32mp_clkfunc.h> 24 #include <drivers/st/stm32mp1_clk.h> 25 #include <drivers/st/stm32mp1_rcc.h> 26 #include <dt-bindings/clock/stm32mp1-clksrc.h> 27 #include <lib/mmio.h> 28 #include <lib/spinlock.h> 29 #include <lib/utils_def.h> 30 #include <plat/common/platform.h> 31 32 #define MAX_HSI_HZ 64000000 33 #define USB_PHY_48_MHZ 48000000 34 35 #define TIMEOUT_US_200MS U(200000) 36 #define TIMEOUT_US_1S U(1000000) 37 38 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 39 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 40 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 41 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS 42 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 43 44 const char *stm32mp_osc_node_label[NB_OSC] = { 45 [_LSI] = "clk-lsi", 46 [_LSE] = "clk-lse", 47 [_HSI] = "clk-hsi", 48 [_HSE] = "clk-hse", 49 [_CSI] = "clk-csi", 50 [_I2S_CKIN] = "i2s_ckin", 51 }; 52 53 enum stm32mp1_parent_id { 54 /* Oscillators are defined in enum stm32mp_osc_id */ 55 56 /* Other parent source */ 57 _HSI_KER = NB_OSC, 58 _HSE_KER, 59 _HSE_KER_DIV2, 60 _HSE_RTC, 61 _CSI_KER, 62 _PLL1_P, 63 _PLL1_Q, 64 _PLL1_R, 65 _PLL2_P, 66 _PLL2_Q, 67 _PLL2_R, 68 _PLL3_P, 69 _PLL3_Q, 70 _PLL3_R, 71 _PLL4_P, 72 _PLL4_Q, 73 _PLL4_R, 74 _ACLK, 75 _PCLK1, 76 _PCLK2, 77 _PCLK3, 78 _PCLK4, 79 _PCLK5, 80 _HCLK6, 81 _HCLK2, 82 _CK_PER, 83 _CK_MPU, 84 _CK_MCU, 85 _USB_PHY_48, 86 _PARENT_NB, 87 _UNKNOWN_ID = 0xff, 88 }; 89 90 /* Lists only the parent clock we are interested in */ 91 enum stm32mp1_parent_sel { 92 _I2C12_SEL, 93 _I2C35_SEL, 94 _STGEN_SEL, 95 _I2C46_SEL, 96 _SPI6_SEL, 97 _UART1_SEL, 98 _RNG1_SEL, 99 _UART6_SEL, 100 _UART24_SEL, 101 _UART35_SEL, 102 _UART78_SEL, 103 _SDMMC12_SEL, 104 _SDMMC3_SEL, 105 _QSPI_SEL, 106 _FMC_SEL, 107 _AXIS_SEL, 108 _MCUS_SEL, 109 _USBPHY_SEL, 110 _USBO_SEL, 111 _MPU_SEL, 112 _CKPER_SEL, 113 _RTC_SEL, 114 _PARENT_SEL_NB, 115 _UNKNOWN_SEL = 0xff, 116 }; 117 118 /* State the parent clock ID straight related to a clock */ 119 static const uint8_t parent_id_clock_id[_PARENT_NB] = { 120 [_HSE] = CK_HSE, 121 [_HSI] = CK_HSI, 122 [_CSI] = CK_CSI, 123 [_LSE] = CK_LSE, 124 [_LSI] = CK_LSI, 125 [_I2S_CKIN] = _UNKNOWN_ID, 126 [_USB_PHY_48] = _UNKNOWN_ID, 127 [_HSI_KER] = CK_HSI, 128 [_HSE_KER] = CK_HSE, 129 [_HSE_KER_DIV2] = CK_HSE_DIV2, 130 [_HSE_RTC] = _UNKNOWN_ID, 131 [_CSI_KER] = CK_CSI, 132 [_PLL1_P] = PLL1_P, 133 [_PLL1_Q] = PLL1_Q, 134 [_PLL1_R] = PLL1_R, 135 [_PLL2_P] = PLL2_P, 136 [_PLL2_Q] = PLL2_Q, 137 [_PLL2_R] = PLL2_R, 138 [_PLL3_P] = PLL3_P, 139 [_PLL3_Q] = PLL3_Q, 140 [_PLL3_R] = PLL3_R, 141 [_PLL4_P] = PLL4_P, 142 [_PLL4_Q] = PLL4_Q, 143 [_PLL4_R] = PLL4_R, 144 [_ACLK] = CK_AXI, 145 [_PCLK1] = CK_AXI, 146 [_PCLK2] = CK_AXI, 147 [_PCLK3] = CK_AXI, 148 [_PCLK4] = CK_AXI, 149 [_PCLK5] = CK_AXI, 150 [_CK_PER] = CK_PER, 151 [_CK_MPU] = CK_MPU, 152 [_CK_MCU] = CK_MCU, 153 }; 154 155 static unsigned int clock_id2parent_id(unsigned long id) 156 { 157 unsigned int n; 158 159 for (n = 0U; n < ARRAY_SIZE(parent_id_clock_id); n++) { 160 if (parent_id_clock_id[n] == id) { 161 return n; 162 } 163 } 164 165 return _UNKNOWN_ID; 166 } 167 168 enum stm32mp1_pll_id { 169 _PLL1, 170 _PLL2, 171 _PLL3, 172 _PLL4, 173 _PLL_NB 174 }; 175 176 enum stm32mp1_div_id { 177 _DIV_P, 178 _DIV_Q, 179 _DIV_R, 180 _DIV_NB, 181 }; 182 183 enum stm32mp1_clksrc_id { 184 CLKSRC_MPU, 185 CLKSRC_AXI, 186 CLKSRC_MCU, 187 CLKSRC_PLL12, 188 CLKSRC_PLL3, 189 CLKSRC_PLL4, 190 CLKSRC_RTC, 191 CLKSRC_MCO1, 192 CLKSRC_MCO2, 193 CLKSRC_NB 194 }; 195 196 enum stm32mp1_clkdiv_id { 197 CLKDIV_MPU, 198 CLKDIV_AXI, 199 CLKDIV_MCU, 200 CLKDIV_APB1, 201 CLKDIV_APB2, 202 CLKDIV_APB3, 203 CLKDIV_APB4, 204 CLKDIV_APB5, 205 CLKDIV_RTC, 206 CLKDIV_MCO1, 207 CLKDIV_MCO2, 208 CLKDIV_NB 209 }; 210 211 enum stm32mp1_pllcfg { 212 PLLCFG_M, 213 PLLCFG_N, 214 PLLCFG_P, 215 PLLCFG_Q, 216 PLLCFG_R, 217 PLLCFG_O, 218 PLLCFG_NB 219 }; 220 221 enum stm32mp1_pllcsg { 222 PLLCSG_MOD_PER, 223 PLLCSG_INC_STEP, 224 PLLCSG_SSCG_MODE, 225 PLLCSG_NB 226 }; 227 228 enum stm32mp1_plltype { 229 PLL_800, 230 PLL_1600, 231 PLL_TYPE_NB 232 }; 233 234 struct stm32mp1_pll { 235 uint8_t refclk_min; 236 uint8_t refclk_max; 237 uint8_t divn_max; 238 }; 239 240 struct stm32mp1_clk_gate { 241 uint16_t offset; 242 uint8_t bit; 243 uint8_t index; 244 uint8_t set_clr; 245 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 246 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 247 }; 248 249 struct stm32mp1_clk_sel { 250 uint16_t offset; 251 uint8_t src; 252 uint8_t msk; 253 uint8_t nb_parent; 254 const uint8_t *parent; 255 }; 256 257 #define REFCLK_SIZE 4 258 struct stm32mp1_clk_pll { 259 enum stm32mp1_plltype plltype; 260 uint16_t rckxselr; 261 uint16_t pllxcfgr1; 262 uint16_t pllxcfgr2; 263 uint16_t pllxfracr; 264 uint16_t pllxcr; 265 uint16_t pllxcsgr; 266 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 267 }; 268 269 /* Clocks with selectable source and non set/clr register access */ 270 #define _CLK_SELEC(off, b, idx, s) \ 271 { \ 272 .offset = (off), \ 273 .bit = (b), \ 274 .index = (idx), \ 275 .set_clr = 0, \ 276 .sel = (s), \ 277 .fixed = _UNKNOWN_ID, \ 278 } 279 280 /* Clocks with fixed source and non set/clr register access */ 281 #define _CLK_FIXED(off, b, idx, f) \ 282 { \ 283 .offset = (off), \ 284 .bit = (b), \ 285 .index = (idx), \ 286 .set_clr = 0, \ 287 .sel = _UNKNOWN_SEL, \ 288 .fixed = (f), \ 289 } 290 291 /* Clocks with selectable source and set/clr register access */ 292 #define _CLK_SC_SELEC(off, b, idx, s) \ 293 { \ 294 .offset = (off), \ 295 .bit = (b), \ 296 .index = (idx), \ 297 .set_clr = 1, \ 298 .sel = (s), \ 299 .fixed = _UNKNOWN_ID, \ 300 } 301 302 /* Clocks with fixed source and set/clr register access */ 303 #define _CLK_SC_FIXED(off, b, idx, f) \ 304 { \ 305 .offset = (off), \ 306 .bit = (b), \ 307 .index = (idx), \ 308 .set_clr = 1, \ 309 .sel = _UNKNOWN_SEL, \ 310 .fixed = (f), \ 311 } 312 313 #define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \ 314 [_ ## _label ## _SEL] = { \ 315 .offset = _rcc_selr, \ 316 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \ 317 .msk = (_rcc_selr ## _ ## _label ## SRC_MASK) >> \ 318 (_rcc_selr ## _ ## _label ## SRC_SHIFT), \ 319 .parent = (_parents), \ 320 .nb_parent = ARRAY_SIZE(_parents) \ 321 } 322 323 #define _CLK_PLL(idx, type, off1, off2, off3, \ 324 off4, off5, off6, \ 325 p1, p2, p3, p4) \ 326 [(idx)] = { \ 327 .plltype = (type), \ 328 .rckxselr = (off1), \ 329 .pllxcfgr1 = (off2), \ 330 .pllxcfgr2 = (off3), \ 331 .pllxfracr = (off4), \ 332 .pllxcr = (off5), \ 333 .pllxcsgr = (off6), \ 334 .refclk[0] = (p1), \ 335 .refclk[1] = (p2), \ 336 .refclk[2] = (p3), \ 337 .refclk[3] = (p4), \ 338 } 339 340 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 341 342 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 343 _CLK_FIXED(RCC_DDRITFCR, 0, DDRC1, _ACLK), 344 _CLK_FIXED(RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 345 _CLK_FIXED(RCC_DDRITFCR, 2, DDRC2, _ACLK), 346 _CLK_FIXED(RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 347 _CLK_FIXED(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 348 _CLK_FIXED(RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 349 _CLK_FIXED(RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 350 _CLK_FIXED(RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 351 _CLK_FIXED(RCC_DDRITFCR, 8, AXIDCG, _ACLK), 352 _CLK_FIXED(RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 353 _CLK_FIXED(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 354 355 _CLK_SC_FIXED(RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 356 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 357 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 358 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 359 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 360 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 361 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 362 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 363 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 364 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 365 _CLK_SC_SELEC(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 366 367 _CLK_SC_FIXED(RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 368 _CLK_SC_SELEC(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 369 370 _CLK_SC_FIXED(RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 371 372 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 373 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 374 _CLK_SC_SELEC(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 375 376 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), 377 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 378 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), 379 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL), 380 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), 381 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), 382 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), 383 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5), 384 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5), 385 _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5), 386 _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 387 388 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 389 _CLK_SC_SELEC(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 390 391 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 392 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 393 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 394 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 395 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 396 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 397 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 398 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 399 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 400 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 401 _CLK_SC_SELEC(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 402 403 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5), 404 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5), 405 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5), 406 _CLK_SC_SELEC(RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL), 407 _CLK_SC_FIXED(RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5), 408 409 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 410 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 411 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 412 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 413 _CLK_SC_SELEC(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 414 415 _CLK_SELEC(RCC_BDCR, 20, RTC, _RTC_SEL), 416 _CLK_SELEC(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 417 }; 418 419 static const uint8_t i2c12_parents[] = { 420 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 421 }; 422 423 static const uint8_t i2c35_parents[] = { 424 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 425 }; 426 427 static const uint8_t stgen_parents[] = { 428 _HSI_KER, _HSE_KER 429 }; 430 431 static const uint8_t i2c46_parents[] = { 432 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 433 }; 434 435 static const uint8_t spi6_parents[] = { 436 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 437 }; 438 439 static const uint8_t usart1_parents[] = { 440 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 441 }; 442 443 static const uint8_t rng1_parents[] = { 444 _CSI, _PLL4_R, _LSE, _LSI 445 }; 446 447 static const uint8_t uart6_parents[] = { 448 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 449 }; 450 451 static const uint8_t uart234578_parents[] = { 452 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 453 }; 454 455 static const uint8_t sdmmc12_parents[] = { 456 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER 457 }; 458 459 static const uint8_t sdmmc3_parents[] = { 460 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER 461 }; 462 463 static const uint8_t qspi_parents[] = { 464 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 465 }; 466 467 static const uint8_t fmc_parents[] = { 468 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 469 }; 470 471 static const uint8_t axiss_parents[] = { 472 _HSI, _HSE, _PLL2_P 473 }; 474 475 static const uint8_t mcuss_parents[] = { 476 _HSI, _HSE, _CSI, _PLL3_P 477 }; 478 479 static const uint8_t usbphy_parents[] = { 480 _HSE_KER, _PLL4_R, _HSE_KER_DIV2 481 }; 482 483 static const uint8_t usbo_parents[] = { 484 _PLL4_R, _USB_PHY_48 485 }; 486 487 static const uint8_t mpu_parents[] = { 488 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */ 489 }; 490 491 static const uint8_t per_parents[] = { 492 _HSI, _HSE, _CSI, 493 }; 494 495 static const uint8_t rtc_parents[] = { 496 _UNKNOWN_ID, _LSE, _LSI, _HSE_RTC 497 }; 498 499 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 500 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents), 501 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents), 502 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents), 503 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents), 504 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents), 505 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents), 506 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents), 507 _CLK_PARENT_SEL(MPU, RCC_MPCKSELR, mpu_parents), 508 _CLK_PARENT_SEL(CKPER, RCC_CPERCKSELR, per_parents), 509 _CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents), 510 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents), 511 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents), 512 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents), 513 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents), 514 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents), 515 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents), 516 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents), 517 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents), 518 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, axiss_parents), 519 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mcuss_parents), 520 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents), 521 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents), 522 }; 523 524 /* Define characteristic of PLL according type */ 525 #define DIVN_MIN 24 526 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 527 [PLL_800] = { 528 .refclk_min = 4, 529 .refclk_max = 16, 530 .divn_max = 99, 531 }, 532 [PLL_1600] = { 533 .refclk_min = 8, 534 .refclk_max = 16, 535 .divn_max = 199, 536 }, 537 }; 538 539 /* PLLNCFGR2 register divider by output */ 540 static const uint8_t pllncfgr2[_DIV_NB] = { 541 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 542 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 543 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 544 }; 545 546 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 547 _CLK_PLL(_PLL1, PLL_1600, 548 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 549 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 550 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 551 _CLK_PLL(_PLL2, PLL_1600, 552 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 553 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 554 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 555 _CLK_PLL(_PLL3, PLL_800, 556 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 557 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 558 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 559 _CLK_PLL(_PLL4, PLL_800, 560 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 561 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 562 _HSI, _HSE, _CSI, _I2S_CKIN), 563 }; 564 565 /* Prescaler table lookups for clock computation */ 566 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 567 static const uint8_t stm32mp1_mcu_div[16] = { 568 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 569 }; 570 571 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 572 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 573 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 574 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 575 0, 1, 2, 3, 4, 4, 4, 4 576 }; 577 578 /* div = /1 /2 /3 /4 */ 579 static const uint8_t stm32mp1_axi_div[8] = { 580 1, 2, 3, 4, 4, 4, 4, 4 581 }; 582 583 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] __unused = { 584 [_HSI] = "HSI", 585 [_HSE] = "HSE", 586 [_CSI] = "CSI", 587 [_LSI] = "LSI", 588 [_LSE] = "LSE", 589 [_I2S_CKIN] = "I2S_CKIN", 590 [_HSI_KER] = "HSI_KER", 591 [_HSE_KER] = "HSE_KER", 592 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 593 [_HSE_RTC] = "HSE_RTC", 594 [_CSI_KER] = "CSI_KER", 595 [_PLL1_P] = "PLL1_P", 596 [_PLL1_Q] = "PLL1_Q", 597 [_PLL1_R] = "PLL1_R", 598 [_PLL2_P] = "PLL2_P", 599 [_PLL2_Q] = "PLL2_Q", 600 [_PLL2_R] = "PLL2_R", 601 [_PLL3_P] = "PLL3_P", 602 [_PLL3_Q] = "PLL3_Q", 603 [_PLL3_R] = "PLL3_R", 604 [_PLL4_P] = "PLL4_P", 605 [_PLL4_Q] = "PLL4_Q", 606 [_PLL4_R] = "PLL4_R", 607 [_ACLK] = "ACLK", 608 [_PCLK1] = "PCLK1", 609 [_PCLK2] = "PCLK2", 610 [_PCLK3] = "PCLK3", 611 [_PCLK4] = "PCLK4", 612 [_PCLK5] = "PCLK5", 613 [_HCLK6] = "KCLK6", 614 [_HCLK2] = "HCLK2", 615 [_CK_PER] = "CK_PER", 616 [_CK_MPU] = "CK_MPU", 617 [_CK_MCU] = "CK_MCU", 618 [_USB_PHY_48] = "USB_PHY_48", 619 }; 620 621 /* RCC clock device driver private */ 622 static unsigned long stm32mp1_osc[NB_OSC]; 623 static struct spinlock reg_lock; 624 static unsigned int gate_refcounts[NB_GATES]; 625 static struct spinlock refcount_lock; 626 627 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 628 { 629 return &stm32mp1_clk_gate[idx]; 630 } 631 632 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 633 { 634 return &stm32mp1_clk_sel[idx]; 635 } 636 637 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 638 { 639 return &stm32mp1_clk_pll[idx]; 640 } 641 642 static void stm32mp1_clk_lock(struct spinlock *lock) 643 { 644 if (stm32mp_lock_available()) { 645 /* Assume interrupts are masked */ 646 spin_lock(lock); 647 } 648 } 649 650 static void stm32mp1_clk_unlock(struct spinlock *lock) 651 { 652 if (stm32mp_lock_available()) { 653 spin_unlock(lock); 654 } 655 } 656 657 bool stm32mp1_rcc_is_secure(void) 658 { 659 uintptr_t rcc_base = stm32mp_rcc_base(); 660 uint32_t mask = RCC_TZCR_TZEN; 661 662 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 663 } 664 665 bool stm32mp1_rcc_is_mckprot(void) 666 { 667 uintptr_t rcc_base = stm32mp_rcc_base(); 668 uint32_t mask = RCC_TZCR_TZEN | RCC_TZCR_MCKPROT; 669 670 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 671 } 672 673 void stm32mp1_clk_rcc_regs_lock(void) 674 { 675 stm32mp1_clk_lock(®_lock); 676 } 677 678 void stm32mp1_clk_rcc_regs_unlock(void) 679 { 680 stm32mp1_clk_unlock(®_lock); 681 } 682 683 static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx) 684 { 685 if (idx >= NB_OSC) { 686 return 0; 687 } 688 689 return stm32mp1_osc[idx]; 690 } 691 692 static int stm32mp1_clk_get_gated_id(unsigned long id) 693 { 694 unsigned int i; 695 696 for (i = 0U; i < NB_GATES; i++) { 697 if (gate_ref(i)->index == id) { 698 return i; 699 } 700 } 701 702 ERROR("%s: clk id %d not found\n", __func__, (uint32_t)id); 703 704 return -EINVAL; 705 } 706 707 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 708 { 709 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel); 710 } 711 712 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 713 { 714 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed); 715 } 716 717 static int stm32mp1_clk_get_parent(unsigned long id) 718 { 719 const struct stm32mp1_clk_sel *sel; 720 uint32_t p_sel; 721 int i; 722 enum stm32mp1_parent_id p; 723 enum stm32mp1_parent_sel s; 724 uintptr_t rcc_base = stm32mp_rcc_base(); 725 726 /* Few non gateable clock have a static parent ID, find them */ 727 i = (int)clock_id2parent_id(id); 728 if (i != _UNKNOWN_ID) { 729 return i; 730 } 731 732 i = stm32mp1_clk_get_gated_id(id); 733 if (i < 0) { 734 panic(); 735 } 736 737 p = stm32mp1_clk_get_fixed_parent(i); 738 if (p < _PARENT_NB) { 739 return (int)p; 740 } 741 742 s = stm32mp1_clk_get_sel(i); 743 if (s == _UNKNOWN_SEL) { 744 return -EINVAL; 745 } 746 if (s >= _PARENT_SEL_NB) { 747 panic(); 748 } 749 750 sel = clk_sel_ref(s); 751 p_sel = (mmio_read_32(rcc_base + sel->offset) & 752 (sel->msk << sel->src)) >> sel->src; 753 if (p_sel < sel->nb_parent) { 754 return (int)sel->parent[p_sel]; 755 } 756 757 return -EINVAL; 758 } 759 760 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 761 { 762 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); 763 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 764 765 return stm32mp1_clk_get_fixed(pll->refclk[src]); 766 } 767 768 /* 769 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 770 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 771 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 772 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 773 */ 774 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 775 { 776 unsigned long refclk, fvco; 777 uint32_t cfgr1, fracr, divm, divn; 778 uintptr_t rcc_base = stm32mp_rcc_base(); 779 780 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); 781 fracr = mmio_read_32(rcc_base + pll->pllxfracr); 782 783 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 784 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 785 786 refclk = stm32mp1_pll_get_fref(pll); 787 788 /* 789 * With FRACV : 790 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 791 * Without FRACV 792 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 793 */ 794 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 795 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 796 RCC_PLLNFRACR_FRACV_SHIFT; 797 unsigned long long numerator, denominator; 798 799 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 800 numerator = refclk * numerator; 801 denominator = ((unsigned long long)divm + 1U) << 13; 802 fvco = (unsigned long)(numerator / denominator); 803 } else { 804 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 805 } 806 807 return fvco; 808 } 809 810 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 811 enum stm32mp1_div_id div_id) 812 { 813 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 814 unsigned long dfout; 815 uint32_t cfgr2, divy; 816 817 if (div_id >= _DIV_NB) { 818 return 0; 819 } 820 821 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); 822 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 823 824 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 825 826 return dfout; 827 } 828 829 static unsigned long get_clock_rate(int p) 830 { 831 uint32_t reg, clkdiv; 832 unsigned long clock = 0; 833 uintptr_t rcc_base = stm32mp_rcc_base(); 834 835 switch (p) { 836 case _CK_MPU: 837 /* MPU sub system */ 838 reg = mmio_read_32(rcc_base + RCC_MPCKSELR); 839 switch (reg & RCC_SELR_SRC_MASK) { 840 case RCC_MPCKSELR_HSI: 841 clock = stm32mp1_clk_get_fixed(_HSI); 842 break; 843 case RCC_MPCKSELR_HSE: 844 clock = stm32mp1_clk_get_fixed(_HSE); 845 break; 846 case RCC_MPCKSELR_PLL: 847 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 848 break; 849 case RCC_MPCKSELR_PLL_MPUDIV: 850 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 851 852 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR); 853 clkdiv = reg & RCC_MPUDIV_MASK; 854 clock >>= stm32mp1_mpu_div[clkdiv]; 855 break; 856 default: 857 break; 858 } 859 break; 860 /* AXI sub system */ 861 case _ACLK: 862 case _HCLK2: 863 case _HCLK6: 864 case _PCLK4: 865 case _PCLK5: 866 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR); 867 switch (reg & RCC_SELR_SRC_MASK) { 868 case RCC_ASSCKSELR_HSI: 869 clock = stm32mp1_clk_get_fixed(_HSI); 870 break; 871 case RCC_ASSCKSELR_HSE: 872 clock = stm32mp1_clk_get_fixed(_HSE); 873 break; 874 case RCC_ASSCKSELR_PLL: 875 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 876 break; 877 default: 878 break; 879 } 880 881 /* System clock divider */ 882 reg = mmio_read_32(rcc_base + RCC_AXIDIVR); 883 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 884 885 switch (p) { 886 case _PCLK4: 887 reg = mmio_read_32(rcc_base + RCC_APB4DIVR); 888 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 889 break; 890 case _PCLK5: 891 reg = mmio_read_32(rcc_base + RCC_APB5DIVR); 892 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 893 break; 894 default: 895 break; 896 } 897 break; 898 /* MCU sub system */ 899 case _CK_MCU: 900 case _PCLK1: 901 case _PCLK2: 902 case _PCLK3: 903 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR); 904 switch (reg & RCC_SELR_SRC_MASK) { 905 case RCC_MSSCKSELR_HSI: 906 clock = stm32mp1_clk_get_fixed(_HSI); 907 break; 908 case RCC_MSSCKSELR_HSE: 909 clock = stm32mp1_clk_get_fixed(_HSE); 910 break; 911 case RCC_MSSCKSELR_CSI: 912 clock = stm32mp1_clk_get_fixed(_CSI); 913 break; 914 case RCC_MSSCKSELR_PLL: 915 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 916 break; 917 default: 918 break; 919 } 920 921 /* MCU clock divider */ 922 reg = mmio_read_32(rcc_base + RCC_MCUDIVR); 923 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 924 925 switch (p) { 926 case _PCLK1: 927 reg = mmio_read_32(rcc_base + RCC_APB1DIVR); 928 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 929 break; 930 case _PCLK2: 931 reg = mmio_read_32(rcc_base + RCC_APB2DIVR); 932 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 933 break; 934 case _PCLK3: 935 reg = mmio_read_32(rcc_base + RCC_APB3DIVR); 936 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 937 break; 938 case _CK_MCU: 939 default: 940 break; 941 } 942 break; 943 case _CK_PER: 944 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR); 945 switch (reg & RCC_SELR_SRC_MASK) { 946 case RCC_CPERCKSELR_HSI: 947 clock = stm32mp1_clk_get_fixed(_HSI); 948 break; 949 case RCC_CPERCKSELR_HSE: 950 clock = stm32mp1_clk_get_fixed(_HSE); 951 break; 952 case RCC_CPERCKSELR_CSI: 953 clock = stm32mp1_clk_get_fixed(_CSI); 954 break; 955 default: 956 break; 957 } 958 break; 959 case _HSI: 960 case _HSI_KER: 961 clock = stm32mp1_clk_get_fixed(_HSI); 962 break; 963 case _CSI: 964 case _CSI_KER: 965 clock = stm32mp1_clk_get_fixed(_CSI); 966 break; 967 case _HSE: 968 case _HSE_KER: 969 clock = stm32mp1_clk_get_fixed(_HSE); 970 break; 971 case _HSE_KER_DIV2: 972 clock = stm32mp1_clk_get_fixed(_HSE) >> 1; 973 break; 974 case _HSE_RTC: 975 clock = stm32mp1_clk_get_fixed(_HSE); 976 clock /= (mmio_read_32(rcc_base + RCC_RTCDIVR) & RCC_DIVR_DIV_MASK) + 1U; 977 break; 978 case _LSI: 979 clock = stm32mp1_clk_get_fixed(_LSI); 980 break; 981 case _LSE: 982 clock = stm32mp1_clk_get_fixed(_LSE); 983 break; 984 /* PLL */ 985 case _PLL1_P: 986 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 987 break; 988 case _PLL1_Q: 989 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 990 break; 991 case _PLL1_R: 992 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 993 break; 994 case _PLL2_P: 995 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 996 break; 997 case _PLL2_Q: 998 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 999 break; 1000 case _PLL2_R: 1001 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 1002 break; 1003 case _PLL3_P: 1004 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 1005 break; 1006 case _PLL3_Q: 1007 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 1008 break; 1009 case _PLL3_R: 1010 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 1011 break; 1012 case _PLL4_P: 1013 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 1014 break; 1015 case _PLL4_Q: 1016 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 1017 break; 1018 case _PLL4_R: 1019 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 1020 break; 1021 /* Other */ 1022 case _USB_PHY_48: 1023 clock = USB_PHY_48_MHZ; 1024 break; 1025 default: 1026 break; 1027 } 1028 1029 return clock; 1030 } 1031 1032 static void __clk_enable(struct stm32mp1_clk_gate const *gate) 1033 { 1034 uintptr_t rcc_base = stm32mp_rcc_base(); 1035 1036 VERBOSE("Enable clock %u\n", gate->index); 1037 1038 if (gate->set_clr != 0U) { 1039 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); 1040 } else { 1041 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1042 } 1043 } 1044 1045 static void __clk_disable(struct stm32mp1_clk_gate const *gate) 1046 { 1047 uintptr_t rcc_base = stm32mp_rcc_base(); 1048 1049 VERBOSE("Disable clock %u\n", gate->index); 1050 1051 if (gate->set_clr != 0U) { 1052 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET, 1053 BIT(gate->bit)); 1054 } else { 1055 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1056 } 1057 } 1058 1059 static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate) 1060 { 1061 uintptr_t rcc_base = stm32mp_rcc_base(); 1062 1063 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit); 1064 } 1065 1066 unsigned int stm32mp1_clk_get_refcount(unsigned long id) 1067 { 1068 int i = stm32mp1_clk_get_gated_id(id); 1069 1070 if (i < 0) { 1071 panic(); 1072 } 1073 1074 return gate_refcounts[i]; 1075 } 1076 1077 /* Oscillators and PLLs are not gated at runtime */ 1078 static bool clock_is_always_on(unsigned long id) 1079 { 1080 switch (id) { 1081 case CK_HSE: 1082 case CK_CSI: 1083 case CK_LSI: 1084 case CK_LSE: 1085 case CK_HSI: 1086 case CK_HSE_DIV2: 1087 case PLL1_Q: 1088 case PLL1_R: 1089 case PLL2_P: 1090 case PLL2_Q: 1091 case PLL2_R: 1092 case PLL3_P: 1093 case PLL3_Q: 1094 case PLL3_R: 1095 case CK_AXI: 1096 case CK_MPU: 1097 case CK_MCU: 1098 case RTC: 1099 return true; 1100 default: 1101 return false; 1102 } 1103 } 1104 1105 void __stm32mp1_clk_enable(unsigned long id, bool secure) 1106 { 1107 const struct stm32mp1_clk_gate *gate; 1108 int i; 1109 unsigned int *refcnt; 1110 1111 if (clock_is_always_on(id)) { 1112 return; 1113 } 1114 1115 i = stm32mp1_clk_get_gated_id(id); 1116 if (i < 0) { 1117 ERROR("Clock %d can't be enabled\n", (uint32_t)id); 1118 panic(); 1119 } 1120 1121 gate = gate_ref(i); 1122 refcnt = &gate_refcounts[i]; 1123 1124 stm32mp1_clk_lock(&refcount_lock); 1125 1126 if (stm32mp_incr_shrefcnt(refcnt, secure) != 0) { 1127 __clk_enable(gate); 1128 } 1129 1130 stm32mp1_clk_unlock(&refcount_lock); 1131 } 1132 1133 void __stm32mp1_clk_disable(unsigned long id, bool secure) 1134 { 1135 const struct stm32mp1_clk_gate *gate; 1136 int i; 1137 unsigned int *refcnt; 1138 1139 if (clock_is_always_on(id)) { 1140 return; 1141 } 1142 1143 i = stm32mp1_clk_get_gated_id(id); 1144 if (i < 0) { 1145 ERROR("Clock %d can't be disabled\n", (uint32_t)id); 1146 panic(); 1147 } 1148 1149 gate = gate_ref(i); 1150 refcnt = &gate_refcounts[i]; 1151 1152 stm32mp1_clk_lock(&refcount_lock); 1153 1154 if (stm32mp_decr_shrefcnt(refcnt, secure) != 0) { 1155 __clk_disable(gate); 1156 } 1157 1158 stm32mp1_clk_unlock(&refcount_lock); 1159 } 1160 1161 static int stm32mp_clk_enable(unsigned long id) 1162 { 1163 __stm32mp1_clk_enable(id, true); 1164 1165 return 0; 1166 } 1167 1168 static void stm32mp_clk_disable(unsigned long id) 1169 { 1170 __stm32mp1_clk_disable(id, true); 1171 } 1172 1173 static bool stm32mp_clk_is_enabled(unsigned long id) 1174 { 1175 int i; 1176 1177 if (clock_is_always_on(id)) { 1178 return true; 1179 } 1180 1181 i = stm32mp1_clk_get_gated_id(id); 1182 if (i < 0) { 1183 panic(); 1184 } 1185 1186 return __clk_is_enabled(gate_ref(i)); 1187 } 1188 1189 static unsigned long stm32mp_clk_get_rate(unsigned long id) 1190 { 1191 uintptr_t rcc_base = stm32mp_rcc_base(); 1192 int p = stm32mp1_clk_get_parent(id); 1193 uint32_t prescaler, timpre; 1194 unsigned long parent_rate; 1195 1196 if (p < 0) { 1197 return 0; 1198 } 1199 1200 parent_rate = get_clock_rate(p); 1201 1202 switch (id) { 1203 case TIM2_K: 1204 case TIM3_K: 1205 case TIM4_K: 1206 case TIM5_K: 1207 case TIM6_K: 1208 case TIM7_K: 1209 case TIM12_K: 1210 case TIM13_K: 1211 case TIM14_K: 1212 prescaler = mmio_read_32(rcc_base + RCC_APB1DIVR) & 1213 RCC_APBXDIV_MASK; 1214 timpre = mmio_read_32(rcc_base + RCC_TIMG1PRER) & 1215 RCC_TIMGXPRER_TIMGXPRE; 1216 break; 1217 1218 case TIM1_K: 1219 case TIM8_K: 1220 case TIM15_K: 1221 case TIM16_K: 1222 case TIM17_K: 1223 prescaler = mmio_read_32(rcc_base + RCC_APB2DIVR) & 1224 RCC_APBXDIV_MASK; 1225 timpre = mmio_read_32(rcc_base + RCC_TIMG2PRER) & 1226 RCC_TIMGXPRER_TIMGXPRE; 1227 break; 1228 1229 default: 1230 return parent_rate; 1231 } 1232 1233 if (prescaler == 0U) { 1234 return parent_rate; 1235 } 1236 1237 return parent_rate * (timpre + 1U) * 2U; 1238 } 1239 1240 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on) 1241 { 1242 uintptr_t address = stm32mp_rcc_base() + offset; 1243 1244 if (enable) { 1245 mmio_setbits_32(address, mask_on); 1246 } else { 1247 mmio_clrbits_32(address, mask_on); 1248 } 1249 } 1250 1251 static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on) 1252 { 1253 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR; 1254 uintptr_t address = stm32mp_rcc_base() + offset; 1255 1256 mmio_write_32(address, mask_on); 1257 } 1258 1259 static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy) 1260 { 1261 uint64_t timeout; 1262 uint32_t mask_test; 1263 uintptr_t address = stm32mp_rcc_base() + offset; 1264 1265 if (enable) { 1266 mask_test = mask_rdy; 1267 } else { 1268 mask_test = 0; 1269 } 1270 1271 timeout = timeout_init_us(OSCRDY_TIMEOUT); 1272 while ((mmio_read_32(address) & mask_rdy) != mask_test) { 1273 if (timeout_elapsed(timeout)) { 1274 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n", 1275 mask_rdy, address, enable, mmio_read_32(address)); 1276 return -ETIMEDOUT; 1277 } 1278 } 1279 1280 return 0; 1281 } 1282 1283 static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv) 1284 { 1285 uint32_t value; 1286 uintptr_t rcc_base = stm32mp_rcc_base(); 1287 1288 if (digbyp) { 1289 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); 1290 } 1291 1292 if (bypass || digbyp) { 1293 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); 1294 } 1295 1296 /* 1297 * Warning: not recommended to switch directly from "high drive" 1298 * to "medium low drive", and vice-versa. 1299 */ 1300 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> 1301 RCC_BDCR_LSEDRV_SHIFT; 1302 1303 while (value != lsedrv) { 1304 if (value > lsedrv) { 1305 value--; 1306 } else { 1307 value++; 1308 } 1309 1310 mmio_clrsetbits_32(rcc_base + RCC_BDCR, 1311 RCC_BDCR_LSEDRV_MASK, 1312 value << RCC_BDCR_LSEDRV_SHIFT); 1313 } 1314 1315 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); 1316 } 1317 1318 static void stm32mp1_lse_wait(void) 1319 { 1320 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { 1321 VERBOSE("%s: failed\n", __func__); 1322 } 1323 } 1324 1325 static void stm32mp1_lsi_set(bool enable) 1326 { 1327 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION); 1328 1329 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) { 1330 VERBOSE("%s: failed\n", __func__); 1331 } 1332 } 1333 1334 static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css) 1335 { 1336 uintptr_t rcc_base = stm32mp_rcc_base(); 1337 1338 if (digbyp) { 1339 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP); 1340 } 1341 1342 if (bypass || digbyp) { 1343 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP); 1344 } 1345 1346 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON); 1347 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) { 1348 VERBOSE("%s: failed\n", __func__); 1349 } 1350 1351 if (css) { 1352 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON); 1353 } 1354 } 1355 1356 static void stm32mp1_csi_set(bool enable) 1357 { 1358 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION); 1359 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) { 1360 VERBOSE("%s: failed\n", __func__); 1361 } 1362 } 1363 1364 static void stm32mp1_hsi_set(bool enable) 1365 { 1366 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION); 1367 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) { 1368 VERBOSE("%s: failed\n", __func__); 1369 } 1370 } 1371 1372 static int stm32mp1_set_hsidiv(uint8_t hsidiv) 1373 { 1374 uint64_t timeout; 1375 uintptr_t rcc_base = stm32mp_rcc_base(); 1376 uintptr_t address = rcc_base + RCC_OCRDYR; 1377 1378 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, 1379 RCC_HSICFGR_HSIDIV_MASK, 1380 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 1381 1382 timeout = timeout_init_us(HSIDIV_TIMEOUT); 1383 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 1384 if (timeout_elapsed(timeout)) { 1385 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", 1386 address, mmio_read_32(address)); 1387 return -ETIMEDOUT; 1388 } 1389 } 1390 1391 return 0; 1392 } 1393 1394 static int stm32mp1_hsidiv(unsigned long hsifreq) 1395 { 1396 uint8_t hsidiv; 1397 uint32_t hsidivfreq = MAX_HSI_HZ; 1398 1399 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1400 if (hsidivfreq == hsifreq) { 1401 break; 1402 } 1403 1404 hsidivfreq /= 2U; 1405 } 1406 1407 if (hsidiv == 4U) { 1408 ERROR("Invalid clk-hsi frequency\n"); 1409 return -1; 1410 } 1411 1412 if (hsidiv != 0U) { 1413 return stm32mp1_set_hsidiv(hsidiv); 1414 } 1415 1416 return 0; 1417 } 1418 1419 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id, 1420 unsigned int clksrc, 1421 uint32_t *pllcfg, int plloff) 1422 { 1423 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1424 uintptr_t rcc_base = stm32mp_rcc_base(); 1425 uintptr_t pllxcr = rcc_base + pll->pllxcr; 1426 enum stm32mp1_plltype type = pll->plltype; 1427 uintptr_t clksrc_address = rcc_base + (clksrc >> 4); 1428 unsigned long refclk; 1429 uint32_t ifrge = 0U; 1430 uint32_t src, value, fracv = 0; 1431 void *fdt; 1432 1433 /* Check PLL output */ 1434 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) { 1435 return false; 1436 } 1437 1438 /* Check current clksrc */ 1439 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK; 1440 if (src != (clksrc & RCC_SELR_SRC_MASK)) { 1441 return false; 1442 } 1443 1444 /* Check Div */ 1445 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK; 1446 1447 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1448 (pllcfg[PLLCFG_M] + 1U); 1449 1450 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1451 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1452 return false; 1453 } 1454 1455 if ((type == PLL_800) && (refclk >= 8000000U)) { 1456 ifrge = 1U; 1457 } 1458 1459 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1460 RCC_PLLNCFGR1_DIVN_MASK; 1461 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1462 RCC_PLLNCFGR1_DIVM_MASK; 1463 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1464 RCC_PLLNCFGR1_IFRGE_MASK; 1465 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) { 1466 return false; 1467 } 1468 1469 /* Fractional configuration */ 1470 if (fdt_get_address(&fdt) == 1) { 1471 fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0); 1472 } 1473 1474 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1475 value |= RCC_PLLNFRACR_FRACLE; 1476 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) { 1477 return false; 1478 } 1479 1480 /* Output config */ 1481 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1482 RCC_PLLNCFGR2_DIVP_MASK; 1483 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1484 RCC_PLLNCFGR2_DIVQ_MASK; 1485 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1486 RCC_PLLNCFGR2_DIVR_MASK; 1487 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) { 1488 return false; 1489 } 1490 1491 return true; 1492 } 1493 1494 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) 1495 { 1496 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1497 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1498 1499 /* Preserve RCC_PLLNCR_SSCG_CTRL value */ 1500 mmio_clrsetbits_32(pllxcr, 1501 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1502 RCC_PLLNCR_DIVREN, 1503 RCC_PLLNCR_PLLON); 1504 } 1505 1506 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) 1507 { 1508 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1509 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1510 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1511 1512 /* Wait PLL lock */ 1513 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { 1514 if (timeout_elapsed(timeout)) { 1515 ERROR("PLL%d start failed @ 0x%lx: 0x%x\n", 1516 pll_id, pllxcr, mmio_read_32(pllxcr)); 1517 return -ETIMEDOUT; 1518 } 1519 } 1520 1521 /* Start the requested output */ 1522 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1523 1524 return 0; 1525 } 1526 1527 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id) 1528 { 1529 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1530 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1531 uint64_t timeout; 1532 1533 /* Stop all output */ 1534 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1535 RCC_PLLNCR_DIVREN); 1536 1537 /* Stop PLL */ 1538 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); 1539 1540 timeout = timeout_init_us(PLLRDY_TIMEOUT); 1541 /* Wait PLL stopped */ 1542 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { 1543 if (timeout_elapsed(timeout)) { 1544 ERROR("PLL%d stop failed @ 0x%lx: 0x%x\n", 1545 pll_id, pllxcr, mmio_read_32(pllxcr)); 1546 return -ETIMEDOUT; 1547 } 1548 } 1549 1550 return 0; 1551 } 1552 1553 static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id, 1554 uint32_t *pllcfg) 1555 { 1556 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1557 uintptr_t rcc_base = stm32mp_rcc_base(); 1558 uint32_t value; 1559 1560 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1561 RCC_PLLNCFGR2_DIVP_MASK; 1562 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1563 RCC_PLLNCFGR2_DIVQ_MASK; 1564 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1565 RCC_PLLNCFGR2_DIVR_MASK; 1566 mmio_write_32(rcc_base + pll->pllxcfgr2, value); 1567 } 1568 1569 static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id, 1570 uint32_t *pllcfg, uint32_t fracv) 1571 { 1572 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1573 uintptr_t rcc_base = stm32mp_rcc_base(); 1574 enum stm32mp1_plltype type = pll->plltype; 1575 unsigned long refclk; 1576 uint32_t ifrge = 0; 1577 uint32_t src, value; 1578 1579 src = mmio_read_32(rcc_base + pll->rckxselr) & 1580 RCC_SELR_REFCLK_SRC_MASK; 1581 1582 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1583 (pllcfg[PLLCFG_M] + 1U); 1584 1585 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1586 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1587 return -EINVAL; 1588 } 1589 1590 if ((type == PLL_800) && (refclk >= 8000000U)) { 1591 ifrge = 1U; 1592 } 1593 1594 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1595 RCC_PLLNCFGR1_DIVN_MASK; 1596 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1597 RCC_PLLNCFGR1_DIVM_MASK; 1598 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1599 RCC_PLLNCFGR1_IFRGE_MASK; 1600 mmio_write_32(rcc_base + pll->pllxcfgr1, value); 1601 1602 /* Fractional configuration */ 1603 value = 0; 1604 mmio_write_32(rcc_base + pll->pllxfracr, value); 1605 1606 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1607 mmio_write_32(rcc_base + pll->pllxfracr, value); 1608 1609 value |= RCC_PLLNFRACR_FRACLE; 1610 mmio_write_32(rcc_base + pll->pllxfracr, value); 1611 1612 stm32mp1_pll_config_output(pll_id, pllcfg); 1613 1614 return 0; 1615 } 1616 1617 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg) 1618 { 1619 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1620 uint32_t pllxcsg = 0; 1621 1622 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1623 RCC_PLLNCSGR_MOD_PER_MASK; 1624 1625 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1626 RCC_PLLNCSGR_INC_STEP_MASK; 1627 1628 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1629 RCC_PLLNCSGR_SSCG_MODE_MASK; 1630 1631 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg); 1632 1633 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr, 1634 RCC_PLLNCR_SSCG_CTRL); 1635 } 1636 1637 static int stm32mp1_set_clksrc(unsigned int clksrc) 1638 { 1639 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1640 uint64_t timeout; 1641 1642 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK, 1643 clksrc & RCC_SELR_SRC_MASK); 1644 1645 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1646 while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) { 1647 if (timeout_elapsed(timeout)) { 1648 ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc, 1649 clksrc_address, mmio_read_32(clksrc_address)); 1650 return -ETIMEDOUT; 1651 } 1652 } 1653 1654 return 0; 1655 } 1656 1657 static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address) 1658 { 1659 uint64_t timeout; 1660 1661 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, 1662 clkdiv & RCC_DIVR_DIV_MASK); 1663 1664 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1665 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { 1666 if (timeout_elapsed(timeout)) { 1667 ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n", 1668 clkdiv, address, mmio_read_32(address)); 1669 return -ETIMEDOUT; 1670 } 1671 } 1672 1673 return 0; 1674 } 1675 1676 static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv) 1677 { 1678 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1679 1680 /* 1681 * Binding clksrc : 1682 * bit15-4 offset 1683 * bit3: disable 1684 * bit2-0: MCOSEL[2:0] 1685 */ 1686 if ((clksrc & 0x8U) != 0U) { 1687 mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1688 } else { 1689 mmio_clrsetbits_32(clksrc_address, 1690 RCC_MCOCFG_MCOSRC_MASK, 1691 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1692 mmio_clrsetbits_32(clksrc_address, 1693 RCC_MCOCFG_MCODIV_MASK, 1694 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1695 mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1696 } 1697 } 1698 1699 static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css) 1700 { 1701 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; 1702 1703 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || 1704 (clksrc != (uint32_t)CLK_RTC_DISABLED)) { 1705 mmio_clrsetbits_32(address, 1706 RCC_BDCR_RTCSRC_MASK, 1707 (clksrc & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT); 1708 1709 mmio_setbits_32(address, RCC_BDCR_RTCCKEN); 1710 } 1711 1712 if (lse_css) { 1713 mmio_setbits_32(address, RCC_BDCR_LSECSSON); 1714 } 1715 } 1716 1717 static void stm32mp1_stgen_config(void) 1718 { 1719 uint32_t cntfid0; 1720 unsigned long rate; 1721 unsigned long long counter; 1722 1723 cntfid0 = mmio_read_32(STGEN_BASE + CNTFID_OFF); 1724 rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K)); 1725 1726 if (cntfid0 == rate) { 1727 return; 1728 } 1729 1730 mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1731 counter = (unsigned long long)mmio_read_32(STGEN_BASE + CNTCVL_OFF); 1732 counter |= ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF)) << 32; 1733 counter = (counter * rate / cntfid0); 1734 1735 mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter); 1736 mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32)); 1737 mmio_write_32(STGEN_BASE + CNTFID_OFF, rate); 1738 mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1739 1740 write_cntfrq((u_register_t)rate); 1741 1742 /* Need to update timer with new frequency */ 1743 generic_delay_timer_init(); 1744 } 1745 1746 void stm32mp1_stgen_increment(unsigned long long offset_in_ms) 1747 { 1748 unsigned long long cnt; 1749 1750 cnt = ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF) << 32) | 1751 mmio_read_32(STGEN_BASE + CNTCVL_OFF); 1752 1753 cnt += (offset_in_ms * mmio_read_32(STGEN_BASE + CNTFID_OFF)) / 1000U; 1754 1755 mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1756 mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)cnt); 1757 mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(cnt >> 32)); 1758 mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); 1759 } 1760 1761 static void stm32mp1_pkcs_config(uint32_t pkcs) 1762 { 1763 uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU); 1764 uint32_t value = pkcs & 0xFU; 1765 uint32_t mask = 0xFU; 1766 1767 if ((pkcs & BIT(31)) != 0U) { 1768 mask <<= 4; 1769 value <<= 4; 1770 } 1771 1772 mmio_clrsetbits_32(address, mask, value); 1773 } 1774 1775 int stm32mp1_clk_init(void) 1776 { 1777 uintptr_t rcc_base = stm32mp_rcc_base(); 1778 unsigned int clksrc[CLKSRC_NB]; 1779 unsigned int clkdiv[CLKDIV_NB]; 1780 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1781 int plloff[_PLL_NB]; 1782 int ret, len; 1783 enum stm32mp1_pll_id i; 1784 bool lse_css = false; 1785 bool pll3_preserve = false; 1786 bool pll4_preserve = false; 1787 bool pll4_bootrom = false; 1788 const fdt32_t *pkcs_cell; 1789 void *fdt; 1790 int stgen_p = stm32mp1_clk_get_parent(STGEN_K); 1791 int usbphy_p = stm32mp1_clk_get_parent(USBPHY_K); 1792 1793 if (fdt_get_address(&fdt) == 0) { 1794 return -FDT_ERR_NOTFOUND; 1795 } 1796 1797 /* Check status field to disable security */ 1798 if (!fdt_get_rcc_secure_status()) { 1799 mmio_write_32(rcc_base + RCC_TZCR, 0); 1800 } 1801 1802 ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB, 1803 clksrc); 1804 if (ret < 0) { 1805 return -FDT_ERR_NOTFOUND; 1806 } 1807 1808 ret = fdt_rcc_read_uint32_array("st,clkdiv", (uint32_t)CLKDIV_NB, 1809 clkdiv); 1810 if (ret < 0) { 1811 return -FDT_ERR_NOTFOUND; 1812 } 1813 1814 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1815 char name[12]; 1816 1817 snprintf(name, sizeof(name), "st,pll@%d", i); 1818 plloff[i] = fdt_rcc_subnode_offset(name); 1819 1820 if (!fdt_check_node(plloff[i])) { 1821 continue; 1822 } 1823 1824 ret = fdt_read_uint32_array(fdt, plloff[i], "cfg", 1825 (int)PLLCFG_NB, pllcfg[i]); 1826 if (ret < 0) { 1827 return -FDT_ERR_NOTFOUND; 1828 } 1829 } 1830 1831 stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 1832 stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 1833 1834 /* 1835 * Switch ON oscillator found in device-tree. 1836 * Note: HSI already ON after BootROM stage. 1837 */ 1838 if (stm32mp1_osc[_LSI] != 0U) { 1839 stm32mp1_lsi_set(true); 1840 } 1841 if (stm32mp1_osc[_LSE] != 0U) { 1842 bool bypass, digbyp; 1843 uint32_t lsedrv; 1844 1845 bypass = fdt_osc_read_bool(_LSE, "st,bypass"); 1846 digbyp = fdt_osc_read_bool(_LSE, "st,digbypass"); 1847 lse_css = fdt_osc_read_bool(_LSE, "st,css"); 1848 lsedrv = fdt_osc_read_uint32_default(_LSE, "st,drive", 1849 LSEDRV_MEDIUM_HIGH); 1850 stm32mp1_lse_enable(bypass, digbyp, lsedrv); 1851 } 1852 if (stm32mp1_osc[_HSE] != 0U) { 1853 bool bypass, digbyp, css; 1854 1855 bypass = fdt_osc_read_bool(_HSE, "st,bypass"); 1856 digbyp = fdt_osc_read_bool(_HSE, "st,digbypass"); 1857 css = fdt_osc_read_bool(_HSE, "st,css"); 1858 stm32mp1_hse_enable(bypass, digbyp, css); 1859 } 1860 /* 1861 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 1862 * => switch on CSI even if node is not present in device tree 1863 */ 1864 stm32mp1_csi_set(true); 1865 1866 /* Come back to HSI */ 1867 ret = stm32mp1_set_clksrc(CLK_MPU_HSI); 1868 if (ret != 0) { 1869 return ret; 1870 } 1871 ret = stm32mp1_set_clksrc(CLK_AXI_HSI); 1872 if (ret != 0) { 1873 return ret; 1874 } 1875 ret = stm32mp1_set_clksrc(CLK_MCU_HSI); 1876 if (ret != 0) { 1877 return ret; 1878 } 1879 1880 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) & 1881 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) { 1882 pll3_preserve = stm32mp1_check_pll_conf(_PLL3, 1883 clksrc[CLKSRC_PLL3], 1884 pllcfg[_PLL3], 1885 plloff[_PLL3]); 1886 pll4_preserve = stm32mp1_check_pll_conf(_PLL4, 1887 clksrc[CLKSRC_PLL4], 1888 pllcfg[_PLL4], 1889 plloff[_PLL4]); 1890 } 1891 /* Don't initialize PLL4, when used by BOOTROM */ 1892 if ((stm32mp_get_boot_itf_selected() == 1893 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB) && 1894 ((stgen_p == (int)_PLL4_R) || (usbphy_p == (int)_PLL4_R))) { 1895 pll4_bootrom = true; 1896 pll4_preserve = true; 1897 } 1898 1899 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1900 if (((i == _PLL3) && pll3_preserve) || 1901 ((i == _PLL4) && pll4_preserve)) { 1902 continue; 1903 } 1904 1905 ret = stm32mp1_pll_stop(i); 1906 if (ret != 0) { 1907 return ret; 1908 } 1909 } 1910 1911 /* Configure HSIDIV */ 1912 if (stm32mp1_osc[_HSI] != 0U) { 1913 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]); 1914 if (ret != 0) { 1915 return ret; 1916 } 1917 stm32mp1_stgen_config(); 1918 } 1919 1920 /* Select DIV */ 1921 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 1922 mmio_write_32(rcc_base + RCC_MPCKDIVR, 1923 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK); 1924 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR); 1925 if (ret != 0) { 1926 return ret; 1927 } 1928 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR); 1929 if (ret != 0) { 1930 return ret; 1931 } 1932 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR); 1933 if (ret != 0) { 1934 return ret; 1935 } 1936 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR); 1937 if (ret != 0) { 1938 return ret; 1939 } 1940 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR); 1941 if (ret != 0) { 1942 return ret; 1943 } 1944 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR); 1945 if (ret != 0) { 1946 return ret; 1947 } 1948 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR); 1949 if (ret != 0) { 1950 return ret; 1951 } 1952 1953 /* No ready bit for RTC */ 1954 mmio_write_32(rcc_base + RCC_RTCDIVR, 1955 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK); 1956 1957 /* Configure PLLs source */ 1958 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]); 1959 if (ret != 0) { 1960 return ret; 1961 } 1962 1963 if (!pll3_preserve) { 1964 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]); 1965 if (ret != 0) { 1966 return ret; 1967 } 1968 } 1969 1970 if (!pll4_preserve) { 1971 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]); 1972 if (ret != 0) { 1973 return ret; 1974 } 1975 } 1976 1977 /* Configure and start PLLs */ 1978 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1979 uint32_t fracv; 1980 uint32_t csg[PLLCSG_NB]; 1981 1982 if (((i == _PLL3) && pll3_preserve) || 1983 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) { 1984 continue; 1985 } 1986 1987 if (!fdt_check_node(plloff[i])) { 1988 continue; 1989 } 1990 1991 if ((i == _PLL4) && pll4_bootrom) { 1992 /* Set output divider if not done by the Bootrom */ 1993 stm32mp1_pll_config_output(i, pllcfg[i]); 1994 continue; 1995 } 1996 1997 fracv = fdt_read_uint32_default(fdt, plloff[i], "frac", 0); 1998 1999 ret = stm32mp1_pll_config(i, pllcfg[i], fracv); 2000 if (ret != 0) { 2001 return ret; 2002 } 2003 ret = fdt_read_uint32_array(fdt, plloff[i], "csg", 2004 (uint32_t)PLLCSG_NB, csg); 2005 if (ret == 0) { 2006 stm32mp1_pll_csg(i, csg); 2007 } else if (ret != -FDT_ERR_NOTFOUND) { 2008 return ret; 2009 } 2010 2011 stm32mp1_pll_start(i); 2012 } 2013 /* Wait and start PLLs ouptut when ready */ 2014 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2015 if (!fdt_check_node(plloff[i])) { 2016 continue; 2017 } 2018 2019 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]); 2020 if (ret != 0) { 2021 return ret; 2022 } 2023 } 2024 /* Wait LSE ready before to use it */ 2025 if (stm32mp1_osc[_LSE] != 0U) { 2026 stm32mp1_lse_wait(); 2027 } 2028 2029 /* Configure with expected clock source */ 2030 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]); 2031 if (ret != 0) { 2032 return ret; 2033 } 2034 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]); 2035 if (ret != 0) { 2036 return ret; 2037 } 2038 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]); 2039 if (ret != 0) { 2040 return ret; 2041 } 2042 stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css); 2043 2044 /* Configure PKCK */ 2045 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len); 2046 if (pkcs_cell != NULL) { 2047 bool ckper_disabled = false; 2048 uint32_t j; 2049 uint32_t usbreg_bootrom = 0U; 2050 2051 if (pll4_bootrom) { 2052 usbreg_bootrom = mmio_read_32(rcc_base + RCC_USBCKSELR); 2053 } 2054 2055 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { 2056 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]); 2057 2058 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) { 2059 ckper_disabled = true; 2060 continue; 2061 } 2062 stm32mp1_pkcs_config(pkcs); 2063 } 2064 2065 /* 2066 * CKPER is source for some peripheral clocks 2067 * (FMC-NAND / QPSI-NOR) and switching source is allowed 2068 * only if previous clock is still ON 2069 * => deactivated CKPER only after switching clock 2070 */ 2071 if (ckper_disabled) { 2072 stm32mp1_pkcs_config(CLK_CKPER_DISABLED); 2073 } 2074 2075 if (pll4_bootrom) { 2076 uint32_t usbreg_value, usbreg_mask; 2077 const struct stm32mp1_clk_sel *sel; 2078 2079 sel = clk_sel_ref(_USBPHY_SEL); 2080 usbreg_mask = (uint32_t)sel->msk << sel->src; 2081 sel = clk_sel_ref(_USBO_SEL); 2082 usbreg_mask |= (uint32_t)sel->msk << sel->src; 2083 2084 usbreg_value = mmio_read_32(rcc_base + RCC_USBCKSELR) & 2085 usbreg_mask; 2086 usbreg_bootrom &= usbreg_mask; 2087 if (usbreg_bootrom != usbreg_value) { 2088 VERBOSE("forbidden new USB clk path\n"); 2089 VERBOSE("vs bootrom on USB boot\n"); 2090 return -FDT_ERR_BADVALUE; 2091 } 2092 } 2093 } 2094 2095 /* Switch OFF HSI if not found in device-tree */ 2096 if (stm32mp1_osc[_HSI] == 0U) { 2097 stm32mp1_hsi_set(false); 2098 } 2099 stm32mp1_stgen_config(); 2100 2101 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 2102 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR, 2103 RCC_DDRITFCR_DDRCKMOD_MASK, 2104 RCC_DDRITFCR_DDRCKMOD_SSR << 2105 RCC_DDRITFCR_DDRCKMOD_SHIFT); 2106 2107 return 0; 2108 } 2109 2110 static void stm32mp1_osc_clk_init(const char *name, 2111 enum stm32mp_osc_id index) 2112 { 2113 uint32_t frequency; 2114 2115 if (fdt_osc_read_freq(name, &frequency) == 0) { 2116 stm32mp1_osc[index] = frequency; 2117 } 2118 } 2119 2120 static void stm32mp1_osc_init(void) 2121 { 2122 enum stm32mp_osc_id i; 2123 2124 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { 2125 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i); 2126 } 2127 } 2128 2129 #ifdef STM32MP_SHARED_RESOURCES 2130 /* 2131 * Get the parent ID of the target parent clock, for tagging as secure 2132 * shared clock dependencies. 2133 */ 2134 static int get_parent_id_parent(unsigned int parent_id) 2135 { 2136 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 2137 enum stm32mp1_pll_id pll_id; 2138 uint32_t p_sel; 2139 uintptr_t rcc_base = stm32mp_rcc_base(); 2140 2141 switch (parent_id) { 2142 case _ACLK: 2143 case _PCLK4: 2144 case _PCLK5: 2145 s = _AXIS_SEL; 2146 break; 2147 case _PLL1_P: 2148 case _PLL1_Q: 2149 case _PLL1_R: 2150 pll_id = _PLL1; 2151 break; 2152 case _PLL2_P: 2153 case _PLL2_Q: 2154 case _PLL2_R: 2155 pll_id = _PLL2; 2156 break; 2157 case _PLL3_P: 2158 case _PLL3_Q: 2159 case _PLL3_R: 2160 pll_id = _PLL3; 2161 break; 2162 case _PLL4_P: 2163 case _PLL4_Q: 2164 case _PLL4_R: 2165 pll_id = _PLL4; 2166 break; 2167 case _PCLK1: 2168 case _PCLK2: 2169 case _HCLK2: 2170 case _HCLK6: 2171 case _CK_PER: 2172 case _CK_MPU: 2173 case _CK_MCU: 2174 case _USB_PHY_48: 2175 /* We do not expect to access these */ 2176 panic(); 2177 break; 2178 default: 2179 /* Other parents have no parent */ 2180 return -1; 2181 } 2182 2183 if (s != _UNKNOWN_SEL) { 2184 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s); 2185 2186 p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) & 2187 sel->msk; 2188 2189 if (p_sel < sel->nb_parent) { 2190 return (int)sel->parent[p_sel]; 2191 } 2192 } else { 2193 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 2194 2195 p_sel = mmio_read_32(rcc_base + pll->rckxselr) & 2196 RCC_SELR_REFCLK_SRC_MASK; 2197 2198 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) { 2199 return (int)pll->refclk[p_sel]; 2200 } 2201 } 2202 2203 VERBOSE("No parent selected for %s\n", 2204 stm32mp1_clk_parent_name[parent_id]); 2205 2206 return -1; 2207 } 2208 2209 static void secure_parent_clocks(unsigned long parent_id) 2210 { 2211 int grandparent_id; 2212 2213 switch (parent_id) { 2214 case _PLL3_P: 2215 case _PLL3_Q: 2216 case _PLL3_R: 2217 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2218 break; 2219 2220 /* These clocks are always secure when RCC is secure */ 2221 case _ACLK: 2222 case _HCLK2: 2223 case _HCLK6: 2224 case _PCLK4: 2225 case _PCLK5: 2226 case _PLL1_P: 2227 case _PLL1_Q: 2228 case _PLL1_R: 2229 case _PLL2_P: 2230 case _PLL2_Q: 2231 case _PLL2_R: 2232 case _HSI: 2233 case _HSI_KER: 2234 case _LSI: 2235 case _CSI: 2236 case _CSI_KER: 2237 case _HSE: 2238 case _HSE_KER: 2239 case _HSE_KER_DIV2: 2240 case _HSE_RTC: 2241 case _LSE: 2242 break; 2243 2244 default: 2245 VERBOSE("Cannot secure parent clock %s\n", 2246 stm32mp1_clk_parent_name[parent_id]); 2247 panic(); 2248 } 2249 2250 grandparent_id = get_parent_id_parent(parent_id); 2251 if (grandparent_id >= 0) { 2252 secure_parent_clocks(grandparent_id); 2253 } 2254 } 2255 2256 void stm32mp1_register_clock_parents_secure(unsigned long clock_id) 2257 { 2258 int parent_id; 2259 2260 if (!stm32mp1_rcc_is_secure()) { 2261 return; 2262 } 2263 2264 switch (clock_id) { 2265 case PLL1: 2266 case PLL2: 2267 /* PLL1/PLL2 are always secure: nothing to do */ 2268 break; 2269 case PLL3: 2270 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2271 break; 2272 case PLL4: 2273 ERROR("PLL4 cannot be secured\n"); 2274 panic(); 2275 break; 2276 default: 2277 /* Others are expected gateable clock */ 2278 parent_id = stm32mp1_clk_get_parent(clock_id); 2279 if (parent_id < 0) { 2280 INFO("No parent found for clock %lu\n", clock_id); 2281 } else { 2282 secure_parent_clocks(parent_id); 2283 } 2284 break; 2285 } 2286 } 2287 #endif /* STM32MP_SHARED_RESOURCES */ 2288 2289 static void sync_earlyboot_clocks_state(void) 2290 { 2291 unsigned int idx; 2292 const unsigned long secure_enable[] = { 2293 AXIDCG, 2294 BSEC, 2295 DDRC1, DDRC1LP, 2296 DDRC2, DDRC2LP, 2297 DDRCAPB, DDRPHYCAPB, DDRPHYCAPBLP, 2298 DDRPHYC, DDRPHYCLP, 2299 RTCAPB, 2300 TZC1, TZC2, 2301 TZPC, 2302 STGEN_K, 2303 }; 2304 2305 for (idx = 0U; idx < ARRAY_SIZE(secure_enable); idx++) { 2306 stm32mp_clk_enable(secure_enable[idx]); 2307 } 2308 } 2309 2310 static const struct clk_ops stm32mp_clk_ops = { 2311 .enable = stm32mp_clk_enable, 2312 .disable = stm32mp_clk_disable, 2313 .is_enabled = stm32mp_clk_is_enabled, 2314 .get_rate = stm32mp_clk_get_rate, 2315 .get_parent = stm32mp1_clk_get_parent, 2316 }; 2317 2318 int stm32mp1_clk_probe(void) 2319 { 2320 stm32mp1_osc_init(); 2321 2322 sync_earlyboot_clocks_state(); 2323 2324 clk_register(&stm32mp_clk_ops); 2325 2326 return 0; 2327 } 2328