1# 2# Copyright (c) 2021, MediaTek Inc. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7MTK_PLAT := plat/mediatek 8MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} 9 10PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ 11 -I${MTK_PLAT}/common/drivers/timer/ \ 12 -I${MTK_PLAT_SOC}/drivers/emi_mpu/ \ 13 -I${MTK_PLAT_SOC}/include/ 14 15include drivers/arm/gic/v3/gicv3.mk 16include lib/xlat_tables_v2/xlat_tables.mk 17 18PLAT_BL_COMMON_SOURCES := ${GICV3_SOURCES} \ 19 ${XLAT_TABLES_LIB_SRCS} \ 20 plat/common/aarch64/crash_console_helpers.S \ 21 plat/common/plat_psci_common.c 22 23 24BL31_SOURCES += common/desc_image_load.c \ 25 drivers/delay_timer/delay_timer.c \ 26 drivers/delay_timer/generic_delay_timer.c \ 27 drivers/ti/uart/aarch64/16550_console.S \ 28 lib/bl_aux_params/bl_aux_params.c \ 29 lib/cpus/aarch64/cortex_a55.S \ 30 lib/cpus/aarch64/cortex_a76.S \ 31 plat/common/plat_gicv3.c \ 32 ${MTK_PLAT}/common/mtk_plat_common.c \ 33 ${MTK_PLAT}/common/params_setup.c \ 34 ${MTK_PLAT}/common/drivers/timer/mt_timer.c \ 35 ${MTK_PLAT_SOC}/aarch64/platform_common.c \ 36 ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ 37 ${MTK_PLAT_SOC}/bl31_plat_setup.c \ 38 ${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \ 39 ${MTK_PLAT_SOC}/plat_pm.c \ 40 ${MTK_PLAT_SOC}/plat_topology.c 41 42# Configs for A76 and A55 43HW_ASSISTED_COHERENCY := 1 44USE_COHERENT_MEM := 0 45CTX_INCLUDE_AARCH32_REGS := 0 46ERRATA_A55_1530923 := 1 47ERRATA_A55_1221012 := 1 48 49# indicate the reset vector address can be programmed 50PROGRAMMABLE_RESET_ADDRESS := 1 51 52COLD_BOOT_SINGLE_CPU := 1 53 54MACH_MT8186 := 1 55$(eval $(call add_define,MACH_MT8186)) 56 57include lib/coreboot/coreboot.mk 58