1 /* 2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #define PLAT_PRIMARY_CPU 0x0 11 12 #define MT_GIC_BASE (0x0C000000) 13 #define MCUCFG_BASE (0x0C530000) 14 #define IO_PHYS (0x10000000) 15 16 /* Aggregate of all devices for MMU mapping */ 17 #define MTK_DEV_RNG0_BASE IO_PHYS 18 #define MTK_DEV_RNG0_SIZE 0x10000000 19 #define MTK_DEV_RNG2_BASE MT_GIC_BASE 20 #define MTK_DEV_RNG2_SIZE 0x600000 21 22 /******************************************************************************* 23 * GPIO related constants 24 ******************************************************************************/ 25 #define GPIO_BASE (IO_PHYS + 0x00005000) 26 #define IOCFG_LT_BASE (IO_PHYS + 0x00002000) 27 #define IOCFG_LM_BASE (IO_PHYS + 0x00002200) 28 #define IOCFG_LB_BASE (IO_PHYS + 0x00002400) 29 #define IOCFG_BL_BASE (IO_PHYS + 0x00002600) 30 #define IOCFG_RB_BASE (IO_PHYS + 0x00002A00) 31 #define IOCFG_RT_BASE (IO_PHYS + 0x00002C00) 32 33 /******************************************************************************* 34 * UART related constants 35 ******************************************************************************/ 36 #define UART0_BASE (IO_PHYS + 0x01002000) 37 38 #define UART_BAUDRATE 115200 39 40 /******************************************************************************* 41 * PWRAP related constants 42 ******************************************************************************/ 43 #define PMIC_WRAP_BASE (IO_PHYS + 0x0000D000) 44 45 /******************************************************************************* 46 * EMI MPU related constants 47 ******************************************************************************/ 48 #define EMI_MPU_BASE (IO_PHYS + 0x0021B000) 49 50 /******************************************************************************* 51 * GIC-600 & interrupt handling related constants 52 ******************************************************************************/ 53 /* Base MTK_platform compatible GIC memory map */ 54 #define BASE_GICD_BASE MT_GIC_BASE 55 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 56 57 #define SYS_CIRQ_BASE (IO_PHYS + 0x204000) 58 #define CIRQ_REG_NUM 11 59 #define CIRQ_IRQ_NUM 326 60 #define CIRQ_SPI_START 64 61 #define MD_WDT_IRQ_BIT_ID 107 62 /******************************************************************************* 63 * System counter frequency related constants 64 ******************************************************************************/ 65 #define SYS_COUNTER_FREQ_IN_TICKS 13000000 66 #define SYS_COUNTER_FREQ_IN_MHZ 13 67 68 /******************************************************************************* 69 * Platform binary types for linking 70 ******************************************************************************/ 71 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 72 #define PLATFORM_LINKER_ARCH aarch64 73 74 /******************************************************************************* 75 * Generic platform constants 76 ******************************************************************************/ 77 #define PLATFORM_STACK_SIZE 0x800 78 79 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 80 81 #define PLAT_MAX_PWR_LVL U(3) 82 #define PLAT_MAX_RET_STATE U(1) 83 #define PLAT_MAX_OFF_STATE U(9) 84 85 #define PLATFORM_SYSTEM_COUNT U(1) 86 #define PLATFORM_MCUSYS_COUNT U(1) 87 #define PLATFORM_CLUSTER_COUNT U(1) 88 #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 89 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 90 91 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 92 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 93 94 #define SOC_CHIP_ID U(0x8186) 95 96 /******************************************************************************* 97 * Platform memory map related constants 98 ******************************************************************************/ 99 #define TZRAM_BASE 0x54600000 100 #define TZRAM_SIZE 0x00030000 101 102 /******************************************************************************* 103 * BL31 specific defines. 104 ******************************************************************************/ 105 /* 106 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 107 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 108 * little space for growth. 109 */ 110 #define BL31_BASE (TZRAM_BASE + 0x1000) 111 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 112 113 /******************************************************************************* 114 * Platform specific page table and MMU setup constants 115 ******************************************************************************/ 116 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 117 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 118 #define MAX_XLAT_TABLES 16 119 #define MAX_MMAP_REGIONS 16 120 121 /******************************************************************************* 122 * Declarations and constants to access the mailboxes safely. Each mailbox is 123 * aligned on the biggest cache line size in the platform. This is known only 124 * to the platform as it might have a combination of integrated and external 125 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 126 * line at any cache level. They could belong to different cpus/clusters & 127 * get written while being protected by different locks causing corruption of 128 * a valid mailbox address. 129 ******************************************************************************/ 130 #define CACHE_WRITEBACK_SHIFT 6 131 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 132 #endif /* PLATFORM_DEF_H */ 133