Merge changes from topic "xlnx_zynqmp_misra_fix1" into integration

* changes:
fix(zynqmp): resolve the misra 8.6 warnings
fix(zynqmp): resolve the misra 4.6 warnings

Merge "feat(stm32mp1): save boot auth status and partition info" into integration

Merge changes from topic "HEAD" into integration

* changes:
feat(synquacer): add FWU Multi Bank Update support
feat(synquacer): add TBBR support
feat(synquacer): add BL2 support
refactor(syn

Merge changes from topic "HEAD" into integration

* changes:
feat(synquacer): add FWU Multi Bank Update support
feat(synquacer): add TBBR support
feat(synquacer): add BL2 support
refactor(synquacer): move common source files

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feat(synquacer): add FWU Multi Bank Update support

Add FWU Multi Bank Update support. This reads the platform metadata
and update the FIP base address so that BL2 can load correct BL3X
based on the

feat(synquacer): add FWU Multi Bank Update support

Add FWU Multi Bank Update support. This reads the platform metadata
and update the FIP base address so that BL2 can load correct BL3X
based on the boot index.

Cc: Sumit Garg <sumit.garg@linaro.org>
Cc: Masahisa Kojima <masahisa.kojima@linaro.org>
Cc: Manish V Badarkhe <manish.badarkhe@arm.com>
Cc: Leonardo Sandoval <leonardo.sandoval@linaro.org>
Change-Id: I5d96972bc4b3b9a12a8157117e53a05da5ce89f6
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>

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feat(synquacer): add TBBR support

enable Trusted-Boot for Synquacer platform.

Cc: Sumit Garg <sumit.garg@linaro.org>
Cc: Masahisa Kojima <masahisa.kojima@linaro.org>
Cc: Manish V Badarkhe <manish.b

feat(synquacer): add TBBR support

enable Trusted-Boot for Synquacer platform.

Cc: Sumit Garg <sumit.garg@linaro.org>
Cc: Masahisa Kojima <masahisa.kojima@linaro.org>
Cc: Manish V Badarkhe <manish.badarkhe@arm.com>
Cc: Leonardo Sandoval <leonardo.sandoval@linaro.org>
Change-Id: I2608b4d573d95d55da1fc5544333e0dbf3f763f2
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>

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feat(synquacer): add BL2 support

Add BL2 support by default. Move the legacy mode behind the
RESET_TO_BL31 define.

Cc: Sumit Garg <sumit.garg@linaro.org>
Cc: Masahisa Kojima <masahisa.kojima@linaro

feat(synquacer): add BL2 support

Add BL2 support by default. Move the legacy mode behind the
RESET_TO_BL31 define.

Cc: Sumit Garg <sumit.garg@linaro.org>
Cc: Masahisa Kojima <masahisa.kojima@linaro.org>
Cc: Manish V Badarkhe <manish.badarkhe@arm.com>
Cc: Leonardo Sandoval <leonardo.sandoval@linaro.org>
Change-Id: Ic490745a7e8f6114172733428ebd6bd6adfcc1ec
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>

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refactor(synquacer): move common source files

Prepare for introduction of BL2 support by moving
reusable files from BL31_SOURCES into PLAT_BL_COMMON_SOURCES

Cc: Sumit Garg <sumit.garg@linaro.org>
C

refactor(synquacer): move common source files

Prepare for introduction of BL2 support by moving
reusable files from BL31_SOURCES into PLAT_BL_COMMON_SOURCES

Cc: Sumit Garg <sumit.garg@linaro.org>
Cc: Masahisa Kojima <masahisa.kojima@linaro.org>
Cc: Manish V Badarkhe <manish.badarkhe@arm.com>
Cc: Leonardo Sandoval <leonardo.sandoval@linaro.org>
Change-Id: I21137cdd40d027cfa77f1dec3598ee85d4873581
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>

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Merge changes from topic "st_optee_paged" into integration

* changes:
feat(stm32mp1): optionally use paged OP-TEE
feat(optee): check paged_image_info

feat(stm32mp1): save boot auth status and partition info

Introduce a functionality for saving/restoring boot auth status
and partition used for booting (FSBL partition on which the boot
was successf

feat(stm32mp1): save boot auth status and partition info

Introduce a functionality for saving/restoring boot auth status
and partition used for booting (FSBL partition on which the boot
was successful).

Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Change-Id: I4d7f153b70dfc49dad8c1c3fa71111a350caf1ee

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Merge changes from topic "mb_hash" into integration

* changes:
refactor(imx): update config of mbedtls support
refactor(qemu): update configuring mbedtls support
refactor(measured-boot): mb al

Merge changes from topic "mb_hash" into integration

* changes:
refactor(imx): update config of mbedtls support
refactor(qemu): update configuring mbedtls support
refactor(measured-boot): mb algorithm selection

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feat(imx8m): keep pu domains in default state during boot stage

No need to keep all PU domains on as the full power domain driver
support has been added.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>

feat(imx8m): keep pu domains in default state during boot stage

No need to keep all PU domains on as the full power domain driver
support has been added.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Iec22dcabbbfe3f38b915104a437d396d7b1bb2d8

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feat(imx8m): add the PU power domain support on imx8mm/mn

Add the PU power domain support for imx8mm/mn.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ib88b4b5db956fdf2c77d2f2f3723d61a7060

feat(imx8m): add the PU power domain support on imx8mm/mn

Add the PU power domain support for imx8mm/mn.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ib88b4b5db956fdf2c77d2f2f3723d61a7060409d

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feat(imx8m): add the anamix pll override setting

Add PLL power down override & bypass support when
system enter DSM mode.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I50cd6b82151961ab849

feat(imx8m): add the anamix pll override setting

Add PLL power down override & bypass support when
system enter DSM mode.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I50cd6b82151961ab849f58714a8c307d3f7f4166

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feat(imx8m): add the ddr frequency change support for imx8m family

Add the DDR frequency change support.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: If1167785796b8678c351569b83d2922c66f6

feat(imx8m): add the ddr frequency change support for imx8m family

Add the DDR frequency change support.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: If1167785796b8678c351569b83d2922c66f6e530

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feat(imx8mn): enable dram retention suuport on imx8mn

Enable dram retention support on i.MX8MN.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I9b3a08efbbd154b2fc7e41bedb36a4d4e3784448

feat(imx8mm): enable dram retention suuport on imx8mm

Enable dram retention support on i.MX8MM.

Change-Id: I76ada615d386602e551d572ff4e60ee19bb8e418
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

feat(imx8m): add dram retention flow for imx8m family

Add the dram retention flow for i.MX8M SoC family.

Change-Id: Ifb8ba5b2f6f002133cf47c07fef73df29c51c890
Signed-off-by: Jacky Bai <ping.bai@nxp.

feat(imx8m): add dram retention flow for imx8m family

Add the dram retention flow for i.MX8M SoC family.

Change-Id: Ifb8ba5b2f6f002133cf47c07fef73df29c51c890
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

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Merge "fix(zynqmp): move bl31 with DEBUG=1 back to OCM" into integration

Merge changes from topic "xlnx_versal_misra_fix" into integration

* changes:
fix(versal): resolve misra 15.6 warnings
fix(zynqmp): resolve misra 8.13 warnings
fix(versal): resolve misra 8.13 w

Merge changes from topic "xlnx_versal_misra_fix" into integration

* changes:
fix(versal): resolve misra 15.6 warnings
fix(zynqmp): resolve misra 8.13 warnings
fix(versal): resolve misra 8.13 warnings
fix(versal): resolve the misra 4.6 warnings

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Merge changes from topic "lw/cca_cot" into integration

* changes:
feat(arm): retrieve the right ROTPK for cca
feat(arm): add support for cca CoT
feat(arm): provide some swd rotpk files
build

Merge changes from topic "lw/cca_cot" into integration

* changes:
feat(arm): retrieve the right ROTPK for cca
feat(arm): add support for cca CoT
feat(arm): provide some swd rotpk files
build(tbbr): drive cert_create changes for cca CoT
refactor(arm): add cca CoT certificates to fconf
feat(fiptool): add cca, core_swd, plat cert in FIP
feat(cert_create): define the cca chain of trust
feat(cca): introduce new "cca" chain of trust
build(changelog): add new scope for CCA
refactor(fvp): increase bl2 size when bl31 in DRAM

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feat(stm32mp1): optionally use paged OP-TEE

STM32MP13 can encrypt the DDR. OP-TEE is then fully in DDR, and there
is no need for paged image on STM32MP13. The management of the paged
OP-TEE is made

feat(stm32mp1): optionally use paged OP-TEE

STM32MP13 can encrypt the DDR. OP-TEE is then fully in DDR, and there
is no need for paged image on STM32MP13. The management of the paged
OP-TEE is made conditional, and will be kept only for STM32MP15.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I85ac7aaf6a172c4ee529736113ed40fe66835fd7

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feat(plat/arm/sgi): increase memory reserved for bl31 image

Increase the size of bl31 image by 52K to accomodate increased size of
xlat table.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>

feat(plat/arm/sgi): increase memory reserved for bl31 image

Increase the size of bl31 image by 52K to accomodate increased size of
xlat table.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: Ic3a8d8be1104adf48d22aa829e2197f710b6b666

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feat(plat/arm/sgi): read isolated cpu mpid list from sds

Add support to read the list of isolated CPUs from SDS and publish this
list via the non-trusted firmware configuration file for the next sta

feat(plat/arm/sgi): read isolated cpu mpid list from sds

Add support to read the list of isolated CPUs from SDS and publish this
list via the non-trusted firmware configuration file for the next stages
of boot software to use.

Isolated CPUs are those that are not to be used on the platform for
various reasons. The isolated CPU list is an array of MPID values of the
CPUs that have to be isolated.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I4313cf025f4c9e9feffebca2d35b259f5bafce69

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feat(board/rdn2): add a new 'isolated-cpu-list' property

Add a new property named 'isolated-cpu-list' to list the CPUs that are
to be isolated and not used by the platform. The data represented by
t

feat(board/rdn2): add a new 'isolated-cpu-list' property

Add a new property named 'isolated-cpu-list' to list the CPUs that are
to be isolated and not used by the platform. The data represented by
this property is formatted as below.

strutct isolated_cpu_mpid_list {
uint64_t count;
uint64_t mpid_list[MAX Number of PE];
}

Also, the property is pre-initialized to 0 to reserve space for the
property in the dtb. The data for this property is read from SDS and
updated during boot. The number of entries in this list is equal to the
maximum number of PEs present on the platform.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I4119f899a273ccbf8259e0d711d3a25501c7ec64

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Merge changes from topic "uart_segregation_v2" into integration

* changes:
feat(sgi): add page table translation entry for secure uart
feat(sgi): route TF-A logs via secure uart
feat(sgi): dev

Merge changes from topic "uart_segregation_v2" into integration

* changes:
feat(sgi): add page table translation entry for secure uart
feat(sgi): route TF-A logs via secure uart
feat(sgi): deviate from arm css common uart related definitions

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