1 /* 2 * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <plat/common/common_def.h> 12 13 /* CPU topology */ 14 #define PLAT_MAX_CORES_PER_CLUSTER U(2) 15 #define PLAT_CLUSTER_COUNT U(12) 16 #define PLATFORM_CORE_COUNT (PLAT_CLUSTER_COUNT * \ 17 PLAT_MAX_CORES_PER_CLUSTER) 18 19 /* Macros to read the SQ power domain state */ 20 #define SQ_PWR_LVL0 MPIDR_AFFLVL0 21 #define SQ_PWR_LVL1 MPIDR_AFFLVL1 22 #define SQ_PWR_LVL2 MPIDR_AFFLVL2 23 24 #define SQ_CORE_PWR_STATE(state) (state)->pwr_domain_state[SQ_PWR_LVL0] 25 #define SQ_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[SQ_PWR_LVL1] 26 #define SQ_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > SQ_PWR_LVL1) ?\ 27 (state)->pwr_domain_state[SQ_PWR_LVL2] : 0) 28 29 #define PLAT_MAX_PWR_LVL U(1) 30 #define PLAT_MAX_RET_STATE U(1) 31 #define PLAT_MAX_OFF_STATE U(2) 32 33 #define SQ_LOCAL_STATE_RUN 0 34 #define SQ_LOCAL_STATE_RET 1 35 #define SQ_LOCAL_STATE_OFF 2 36 37 #define CACHE_WRITEBACK_SHIFT 6 38 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 39 40 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 41 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 42 #define MAX_XLAT_TABLES 8 43 #define MAX_MMAP_REGIONS 8 44 45 #define PLATFORM_STACK_SIZE 0x400 46 47 #if !RESET_TO_BL31 48 49 /* A mailbox page will be mapped from BL2 and BL31 */ 50 #define BL2_MAILBOX_BASE 0x0403f000 51 #define BL2_MAILBOX_SIZE 0x1000 52 53 #define MAX_IO_HANDLES 2 54 #define MAX_IO_DEVICES 2 55 #define MAX_IO_BLOCK_DEVICES U(1) 56 57 #define BL2_BASE 0x04000000 58 #define BL2_SIZE (256 * 1024) 59 #define BL2_LIMIT (BL2_BASE + BL2_SIZE) 60 61 /* If BL2 is enabled, the BL31 is loaded on secure DRAM */ 62 #define BL31_BASE 0xfbe00000 63 #define BL31_SIZE 0x00100000 64 #else 65 66 #define BL31_BASE 0x04000000 67 #define BL31_SIZE 0x00080000 68 #endif 69 70 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 71 72 #define BL32_BASE 0xfc000000 73 #define BL32_SIZE 0x03c00000 74 #define BL32_LIMIT (BL32_BASE + BL32_SIZE) 75 76 /* Alternative BL33 */ 77 #define PLAT_SQ_BL33_BASE 0xe0000000 78 #define PLAT_SQ_BL33_SIZE 0x00100000 79 80 /* FIP IO base */ 81 #define PLAT_SQ_FIP_IOBASE 0x08600000 82 #define PLAT_SQ_FIP_MAXSIZE 0x00400000 83 84 #define PLAT_SQ_CCN_BASE 0x32000000 85 #define PLAT_SQ_CLUSTER_TO_CCN_ID_MAP \ 86 0, /* Cluster 0 */ \ 87 18, /* Cluster 1 */ \ 88 11, /* Cluster 2 */ \ 89 29, /* Cluster 3 */ \ 90 35, /* Cluster 4 */ \ 91 17, /* Cluster 5 */ \ 92 12, /* Cluster 6 */ \ 93 30, /* Cluster 7 */ \ 94 14, /* Cluster 8 */ \ 95 32, /* Cluster 9 */ \ 96 15, /* Cluster 10 */ \ 97 33 /* Cluster 11 */ 98 99 /* UART related constants */ 100 #define PLAT_SQ_BOOT_UART_BASE 0x2A400000 101 #define PLAT_SQ_BOOT_UART_CLK_IN_HZ 62500000 102 #define SQ_CONSOLE_BAUDRATE 115200 103 104 #define SQ_SYS_CNTCTL_BASE 0x2a430000 105 106 #define SQ_SYS_TIMCTL_BASE 0x2a810000 107 #define PLAT_SQ_NSTIMER_FRAME_ID 0 108 #define SQ_SYS_CNT_BASE_NS 0x2a830000 109 110 #define DRAMINFO_BASE 0x2E00FFC0 111 112 #define PLAT_SQ_MHU_BASE 0x45000000 113 114 #define PLAT_SQ_SCP_COM_SHARED_MEM_BASE 0x45400000 115 #define SCPI_CMD_GET_DRAMINFO 0x1 116 117 #define SQ_BOOT_CFG_ADDR 0x45410000 118 #define PLAT_SQ_PRIMARY_CPU_SHIFT 8 119 #define PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 6 120 121 #define PLAT_SQ_GICD_BASE 0x30000000 122 #define PLAT_SQ_GICR_BASE 0x30400000 123 124 #define PLAT_SQ_GPIO_BASE 0x51000000 125 126 #define PLAT_SPM_BUF_BASE (BL32_LIMIT - 32 * PLAT_SPM_BUF_SIZE) 127 #define PLAT_SPM_BUF_SIZE ULL(0x10000) 128 #define PLAT_SPM_SPM_BUF_EL0_MMAP MAP_REGION2(PLAT_SPM_BUF_BASE, \ 129 PLAT_SPM_BUF_BASE, \ 130 PLAT_SPM_BUF_SIZE, \ 131 MT_RO_DATA | MT_SECURE | \ 132 MT_USER, PAGE_SIZE) 133 134 #define PLAT_SP_IMAGE_NS_BUF_BASE BL32_LIMIT 135 #define PLAT_SP_IMAGE_NS_BUF_SIZE ULL(0x200000) 136 #define PLAT_SP_IMAGE_NS_BUF_MMAP MAP_REGION2(PLAT_SP_IMAGE_NS_BUF_BASE, \ 137 PLAT_SP_IMAGE_NS_BUF_BASE, \ 138 PLAT_SP_IMAGE_NS_BUF_SIZE, \ 139 MT_RW_DATA | MT_NS | \ 140 MT_USER, PAGE_SIZE) 141 142 #define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x10000) 143 #define PLAT_SP_IMAGE_STACK_SIZE (32 * PLAT_SP_IMAGE_STACK_PCPU_SIZE) 144 #define PLAT_SP_IMAGE_STACK_BASE (PLAT_SQ_SP_HEAP_BASE + PLAT_SQ_SP_HEAP_SIZE) 145 146 #define PLAT_SQ_SP_IMAGE_SIZE ULL(0x200000) 147 #define PLAT_SQ_SP_IMAGE_MMAP MAP_REGION2(BL32_BASE, BL32_BASE, \ 148 PLAT_SQ_SP_IMAGE_SIZE, \ 149 MT_CODE | MT_SECURE | \ 150 MT_USER, PAGE_SIZE) 151 152 #define PLAT_SQ_SP_HEAP_BASE (BL32_BASE + PLAT_SQ_SP_IMAGE_SIZE) 153 #define PLAT_SQ_SP_HEAP_SIZE ULL(0x800000) 154 155 #define PLAT_SQ_SP_IMAGE_RW_MMAP MAP_REGION2(PLAT_SQ_SP_HEAP_BASE, \ 156 PLAT_SQ_SP_HEAP_BASE, \ 157 (PLAT_SQ_SP_HEAP_SIZE + \ 158 PLAT_SP_IMAGE_STACK_SIZE), \ 159 MT_RW_DATA | MT_SECURE | \ 160 MT_USER, PAGE_SIZE) 161 162 #define PLAT_SQ_SP_PRIV_BASE (PLAT_SP_IMAGE_STACK_BASE + \ 163 PLAT_SP_IMAGE_STACK_SIZE) 164 #define PLAT_SQ_SP_PRIV_SIZE ULL(0x40000) 165 166 #define PLAT_SP_PRI 0x20 167 #define PLAT_PRI_BITS 2 168 #define PLAT_SPM_COOKIE_0 ULL(0) 169 #define PLAT_SPM_COOKIE_1 ULL(0) 170 171 /* Total number of memory regions with distinct properties */ 172 #define PLAT_SP_IMAGE_NUM_MEM_REGIONS 6 173 174 #define PLAT_SP_IMAGE_MMAP_REGIONS 30 175 #define PLAT_SP_IMAGE_MAX_XLAT_TABLES 20 176 #define PLAT_SP_IMAGE_XLAT_SECTION_NAME "sp_xlat_table" 177 #define PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME "sp_xlat_table" 178 179 #define PLAT_SQ_UART1_BASE PLAT_SQ_BOOT_UART_BASE 180 #define PLAT_SQ_UART1_SIZE ULL(0x1000) 181 #define PLAT_SQ_UART1_MMAP MAP_REGION_FLAT(PLAT_SQ_UART1_BASE, \ 182 PLAT_SQ_UART1_SIZE, \ 183 MT_DEVICE | MT_RW | \ 184 MT_NS | MT_PRIVILEGED) 185 186 #define PLAT_SQ_PERIPH_BASE 0x50000000 187 #define PLAT_SQ_PERIPH_SIZE ULL(0x8000000) 188 #define PLAT_SQ_PERIPH_MMAP MAP_REGION_FLAT(PLAT_SQ_PERIPH_BASE, \ 189 PLAT_SQ_PERIPH_SIZE, \ 190 MT_DEVICE | MT_RW | \ 191 MT_NS | MT_USER) 192 193 #define PLAT_SQ_FLASH_BASE 0x08000000 194 #define PLAT_SQ_FLASH_SIZE ULL(0x8000000) 195 #define PLAT_SQ_FLASH_MMAP MAP_REGION_FLAT(PLAT_SQ_FLASH_BASE, \ 196 PLAT_SQ_FLASH_SIZE, \ 197 MT_DEVICE | MT_RW | \ 198 MT_NS | MT_USER) 199 200 #endif /* PLATFORM_DEF_H */ 201