1 /* 2 * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <lib/mmio.h> 13 #include <lib/psci/psci.h> 14 15 #include <gpc.h> 16 #include <imx8m_psci.h> 17 #include <plat_imx8.h> 18 19 #define MAX_PLL_NUM U(10) 20 21 static uint32_t gpc_imr_offset[] = { IMR1_CORE0_A53, IMR1_CORE1_A53, IMR1_CORE2_A53, IMR1_CORE3_A53, }; 22 23 DEFINE_BAKERY_LOCK(gpc_lock); 24 25 #pragma weak imx_set_cpu_pwr_off 26 #pragma weak imx_set_cpu_pwr_on 27 #pragma weak imx_set_cpu_lpm 28 #pragma weak imx_set_cluster_powerdown 29 30 void imx_set_cpu_secure_entry(unsigned int core_id, uintptr_t sec_entrypoint) 31 { 32 uint64_t temp_base; 33 34 temp_base = (uint64_t) sec_entrypoint; 35 temp_base >>= 2; 36 37 mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3), 38 ((uint32_t)(temp_base >> 22) & 0xffff)); 39 mmio_write_32(IMX_SRC_BASE + SRC_GPR1_OFFSET + (core_id << 3) + 4, 40 ((uint32_t)temp_base & 0x003fffff)); 41 } 42 43 void imx_set_cpu_pwr_off(unsigned int core_id) 44 { 45 46 bakery_lock_get(&gpc_lock); 47 48 /* enable the wfi power down of the core */ 49 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); 50 51 bakery_lock_release(&gpc_lock); 52 53 /* assert the pcg pcr bit of the core */ 54 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 55 } 56 57 void imx_set_cpu_pwr_on(unsigned int core_id) 58 { 59 bakery_lock_get(&gpc_lock); 60 61 /* clear the wfi power down bit of the core */ 62 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); 63 64 bakery_lock_release(&gpc_lock); 65 66 /* assert the ncpuporeset */ 67 mmio_clrbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); 68 /* assert the pcg pcr bit of the core */ 69 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 70 /* sw power up the core */ 71 mmio_setbits_32(IMX_GPC_BASE + CPU_PGC_UP_TRG, (1 << core_id)); 72 73 /* wait for the power up finished */ 74 while ((mmio_read_32(IMX_GPC_BASE + CPU_PGC_UP_TRG) & (1 << core_id)) != 0) 75 ; 76 77 /* deassert the pcg pcr bit of the core */ 78 mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 79 /* deassert the ncpuporeset */ 80 mmio_setbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); 81 } 82 83 void imx_set_cpu_lpm(unsigned int core_id, bool pdn) 84 { 85 bakery_lock_get(&gpc_lock); 86 87 if (pdn) { 88 /* enable the core WFI PDN & IRQ PUP */ 89 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | 90 COREx_IRQ_WUP(core_id)); 91 /* assert the pcg pcr bit of the core */ 92 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 93 } else { 94 /* disbale CORE WFI PDN & IRQ PUP */ 95 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | 96 COREx_IRQ_WUP(core_id)); 97 /* deassert the pcg pcr bit of the core */ 98 mmio_clrbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); 99 } 100 101 bakery_lock_release(&gpc_lock); 102 } 103 104 /* 105 * the plat and noc can only be power up & down by slot method, 106 * slot0: plat power down; slot1: noc power down; slot2: noc power up; 107 * slot3: plat power up. plat's pup&pdn ack is used by default. if 108 * noc is config to power down, then noc's pdn ack should be used. 109 */ 110 static void imx_a53_plat_slot_config(bool pdn) 111 { 112 if (pdn) { 113 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL); 114 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL); 115 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_PLAT_PDN_ACK | 116 A53_PLAT_PUP_ACK); 117 mmio_setbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); 118 } else { 119 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL); 120 mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL); 121 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_DUMMY_PUP_ACK | 122 A53_DUMMY_PDN_ACK); 123 mmio_clrbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); 124 } 125 } 126 127 void imx_set_cluster_standby(bool enter) 128 { 129 /* 130 * Enable BIT 6 of A53 AD register to make sure system 131 * don't enter LPM mode. 132 */ 133 if (enter) 134 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6)); 135 else 136 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, (1 << 6)); 137 } 138 139 /* i.mx8mq need to override it */ 140 void imx_set_cluster_powerdown(unsigned int last_core, uint8_t power_state) 141 { 142 uint32_t val; 143 144 if (!is_local_state_run(power_state)) { 145 /* config C0~1's LPM, enable a53 clock off in LPM */ 146 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CLK_ON_LPM, 147 LPM_MODE(power_state)); 148 /* config C2-3's LPM */ 149 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, LPM_MODE(power_state)); 150 151 /* enable PLAT/SCU power down */ 152 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD); 153 val &= ~EN_L2_WFI_PDN; 154 /* L2 cache memory is on in WAIT mode */ 155 if (is_local_state_off(power_state)) { 156 val |= (L2PGE | EN_PLAT_PDN); 157 imx_a53_plat_slot_config(true); 158 } 159 160 mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val); 161 } else { 162 /* clear the slot and ack for cluster power down */ 163 imx_a53_plat_slot_config(false); 164 /* reverse the cluster level setting */ 165 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, 0xf, A53_CLK_ON_LPM); 166 mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, 0xf); 167 168 /* clear PLAT/SCU power down */ 169 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_AD, (L2PGE | EN_PLAT_PDN), 170 EN_L2_WFI_PDN); 171 } 172 } 173 174 static unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id) 175 { 176 unsigned int n = id >> ISENABLER_SHIFT; 177 178 return mmio_read_32(base + GICD_ISENABLER + (n << 2)); 179 } 180 181 /* 182 * gic's clock will be gated in system suspend, so gic has no ability to 183 * to wakeup the system, we need to config the imr based on the irq 184 * enable status in gic, then gpc will monitor the wakeup irq 185 */ 186 void imx_set_sys_wakeup(unsigned int last_core, bool pdn) 187 { 188 uint32_t irq_mask; 189 uintptr_t gicd_base = PLAT_GICD_BASE; 190 191 if (pdn) 192 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CORE_WUP_SRC(last_core), 193 IRQ_SRC_A53_WUP); 194 else 195 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, IRQ_SRC_A53_WUP, 196 A53_CORE_WUP_SRC(last_core)); 197 198 /* clear last core's IMR based on GIC's mask setting */ 199 for (int i = 0; i < IRQ_IMR_NUM; i++) { 200 if (pdn) 201 /* set the wakeup irq base GIC */ 202 irq_mask = ~gicd_read_isenabler(gicd_base, 32 * (i + 1)); 203 else 204 irq_mask = IMR_MASK_ALL; 205 206 mmio_write_32(IMX_GPC_BASE + gpc_imr_offset[last_core] + i * 4, 207 irq_mask); 208 } 209 } 210 211 #pragma weak imx_noc_slot_config 212 /* 213 * this function only need to be override by platform 214 * that support noc power down, for example: imx8mm. 215 * otherwize, keep it empty. 216 */ 217 void imx_noc_slot_config(bool pdn) 218 { 219 220 } 221 222 /* this is common for all imx8m soc */ 223 void imx_set_sys_lpm(unsigned int last_core, bool retention) 224 { 225 uint32_t val; 226 227 val = mmio_read_32(IMX_GPC_BASE + SLPCR); 228 val &= ~(SLPCR_EN_DSM | SLPCR_VSTBY | SLPCR_SBYOS | 229 SLPCR_BYPASS_PMIC_READY | SLPCR_A53_FASTWUP_STOP_MODE); 230 231 if (retention) 232 val |= (SLPCR_EN_DSM | SLPCR_VSTBY | SLPCR_SBYOS | 233 SLPCR_BYPASS_PMIC_READY | SLPCR_A53_FASTWUP_STOP_MODE); 234 235 mmio_write_32(IMX_GPC_BASE + SLPCR, val); 236 237 /* config the noc power down */ 238 imx_noc_slot_config(retention); 239 240 /* config wakeup irqs' mask in gpc */ 241 imx_set_sys_wakeup(last_core, retention); 242 } 243 244 void imx_set_rbc_count(void) 245 { 246 mmio_setbits_32(IMX_GPC_BASE + SLPCR, SLPCR_RBC_EN | 247 (0x8 << SLPCR_RBC_COUNT_SHIFT)); 248 } 249 250 void imx_clear_rbc_count(void) 251 { 252 mmio_clrbits_32(IMX_GPC_BASE + SLPCR, SLPCR_RBC_EN | 253 (0x3f << SLPCR_RBC_COUNT_SHIFT)); 254 } 255 256 struct pll_override { 257 uint32_t reg; 258 uint32_t override_mask; 259 }; 260 261 struct pll_override pll[MAX_PLL_NUM] = { 262 {.reg = 0x0, .override_mask = (1 << 12) | (1 << 8), }, 263 {.reg = 0x14, .override_mask = (1 << 12) | (1 << 8), }, 264 {.reg = 0x28, .override_mask = (1 << 12) | (1 << 8), }, 265 {.reg = 0x50, .override_mask = (1 << 12) | (1 << 8), }, 266 {.reg = 0x64, .override_mask = (1 << 10) | (1 << 8), }, 267 {.reg = 0x74, .override_mask = (1 << 10) | (1 << 8), }, 268 {.reg = 0x84, .override_mask = (1 << 10) | (1 << 8), }, 269 {.reg = 0x94, .override_mask = 0x5555500, }, 270 {.reg = 0x104, .override_mask = 0x5555500, }, 271 {.reg = 0x114, .override_mask = 0x500, }, 272 }; 273 274 #define PLL_BYPASS BIT(4) 275 void imx_anamix_override(bool enter) 276 { 277 unsigned int i; 278 279 /* 280 * bypass all the plls & enable the override bit before 281 * entering DSM mode. 282 */ 283 for (i = 0U; i < MAX_PLL_NUM; i++) { 284 if (enter) { 285 mmio_setbits_32(IMX_ANAMIX_BASE + pll[i].reg, PLL_BYPASS); 286 mmio_setbits_32(IMX_ANAMIX_BASE + pll[i].reg, pll[i].override_mask); 287 } else { 288 mmio_clrbits_32(IMX_ANAMIX_BASE + pll[i].reg, PLL_BYPASS); 289 mmio_clrbits_32(IMX_ANAMIX_BASE + pll[i].reg, pll[i].override_mask); 290 } 291 } 292 } 293