1 /* 2 * Copyright 2019-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <lib/mmio.h> 8 9 #include <dram.h> 10 11 struct dram_info dram_info; 12 13 /* Restore the ddrc configs */ 14 void dram_umctl2_init(struct dram_timing_info *timing) 15 { 16 struct dram_cfg_param *ddrc_cfg = timing->ddrc_cfg; 17 unsigned int i; 18 19 for (i = 0U; i < timing->ddrc_cfg_num; i++) { 20 mmio_write_32(ddrc_cfg->reg, ddrc_cfg->val); 21 ddrc_cfg++; 22 } 23 24 /* set the default fsp to P0 */ 25 mmio_write_32(DDRC_MSTR2(0), 0x0); 26 } 27 28 /* Restore the dram PHY config */ 29 void dram_phy_init(struct dram_timing_info *timing) 30 { 31 struct dram_cfg_param *cfg = timing->ddrphy_cfg; 32 unsigned int i; 33 34 /* Restore the PHY init config */ 35 cfg = timing->ddrphy_cfg; 36 for (i = 0U; i < timing->ddrphy_cfg_num; i++) { 37 dwc_ddrphy_apb_wr(cfg->reg, cfg->val); 38 cfg++; 39 } 40 41 /* Restore the DDR PHY CSRs */ 42 cfg = timing->ddrphy_trained_csr; 43 for (i = 0U; i < timing->ddrphy_trained_csr_num; i++) { 44 dwc_ddrphy_apb_wr(cfg->reg, cfg->val); 45 cfg++; 46 } 47 48 /* Load the PIE image */ 49 cfg = timing->ddrphy_pie; 50 for (i = 0U; i < timing->ddrphy_pie_num; i++) { 51 dwc_ddrphy_apb_wr(cfg->reg, cfg->val); 52 cfg++; 53 } 54 } 55 56 void dram_info_init(unsigned long dram_timing_base) 57 { 58 uint32_t ddrc_mstr, current_fsp; 59 60 /* Get the dram type & rank */ 61 ddrc_mstr = mmio_read_32(DDRC_MSTR(0)); 62 63 dram_info.dram_type = ddrc_mstr & DDR_TYPE_MASK; 64 dram_info.num_rank = (ddrc_mstr >> 24) & ACTIVE_RANK_MASK; 65 66 /* Get current fsp info */ 67 current_fsp = mmio_read_32(DDRC_DFIMISC(0)) & 0xf; 68 dram_info.boot_fsp = current_fsp; 69 dram_info.current_fsp = current_fsp; 70 71 dram_info.timing_info = (struct dram_timing_info *)dram_timing_base; 72 } 73