xref: /rk3399_ARM-atf/plat/socionext/synquacer/sq_io_storage.c (revision 48ab390444e1dabb669430ace9b8e5a80348eed0)
1 /*
2  * Copyright (c) 2022, Socionext Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 #include <errno.h>
9 #include <stdint.h>
10 
11 #include <drivers/io/io_block.h>
12 #include <drivers/io/io_driver.h>
13 #include <drivers/io/io_fip.h>
14 #include <drivers/io/io_memmap.h>
15 #include <lib/mmio.h>
16 #include <lib/utils_def.h>
17 #include <lib/xlat_tables/xlat_tables_v2.h>
18 #include <tools_share/firmware_image_package.h>
19 
20 #include <platform_def.h>
21 #include <sq_common.h>
22 
23 static const io_dev_connector_t *sq_fip_dev_con;
24 static uintptr_t sq_fip_dev_handle;
25 
26 static const io_dev_connector_t *sq_backend_dev_con;
27 static uintptr_t sq_backend_dev_handle;
28 
29 static io_block_spec_t sq_fip_spec = {
30 	.offset = PLAT_SQ_FIP_IOBASE,	/* FIP Image is at 5MB offset on memory-mapped NOR flash */
31 	.length = PLAT_SQ_FIP_MAXSIZE,	/* Expected maximum FIP image size */
32 };
33 
34 static const io_uuid_spec_t sq_bl2_spec = {
35 	.uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2,
36 };
37 
38 static const io_uuid_spec_t sq_bl31_spec = {
39 	.uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
40 };
41 
42 static const io_uuid_spec_t sq_bl32_spec = {
43 	.uuid = UUID_SECURE_PAYLOAD_BL32,
44 };
45 
46 static const io_uuid_spec_t sq_bl33_spec = {
47 	.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
48 };
49 
50 struct sq_io_policy {
51 	uintptr_t *dev_handle;
52 	uintptr_t image_spec;
53 	uintptr_t init_params;
54 };
55 
56 static const struct sq_io_policy sq_io_policies[] = {
57 	[FIP_IMAGE_ID] = {
58 		.dev_handle = &sq_backend_dev_handle,
59 		.image_spec = (uintptr_t)&sq_fip_spec,
60 	},
61 	[BL2_IMAGE_ID] = {
62 		.dev_handle = &sq_fip_dev_handle,
63 		.image_spec = (uintptr_t)&sq_bl2_spec,
64 		.init_params = FIP_IMAGE_ID,
65 	},
66 	[BL31_IMAGE_ID] = {
67 		.dev_handle = &sq_fip_dev_handle,
68 		.image_spec = (uintptr_t)&sq_bl31_spec,
69 		.init_params = FIP_IMAGE_ID,
70 	},
71 	[BL32_IMAGE_ID] = {
72 		.dev_handle = &sq_fip_dev_handle,
73 		.image_spec = (uintptr_t)&sq_bl32_spec,
74 		.init_params = FIP_IMAGE_ID,
75 	},
76 	[BL33_IMAGE_ID] = {
77 		.dev_handle = &sq_fip_dev_handle,
78 		.image_spec = (uintptr_t)&sq_bl33_spec,
79 		.init_params = FIP_IMAGE_ID,
80 	},
81 };
82 
83 static int sq_io_memmap_setup(void)
84 {
85 	int ret;
86 
87 	ret = mmap_add_dynamic_region(sq_fip_spec.offset, sq_fip_spec.offset,
88 				      sq_fip_spec.length, MT_RO_DATA | MT_SECURE);
89 	if (ret) {
90 		return ret;
91 	}
92 
93 	ret = register_io_dev_memmap(&sq_backend_dev_con);
94 	if (ret) {
95 		return ret;
96 	}
97 
98 	return io_dev_open(sq_backend_dev_con, 0, &sq_backend_dev_handle);
99 }
100 
101 static int sq_io_fip_setup(void)
102 {
103 	int ret;
104 
105 	ret = register_io_dev_fip(&sq_fip_dev_con);
106 	if (ret) {
107 		return ret;
108 	}
109 
110 	return io_dev_open(sq_fip_dev_con, 0, &sq_fip_dev_handle);
111 }
112 
113 int sq_io_setup(void)
114 {
115 	int ret;
116 
117 	ret = sq_io_memmap_setup();
118 	if (ret) {
119 		return ret;
120 	}
121 
122 	ret = sq_io_fip_setup();
123 	if (ret) {
124 		return ret;
125 	}
126 
127 	return 0;
128 }
129 
130 int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
131 			  uintptr_t *image_spec)
132 {
133 	uintptr_t init_params;
134 
135 	assert(image_id < ARRAY_SIZE(sq_io_policies));
136 
137 	*dev_handle = *sq_io_policies[image_id].dev_handle;
138 	*image_spec = sq_io_policies[image_id].image_spec;
139 	init_params = sq_io_policies[image_id].init_params;
140 
141 	return io_dev_init(*dev_handle, init_params);
142 }
143