Merge "fix(versal_net): fix irq for IPI0" into integration

Merge "refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3" into integration

refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3

BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is runnin

refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3

BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is running at EL3 exception level
These two scenarios are not exactly same even though first implicitly
means second to be true. To distinguish between these two use cases we
introduce new macros.
BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2.
Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where
BL2 runs at EL3 (including four world systems).

BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the
repository.

Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>

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feat(morello): implement methods to retrieve soc-id information

Added silicon revision in the platform information SDS structure.

Implemented platform functions to retrieve the soc-id information
f

feat(morello): implement methods to retrieve soc-id information

Added silicon revision in the platform information SDS structure.

Implemented platform functions to retrieve the soc-id information
for the morello SoC platform. SoC revision, which is same as
silicon revision, is fetched from the morello_plat_info structure
and SoC version is populated with the part number from SSC_VERSION
register, and is reflected in bits[0:15] of soc-id.

Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: I8e0c5b2bc21e393e6d638858cc2ea9f4638f04b9

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fix(versal_net): fix irq for IPI0

Currently isr is not called when IPI0 interrupt occurs.
fix irq number and enable GIC interrupt properly to invoke
registered isr on IPI0 interrupt.

Signed-off-by:

fix(versal_net): fix irq for IPI0

Currently isr is not called when IPI0 interrupt occurs.
fix irq number and enable GIC interrupt properly to invoke
registered isr on IPI0 interrupt.

Signed-off-by: Trung Tran <trung.tran@amd.com>
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: Id0408b3a560b25234886a9fa01c4ed248d1d1532

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Merge "fix(tegra): append major revision to the chip_id value" into integration

Merge "fix(ti): do not take system power reference in bl31_platform_setup()" into integration

Merge "style: remove useless trailing semicolon and line continuations" into integration

feat(qemu): add "neoverse-n1" cpu support

Add support to qemu "neoverse-n1" cpu for "qemu_sbsa" ('sbsa-ref')
platform.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I4620e879c7111

feat(qemu): add "neoverse-n1" cpu support

Add support to qemu "neoverse-n1" cpu for "qemu_sbsa" ('sbsa-ref')
platform.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I4620e879c71115451ae91a1643812d89ec7c071f

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feat(qemu): make coherent memory section optional

Since CPUs such as cortex-a76 are hardware-assisted coherent, coherent
memory section is not required for them and should be an optional
section.

S

feat(qemu): make coherent memory section optional

Since CPUs such as cortex-a76 are hardware-assisted coherent, coherent
memory section is not required for them and should be an optional
section.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I03c8e9148ca1780b8af92024359698f4452f7129

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refactor(qemu): make use of setup_page_tables()

Use the setup_page_tables() helper function to setup page tables.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I0bca4e463ed68abf2e

refactor(qemu): make use of setup_page_tables()

Use the setup_page_tables() helper function to setup page tables.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I0bca4e463ed68abf2ef1c79fc8e5cb2b635fcd1c

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Merge "fix(tegra210): support legacy SMC_ID 0xC2FEFE00" into integration

Merge changes from topic "xlnx_ipi_fix" into integration

* changes:
fix(xilinx): handle CRC failure in IPI callback
fix(xilinx): handle CRC failure in IPI

fix(tegra210): support legacy SMC_ID 0xC2FEFE00

This patch introduces a workaround to support the legacy SMC FID
0xC2FEFE00 to maintain compatibility with older software components.

Change-Id: Icf2

fix(tegra210): support legacy SMC_ID 0xC2FEFE00

This patch introduces a workaround to support the legacy SMC FID
0xC2FEFE00 to maintain compatibility with older software components.

Change-Id: Icf2ef9cfa6b28c09bbab325a642d0b3b20b23535
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>

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fix(tegra): append major revision to the chip_id value

This patch appends the chip's major revision to the chip id value
to form the SoC version value expected by the SMCCC_GET_SOC_VERSION
function

fix(tegra): append major revision to the chip_id value

This patch appends the chip's major revision to the chip id value
to form the SoC version value expected by the SMCCC_GET_SOC_VERSION
function ID.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I09118f446f6b8198588826d4a161bd97dcb6a581

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Merge changes from topic "imx8m_misc_changes" into integration

* changes:
feat(imx8mq): enable dram dvfs support on imx8mq
feat(imx8m): use non-fast wakeup stop mode for system suspend
feat(im

Merge changes from topic "imx8m_misc_changes" into integration

* changes:
feat(imx8mq): enable dram dvfs support on imx8mq
feat(imx8m): use non-fast wakeup stop mode for system suspend
feat(imx8mq): correct the slot ack setting for STOP mode
feat(imx8mq): add anamix pll override setting for DSM mode
feat(imx8mq): add workaround code for ERR11171 on imx8mq
feat(imx8mq): add the dram retention support for imx8mq
feat(imx8mq): add version for B2
fix(imx8m): backup mr12/14 value from lpddr4 chip
fix(imx8m): add ddr4 dvfs sw workaround for ERR050712
fix(imx8m): fix coverity out of bound access issue
fix(imx8m): fix the dram retention random hang on some imx8mq Rev2.0
feat(imx8m): add more dram pll setting
fix(imx8m): fix the current fsp init
fix(imx8m): fix the rank to rank space issue
fix(imx8m): fix the dfiphymaster setting after dvfs
feat(imx8m): update the ddr4 dvfs flow to include ddr3l support
fix(imx8m): correct the rank info get fro mstr
feat(imx8m): fix the ddr4 dvfs random hang on imx8m

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style: remove useless trailing semicolon and line continuations

found using checkpatch.pl[1]

[1]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/lint/checkpatch.pl

S

style: remove useless trailing semicolon and line continuations

found using checkpatch.pl[1]

[1]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/lint/checkpatch.pl

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I7957c9694300fefb85d11f7819c43af95271f14c

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fix(xilinx): handle CRC failure in IPI callback

Currently, if CRC validation fails during IPI communication,
pm_ipi_buff_read_callb() logs error message but don't return
error code to upper layers.

fix(xilinx): handle CRC failure in IPI callback

Currently, if CRC validation fails during IPI communication,
pm_ipi_buff_read_callb() logs error message but don't return
error code to upper layers.

Added CRC failure specific error code which will be returned by
pm_ipi_buff_read_callb() if CRC validation fails.

Signed-off-by: Naman Trivedi Manojbhai <naman.trivedimanojbhai@amd.com>
Change-Id: I2eaca073e2bf325a8c86b1820bdd7cca487b783e

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fix(xilinx): handle CRC failure in IPI

Currently, if CRC validation fails during IPI communication,
pm_ipi_buff_read() logs error message but don't return error
code to upper layers.

Added CRC fail

fix(xilinx): handle CRC failure in IPI

Currently, if CRC validation fails during IPI communication,
pm_ipi_buff_read() logs error message but don't return error
code to upper layers.

Added CRC failure specific error code which will be returned by
pm_ipi_buff_read() if CRC validation fails.

Signed-off-by: Naman Trivedi Manojbhai <naman.trivedimanojbhai@amd.com>
Change-Id: I33be330f276973471f4ce4115d1e1609ed8fb754

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feat(fvp): copy the Event Log to TZC secured DRAM area

Copied the Event Log from internal SRAM to the TZC secured DRAM
reserved area. Also passed this Trusted DRAM address to OPTEE via
NT FW configu

feat(fvp): copy the Event Log to TZC secured DRAM area

Copied the Event Log from internal SRAM to the TZC secured DRAM
reserved area. Also passed this Trusted DRAM address to OPTEE via
NT FW configuration, and to SPMC via TOS FW configuration,
which is eventually used to extend PCR via fTPM application running
on top of OPTEE/SPMC.

Furthermore, this patch makes it easier to access Event Log in RME
enabled systems where Secure World firmware does not have access to
internal(Root) SRAM.

Change-Id: I005e9da1e6075511f412bdf4d8b541fa543df9ab
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(arm): carveout DRAM1 area for Event Log

Reserved 4KB area for Event Log in DRAM1. This area is used by BL2
to copy Event Log from internal SRAM to this carved out DRAM region
in the subsequent

feat(arm): carveout DRAM1 area for Event Log

Reserved 4KB area for Event Log in DRAM1. This area is used by BL2
to copy Event Log from internal SRAM to this carved out DRAM region
in the subsequent patch.

Change-Id: I7b405775c66d249e31edf7688d95770e6c05c175
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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test(tc): test for AP/RSS NV counter interface

Change in PLATFORM_TEST build flag from boolean -> string, with the
current string options being tfm-testsuite and rss-nv-counters.

To get the old beh

test(tc): test for AP/RSS NV counter interface

Change in PLATFORM_TEST build flag from boolean -> string, with the
current string options being tfm-testsuite and rss-nv-counters.

To get the old behavior, i.e. where we used to use PLATFORM_TEST=1,
we now need to pass PLATFORM_TEST=tfm-testsuite.

Adding new test of the AP/RSS interface for non-volatile counters.
The test reads, increments, and reads again each 3 types of NV
counters for: CCA, secure, and non-secure firmware. Enabled by
PLATFORM_TEST=rss-nv-counters.

Change-Id: I2044cc9b2f37984697e0754c9c824eab51a11e7f
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Signed-off-by: Raef Coles <raef.coles@arm.com>

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fix(tc): change the FIP offset to 8 KiB boundary

* This change overrides the default PLAT_ARM_FIP_OFFSET_IN_GPT

* This aligns the FIP base in GPT image to the RSS ATU page size
boundary (8 KiB).

fix(tc): change the FIP offset to 8 KiB boundary

* This change overrides the default PLAT_ARM_FIP_OFFSET_IN_GPT

* This aligns the FIP base in GPT image to the RSS ATU page size
boundary (8 KiB). RSS XIP feature requires the FIP to be aligned to
the page size boundary. TC platform will require the XIP feature.

* The aligned FIP_A is starting at sector 48. Hence the offset will be
48*512 = 0x6000.

Signed-off-by: Tintu Thomas <tintu.thomas@arm.com>
Change-Id: I8135ecd4168231847c80151c33ef8353a1586b9a

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fix(ti): do not take system power reference in bl31_platform_setup()

Taking a reference at this early stage can cause boot failure if the DM
firmware is not fully initialized. Remove this early call

fix(ti): do not take system power reference in bl31_platform_setup()

Taking a reference at this early stage can cause boot failure if the DM
firmware is not fully initialized. Remove this early call until the
fix in DM firmware is widely available.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ic9c47ccf1e9a1b9faeb1c7d2665d54cf55ef5396

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fix(zynqmp): conditional reservation of memory in DTB

When the TF-A is placed in DDR memory range, the DDR memory range is
getting explicitly reserved in the default device tree by TF-A.
This create

fix(zynqmp): conditional reservation of memory in DTB

When the TF-A is placed in DDR memory range, the DDR memory range is
getting explicitly reserved in the default device tree by TF-A.
This creates an error condition in the use case where Device tree is
not present or it is present at a different location.

To fix this, a new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is
introduced. The TF-A will reserve the DDR memory only when a valid
DTB address is provided to XILINX_OF_BOARD_DTB_ADDR during build.

Now the user has options, either manually reserve the desired
DDR address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.

Change-Id: I846fa373ba9f7c984eda3a55ccaaa622082cad81
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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