1 /* 2 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 3 * Copyright (c) 2022-2023, Advanced Micro Devices Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /* Versal power management enums and defines */ 9 10 #ifndef PM_DEFS_H 11 #define PM_DEFS_H 12 13 #include "pm_node.h" 14 15 /********************************************************************* 16 * Macro definitions 17 ********************************************************************/ 18 19 /* State arguments of the self suspend */ 20 #define PM_STATE_CPU_IDLE 0x0U 21 #define PM_STATE_SUSPEND_TO_RAM 0xFU 22 23 #define MAX_LATENCY (~0U) 24 #define MAX_QOS 100U 25 26 /* Processor core device IDs */ 27 #define APU_DEVID(IDX) NODEID(XPM_NODECLASS_DEVICE, XPM_NODESUBCL_DEV_CORE, \ 28 XPM_NODETYPE_DEV_CORE_APU, (IDX)) 29 30 #define XPM_DEVID_ACPU_0 APU_DEVID(XPM_NODEIDX_DEV_ACPU_0) 31 #define XPM_DEVID_ACPU_1 APU_DEVID(XPM_NODEIDX_DEV_ACPU_1) 32 33 #define PERIPH_DEVID(IDX) NODEID((uint32_t)XPM_NODECLASS_DEVICE, \ 34 (uint32_t)XPM_NODESUBCL_DEV_PERIPH, \ 35 (uint32_t)XPM_NODETYPE_DEV_PERIPH, (IDX)) 36 37 #define PM_GET_CALLBACK_DATA 0xa01U 38 #define PM_GET_TRUSTZONE_VERSION 0xa03U 39 #define TF_A_PM_REGISTER_SGI 0xa04U 40 41 /* PM API Versions */ 42 #define PM_API_BASE_VERSION 1U 43 #define PM_API_VERSION_2 2U 44 45 /* Loader API ids */ 46 #define PM_LOAD_PDI 0x701U 47 #define PM_LOAD_GET_HANDOFF_PARAMS 0x70BU 48 49 /* IOCTL IDs for clock driver */ 50 #define IOCTL_SET_PLL_FRAC_MODE 8U 51 #define IOCTL_GET_PLL_FRAC_MODE 9U 52 #define IOCTL_SET_PLL_FRAC_DATA 10U 53 #define IOCTL_GET_PLL_FRAC_DATA 11U 54 #define IOCTL_SET_SGI 25U 55 56 /* System shutdown macros */ 57 #define XPM_SHUTDOWN_TYPE_SHUTDOWN 0U 58 #define XPM_SHUTDOWN_TYPE_RESET 1U 59 #define XPM_SHUTDOWN_TYPE_SETSCOPE_ONLY 2U 60 61 #define XPM_SHUTDOWN_SUBTYPE_RST_SUBSYSTEM 0U 62 #define XPM_SHUTDOWN_SUBTYPE_RST_PS_ONLY 1U 63 #define XPM_SHUTDOWN_SUBTYPE_RST_SYSTEM 2U 64 65 /********************************************************************* 66 * Enum definitions 67 ********************************************************************/ 68 69 /** 70 * @PM_PLL_PARAM_DIV2: Enable for divide by 2 function inside the PLL 71 * @PM_PLL_PARAM_FBDIV: Feedback divisor integer portion for the PLL 72 * @PM_PLL_PARAM_DATA: Feedback divisor fractional portion for the PLL 73 * @PM_PLL_PARAM_PRE_SRC: Clock source for PLL input 74 * @PM_PLL_PARAM_POST_SRC: Clock source for PLL Bypass mode 75 * @PM_PLL_PARAM_LOCK_DLY: Lock circuit config settings for lock windowsize 76 * @PM_PLL_PARAM_LOCK_CNT: Lock circuit counter setting 77 * @PM_PLL_PARAM_LFHF: PLL loop filter high frequency capacitor control 78 * @PM_PLL_PARAM_CP: PLL charge pump control 79 * @PM_PLL_PARAM_RES: PLL loop filter resistor control 80 */ 81 enum pm_pll_param { 82 PM_PLL_PARAM_DIV2, 83 PM_PLL_PARAM_FBDIV, 84 PM_PLL_PARAM_DATA, 85 PM_PLL_PARAM_PRE_SRC, 86 PM_PLL_PARAM_POST_SRC, 87 PM_PLL_PARAM_LOCK_DLY, 88 PM_PLL_PARAM_LOCK_CNT, 89 PM_PLL_PARAM_LFHF, 90 PM_PLL_PARAM_CP, 91 PM_PLL_PARAM_RES, 92 PM_PLL_PARAM_MAX, 93 }; 94 95 enum pm_api_id { 96 /* Miscellaneous API functions: */ 97 PM_GET_API_VERSION = 1, /* Do not change or move */ 98 PM_SET_CONFIGURATION, 99 PM_GET_NODE_STATUS, 100 PM_GET_OP_CHARACTERISTIC, 101 PM_REGISTER_NOTIFIER, 102 /* API for suspending of PUs: */ 103 PM_REQ_SUSPEND, 104 PM_SELF_SUSPEND, 105 PM_FORCE_POWERDOWN, 106 PM_ABORT_SUSPEND, 107 PM_REQ_WAKEUP, 108 PM_SET_WAKEUP_SOURCE, 109 PM_SYSTEM_SHUTDOWN, 110 /* API for managing PM slaves: */ 111 PM_REQ_NODE, 112 PM_RELEASE_NODE, 113 PM_SET_REQUIREMENT, 114 PM_SET_MAX_LATENCY, 115 /* Direct control API functions: */ 116 PM_RESET_ASSERT, 117 PM_RESET_GET_STATUS, 118 PM_MMIO_WRITE, 119 PM_MMIO_READ, 120 PM_INIT_FINALIZE, 121 PM_FPGA_LOAD, 122 PM_FPGA_GET_STATUS, 123 PM_GET_CHIPID, 124 PM_SECURE_RSA_AES, 125 PM_SECURE_SHA, 126 PM_SECURE_RSA, 127 PM_PINCTRL_REQUEST, 128 PM_PINCTRL_RELEASE, 129 PM_PINCTRL_GET_FUNCTION, 130 PM_PINCTRL_SET_FUNCTION, 131 PM_PINCTRL_CONFIG_PARAM_GET, 132 PM_PINCTRL_CONFIG_PARAM_SET, 133 PM_IOCTL, 134 /* API to query information from firmware */ 135 PM_QUERY_DATA, 136 /* Clock control API functions */ 137 PM_CLOCK_ENABLE, 138 PM_CLOCK_DISABLE, 139 PM_CLOCK_GETSTATE, 140 PM_CLOCK_SETDIVIDER, 141 PM_CLOCK_GETDIVIDER, 142 PM_CLOCK_SETRATE, 143 PM_CLOCK_GETRATE, 144 PM_CLOCK_SETPARENT, 145 PM_CLOCK_GETPARENT, 146 PM_SECURE_IMAGE, 147 /* FPGA PL Readback */ 148 PM_FPGA_READ, 149 PM_SECURE_AES, 150 /* PLL control API functions */ 151 PM_PLL_SET_PARAMETER, 152 PM_PLL_GET_PARAMETER, 153 PM_PLL_SET_MODE, 154 PM_PLL_GET_MODE, 155 /* PM Register Access API */ 156 PM_REGISTER_ACCESS, 157 PM_EFUSE_ACCESS, 158 PM_FPGA_GET_VERSION, 159 PM_FPGA_GET_FEATURE_LIST, 160 PM_FEATURE_CHECK = 63, 161 PM_API_MAX = 74 162 }; 163 164 enum pm_abort_reason { 165 ABORT_REASON_WKUP_EVENT = 100, 166 ABORT_REASON_PU_BUSY, 167 ABORT_REASON_NO_PWRDN, 168 ABORT_REASON_UNKNOWN, 169 }; 170 171 enum pm_opchar_type { 172 PM_OPCHAR_TYPE_POWER = 1, 173 PM_OPCHAR_TYPE_TEMP, 174 PM_OPCHAR_TYPE_LATENCY, 175 }; 176 177 /** 178 * Subsystem IDs 179 */ 180 typedef enum { 181 XPM_SUBSYSID_PMC, 182 XPM_SUBSYSID_PSM, 183 XPM_SUBSYSID_APU, 184 XPM_SUBSYSID_RPU0_LOCK, 185 XPM_SUBSYSID_RPU0_0, 186 XPM_SUBSYSID_RPU0_1, 187 XPM_SUBSYSID_DDR0, 188 XPM_SUBSYSID_ME, 189 XPM_SUBSYSID_PL, 190 XPM_SUBSYSID_MAX, 191 } XPm_SubsystemId; 192 193 /* TODO: move pm_ret_status from device specific location to common location */ 194 /** 195 * @PM_RET_SUCCESS: success 196 * @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated) 197 * @PM_RET_ERROR_NOTSUPPORTED: feature not supported (deprecated) 198 * @PM_RET_ERROR_NOFEATURE: feature is not available 199 * @PM_RET_ERROR_INVALID_CRC: invalid crc in IPI communication 200 * @PM_RET_ERROR_NOT_ENABLED: feature is not enabled 201 * @PM_RET_ERROR_INTERNAL: internal error 202 * @PM_RET_ERROR_CONFLICT: conflict 203 * @PM_RET_ERROR_ACCESS: access rights violation 204 * @PM_RET_ERROR_INVALID_NODE: invalid node 205 * @PM_RET_ERROR_DOUBLE_REQ: duplicate request for same node 206 * @PM_RET_ERROR_ABORT_SUSPEND: suspend procedure has been aborted 207 * @PM_RET_ERROR_TIMEOUT: timeout in communication with PMU 208 * @PM_RET_ERROR_NODE_USED: node is already in use 209 */ 210 enum pm_ret_status { 211 PM_RET_SUCCESS, 212 PM_RET_ERROR_ARGS = 1, 213 PM_RET_ERROR_NOTSUPPORTED = 4, 214 PM_RET_ERROR_NOFEATURE = 19, 215 PM_RET_ERROR_INVALID_CRC = 301, 216 PM_RET_ERROR_NOT_ENABLED = 29, 217 PM_RET_ERROR_INTERNAL = 2000, 218 PM_RET_ERROR_CONFLICT = 2001, 219 PM_RET_ERROR_ACCESS = 2002, 220 PM_RET_ERROR_INVALID_NODE = 2003, 221 PM_RET_ERROR_DOUBLE_REQ = 2004, 222 PM_RET_ERROR_ABORT_SUSPEND = 2005, 223 PM_RET_ERROR_TIMEOUT = 2006, 224 PM_RET_ERROR_NODE_USED = 2007, 225 PM_RET_ERROR_NO_FEATURE = 2008 226 }; 227 228 /** 229 * Qids 230 */ 231 enum pm_query_id { 232 XPM_QID_INVALID, 233 XPM_QID_CLOCK_GET_NAME, 234 XPM_QID_CLOCK_GET_TOPOLOGY, 235 XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS, 236 XPM_QID_CLOCK_GET_MUXSOURCES, 237 XPM_QID_CLOCK_GET_ATTRIBUTES, 238 XPM_QID_PINCTRL_GET_NUM_PINS, 239 XPM_QID_PINCTRL_GET_NUM_FUNCTIONS, 240 XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS, 241 XPM_QID_PINCTRL_GET_FUNCTION_NAME, 242 XPM_QID_PINCTRL_GET_FUNCTION_GROUPS, 243 XPM_QID_PINCTRL_GET_PIN_GROUPS, 244 XPM_QID_CLOCK_GET_NUM_CLOCKS, 245 XPM_QID_CLOCK_GET_MAX_DIVISOR, 246 XPM_QID_PLD_GET_PARENT, 247 }; 248 #endif /* PM_DEFS_H */ 249