1 /* 2 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2023, Advanced Micro Devices Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ZYNQMP_PM_API_SYS_H 9 #define ZYNQMP_PM_API_SYS_H 10 11 #include <stdint.h> 12 13 #include "pm_defs.h" 14 15 enum pm_query_id { 16 PM_QID_INVALID, 17 PM_QID_CLOCK_GET_NAME, 18 PM_QID_CLOCK_GET_TOPOLOGY, 19 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS, 20 PM_QID_CLOCK_GET_PARENTS, 21 PM_QID_CLOCK_GET_ATTRIBUTES, 22 PM_QID_PINCTRL_GET_NUM_PINS, 23 PM_QID_PINCTRL_GET_NUM_FUNCTIONS, 24 PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS, 25 PM_QID_PINCTRL_GET_FUNCTION_NAME, 26 PM_QID_PINCTRL_GET_FUNCTION_GROUPS, 27 PM_QID_PINCTRL_GET_PIN_GROUPS, 28 PM_QID_CLOCK_GET_NUM_CLOCKS, 29 PM_QID_CLOCK_GET_MAX_DIVISOR, 30 }; 31 32 enum pm_register_access_id { 33 CONFIG_REG_WRITE, 34 CONFIG_REG_READ, 35 }; 36 37 /** 38 * Assigning of argument values into array elements. 39 */ 40 #define PM_PACK_PAYLOAD1(pl, arg0) { \ 41 pl[0] = (uint32_t)(arg0); \ 42 } 43 44 #define PM_PACK_PAYLOAD2(pl, arg0, arg1) { \ 45 pl[1] = (uint32_t)(arg1); \ 46 PM_PACK_PAYLOAD1(pl, arg0); \ 47 } 48 49 #define PM_PACK_PAYLOAD3(pl, arg0, arg1, arg2) { \ 50 pl[2] = (uint32_t)(arg2); \ 51 PM_PACK_PAYLOAD2(pl, arg0, arg1); \ 52 } 53 54 #define PM_PACK_PAYLOAD4(pl, arg0, arg1, arg2, arg3) { \ 55 pl[3] = (uint32_t)(arg3); \ 56 PM_PACK_PAYLOAD3(pl, arg0, arg1, arg2); \ 57 } 58 59 #define PM_PACK_PAYLOAD5(pl, arg0, arg1, arg2, arg3, arg4) { \ 60 pl[4] = (uint32_t)(arg4); \ 61 PM_PACK_PAYLOAD4(pl, arg0, arg1, arg2, arg3); \ 62 } 63 64 #define PM_PACK_PAYLOAD6(pl, arg0, arg1, arg2, arg3, arg4, arg5) { \ 65 pl[5] = (uint32_t)(arg5); \ 66 PM_PACK_PAYLOAD5(pl, arg0, arg1, arg2, arg3, arg4); \ 67 } 68 69 /********************************************************** 70 * System-level API function declarations 71 **********************************************************/ 72 enum pm_ret_status pm_req_suspend(enum pm_node_id target, 73 enum pm_request_ack ack, 74 uint32_t latency, 75 uint32_t state); 76 77 enum pm_ret_status pm_self_suspend(enum pm_node_id nid, 78 uint32_t latency, 79 uint32_t state, 80 uintptr_t address); 81 82 enum pm_ret_status pm_force_powerdown(enum pm_node_id target, 83 enum pm_request_ack ack); 84 85 enum pm_ret_status pm_abort_suspend(enum pm_abort_reason reason); 86 87 enum pm_ret_status pm_req_wakeup(enum pm_node_id target, 88 uint32_t set_address, 89 uintptr_t address, 90 enum pm_request_ack ack); 91 92 enum pm_ret_status pm_set_wakeup_source(enum pm_node_id target, 93 enum pm_node_id wkup_node, 94 uint32_t enable); 95 96 enum pm_ret_status pm_system_shutdown(uint32_t type, uint32_t subtype); 97 98 /* API functions for managing PM Slaves */ 99 enum pm_ret_status pm_req_node(enum pm_node_id nid, 100 uint32_t capabilities, 101 uint32_t qos, 102 enum pm_request_ack ack); 103 104 enum pm_ret_status pm_set_requirement(enum pm_node_id nid, 105 uint32_t capabilities, 106 uint32_t qos, 107 enum pm_request_ack ack); 108 109 /* Miscellaneous API functions */ 110 enum pm_ret_status pm_get_api_version(uint32_t *version); 111 enum pm_ret_status pm_get_node_status(enum pm_node_id nid, 112 uint32_t *ret_buff); 113 114 /* Direct-Control API functions */ 115 enum pm_ret_status pm_mmio_write(uintptr_t address, 116 uint32_t mask, 117 uint32_t value); 118 enum pm_ret_status pm_mmio_read(uintptr_t address, uint32_t *value); 119 enum pm_ret_status pm_fpga_load(uint32_t address_low, 120 uint32_t address_high, 121 uint32_t size, 122 uint32_t flags); 123 enum pm_ret_status pm_fpga_get_status(uint32_t *value); 124 125 enum pm_ret_status pm_get_chipid(uint32_t *value); 126 enum pm_ret_status pm_secure_rsaaes(uint32_t address_low, 127 uint32_t address_high, 128 uint32_t size, 129 uint32_t flags); 130 uint32_t pm_get_shutdown_scope(void); 131 enum pm_ret_status pm_get_callbackdata(uint32_t *data, size_t count); 132 enum pm_ret_status pm_ioctl(enum pm_node_id nid, 133 uint32_t ioctl_id, 134 uint32_t arg1, 135 uint32_t arg2, 136 uint32_t *value); 137 enum pm_ret_status pm_clock_enable(uint32_t clock_id); 138 enum pm_ret_status pm_clock_disable(uint32_t clock_id); 139 enum pm_ret_status pm_clock_getstate(uint32_t clock_id, 140 uint32_t *state); 141 enum pm_ret_status pm_clock_setdivider(uint32_t clock_id, 142 uint32_t divider); 143 enum pm_ret_status pm_clock_getdivider(uint32_t clock_id, 144 uint32_t *divider); 145 enum pm_ret_status pm_clock_setrate(uint32_t clock_id, 146 uint64_t rate); 147 enum pm_ret_status pm_clock_getrate(uint32_t clock_id, 148 uint64_t *rate); 149 enum pm_ret_status pm_clock_setparent(uint32_t clock_id, 150 uint32_t parent_index); 151 enum pm_ret_status pm_clock_getparent(uint32_t clock_id, 152 uint32_t *parent_index); 153 void pm_query_data(enum pm_query_id qid, uint32_t arg1, uint32_t arg2, 154 uint32_t arg3, uint32_t *data); 155 enum pm_ret_status pm_sha_hash(uint32_t address_high, 156 uint32_t address_low, 157 uint32_t size, 158 uint32_t flags); 159 enum pm_ret_status pm_rsa_core(uint32_t address_high, 160 uint32_t address_low, 161 uint32_t size, 162 uint32_t flags); 163 enum pm_ret_status pm_secure_image(uint32_t address_low, 164 uint32_t address_high, 165 uint32_t key_lo, 166 uint32_t key_hi, 167 uint32_t *value); 168 enum pm_ret_status pm_fpga_read(uint32_t reg_numframes, 169 uint32_t address_low, 170 uint32_t address_high, 171 uint32_t readback_type, 172 uint32_t *value); 173 enum pm_ret_status pm_aes_engine(uint32_t address_high, 174 uint32_t address_low, 175 uint32_t *value); 176 enum pm_ret_status pm_register_access(uint32_t register_access_id, 177 uint32_t address, 178 uint32_t mask, 179 uint32_t value, 180 uint32_t *out); 181 enum pm_ret_status pm_pll_set_parameter(enum pm_node_id nid, 182 enum pm_pll_param param_id, 183 uint32_t value); 184 enum pm_ret_status pm_pll_get_parameter(enum pm_node_id nid, 185 enum pm_pll_param param_id, 186 uint32_t *value); 187 enum pm_ret_status pm_pll_set_mode(enum pm_node_id nid, enum pm_pll_mode mode); 188 enum pm_ret_status pm_pll_get_mode(enum pm_node_id nid, enum pm_pll_mode *mode); 189 enum pm_ret_status pm_efuse_access(uint32_t address_high, 190 uint32_t address_low, uint32_t *value); 191 enum pm_ret_status pm_feature_check(uint32_t api_id, uint32_t *version, 192 uint32_t *bit_mask, uint8_t len); 193 enum pm_ret_status check_api_dependency(uint8_t id); 194 195 #endif /* ZYNQMP_PM_API_SYS_H */ 196