feat(s32g274ardb): add DDR register accessories

Introduce a set of helper functions that
simplify register reads, bitfield updates,
AXI parity configuration and extraction
of training values.

These

feat(s32g274ardb): add DDR register accessories

Introduce a set of helper functions that
simplify register reads, bitfield updates,
AXI parity configuration and extraction
of training values.

These utilities encapsulate register access
patterns and are used for delay calibration,
Vref averaging, memory type detection and PLL
source selection.

Change-Id: I5415a650f6430578a8cca13ff7e144b471c61466
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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feat(s32g274ardb): add DDR PHY mailbox support

Introduce mailbox handling between the DDR
controller and the PHY firmware, providing
mechanisms for message exchange, acknowledgments,
and execution s

feat(s32g274ardb): add DDR PHY mailbox support

Introduce mailbox handling between the DDR
controller and the PHY firmware, providing
mechanisms for message exchange, acknowledgments,
and execution status monitoring.

This enables reliable tracking of firmware
progress during DDR initialization and training,

Change-Id: I4fdd582fcc9a88c09c820ce9e59fe14ec3c043a8
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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fix(tc): correct register write in rng trap handler

Fix the TC rng trap handler to write the random value to the correct
GP register. The handler previously passed the register number to
write_ctx_r

fix(tc): correct register write in rng trap handler

Fix the TC rng trap handler to write the random value to the correct
GP register. The handler previously passed the register number to
write_ctx_reg() instead of the register offset which resulted in the
incorrect register being modified.

Change-Id: I1063b7d1e17037f60a745ceb6653cd3419ec6a67
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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feat(imx8m): keep console at runtime when building TF-A/bl31 with DEBUG

Have informal console output at runtime is useful when searching
errors in TF-A.

Change-Id: I56b5c4fc184e571f79d92bd0aa4fc74f

feat(imx8m): keep console at runtime when building TF-A/bl31 with DEBUG

Have informal console output at runtime is useful when searching
errors in TF-A.

Change-Id: I56b5c4fc184e571f79d92bd0aa4fc74ff4ed6074
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

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feat(fvp): extend image decryption support for FVP

Add encryption IO layer to be stacked above FIP IO layer for optional
encryption of the BL31 and BL32 images in case the ENCRYPT_BL31 or
ENCRYPT_BL

feat(fvp): extend image decryption support for FVP

Add encryption IO layer to be stacked above FIP IO layer for optional
encryption of the BL31 and BL32 images in case the ENCRYPT_BL31 or
ENCRYPT_BL32 build flag is set.

Enable decryption support for FVP through setting the DECRYPTION_SUPPORT
build flag. "DECRYPTION_SUPPORT = aes_gcm" is set to perform authenticated
decryption using AES-GCM algorithm.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Iebc3b360b4a0dc0d933b816d28015ac551b79405

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fix(io): add NULL check for spec io_open FIP

Add check to skip io_open() when spec is NULL to prevent invalid access.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I9e9d

fix(io): add NULL check for spec io_open FIP

Add check to skip io_open() when spec is NULL to prevent invalid access.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I9e9df8028c16d57bb9293c00afc1ce61601d8fd8

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fix: remove circular dependency on ENABLE_FEAT_RAS

ENABLE_FEAT_RAS is enabled by arch_features.mk based on the value of
ARM_ARCH_{MAJOR, MINOR}, but that is only called after each platform's
platfor

fix: remove circular dependency on ENABLE_FEAT_RAS

ENABLE_FEAT_RAS is enabled by arch_features.mk based on the value of
ARM_ARCH_{MAJOR, MINOR}, but that is only called after each platform's
platform.mk. That makes a circular dependency when a file needs to be
compiled based on the flag's value.

Well, FEAT_RAS is mandatory from v8.2 and platforms that set
ARM_ARCH_{MAJOR, MINOR} such need not check for its presence - it will
be present. So remove the check to remove the dependency.

Change-Id: I68db83347e6bc04b7ff3b67f6c3e54921641db23
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpus): add support for LSC25 E-core CPU

Add basic CPU library code to support the Large Screen Compute 2025
E-core CPU.

Change-Id: Ibda2e8441d3a3e35941448b483d07e17db2ef234
Signed-off-by: Ryan

feat(cpus): add support for LSC25 E-core CPU

Add basic CPU library code to support the Large Screen Compute 2025
E-core CPU.

Change-Id: Ibda2e8441d3a3e35941448b483d07e17db2ef234
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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feat(cpus): add support for LSC25 P-core CPU

Add basic CPU library code to support the Large Screen Compute 2025
P-core CPU.

Change-Id: Icfd2fdbaed577e64cb2db028416a6eca5ba2cfcf
Signed-off-by: Ryan

feat(cpus): add support for LSC25 P-core CPU

Add basic CPU library code to support the Large Screen Compute 2025
P-core CPU.

Change-Id: Icfd2fdbaed577e64cb2db028416a6eca5ba2cfcf
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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feat(fvp): load SP_PKGs with TRANSFER_LIST

To enable loading of SP_PKGs when using the TRANSFER_LIST build option,
this patch loads TB_FW_CONFIG in BL1 and populates sp_mem_params_descs
in arm_trans

feat(fvp): load SP_PKGs with TRANSFER_LIST

To enable loading of SP_PKGs when using the TRANSFER_LIST build option,
this patch loads TB_FW_CONFIG in BL1 and populates sp_mem_params_descs
in arm_transfer_list_dyn_cfg_init().

Since there is no standard tag_id defined for TB_FW_CONFIG in the
transfer list, define PLAT_ARM_TB_FW_CONFIG_TL_TAG as a platform-specific
identifier to load TB_FW_CONFIG.

With this change, BL2 can load the SP_PKGs specified in TB_FW_CONFIG.

Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I2470c1ef3bf2bf921d0de1fff541565df13eaee4

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fix(allwinner): avoid crash when running without DTB

For determining the PMIC type and the bus its connected to, we use the
DTB that is appended to the U-Boot binary, by looking for it in DRAM.
And

fix(allwinner): avoid crash when running without DTB

For determining the PMIC type and the bus its connected to, we use the
DTB that is appended to the U-Boot binary, by looking for it in DRAM.
And while we bail out correctly if we don't find it there, we later try
to use the DTB pointer - without checking.

Add a check in sunxi_pmic_setup(), to only proceed if we have found a
DTB before, and exit early otherwise.

This fixes more experimental setups, where TF-A is run without U-Boot.

Change-Id: I9a7677be057a84fe6bee093d098be758970eec81
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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fix(intel): remove invalid SDM SMMU Stream ID register from bypass list

The register is SDM-owned and not accessible by HPS.
It was added by mistakein v2.7.0.
Removing it ensures correct access cont

fix(intel): remove invalid SDM SMMU Stream ID register from bypass list

The register is SDM-owned and not accessible by HPS.
It was added by mistakein v2.7.0.
Removing it ensures correct access control.

Change-Id: I76d27e5b53bfb115ace6011dbb79f2fac049bb4e
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): prevent invalid register rejection on non-A5F4 devices

Move TSN_TBU_STREAM_CTRL_REG_3_TSN0/1/2 handling outside the
main switch to ensure non-A5F4 devices (e.g., A5F0) evaluate
other val

fix(intel): prevent invalid register rejection on non-A5F4 devices

Move TSN_TBU_STREAM_CTRL_REG_3_TSN0/1/2 handling outside the
main switch to ensure non-A5F4 devices (e.g., A5F0) evaluate
other valid registers.

Previously, TSN cases were inside the switch and followed
by a `break` if not A5F4, causing early exit and -1 return.
Valid registers (e.g., ECC_INTMASK_x)were rejected, blocking boot.

Now, A5F4 TSN registers are handled conditionally
and fallthrough is clean for all other devices.

Change-Id: I1339e0e3951ccb68f02dc437f25db6c27d2a0877
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(intel): allow kernel access to TSN TBU stream control registers

Added TSN_TBU_STREAM_CTRL_REG_3_TSN0/1/2 to ATF's secure range check
to permit setting the 31st bit from kernel space.

Change-Id:

fix(intel): allow kernel access to TSN TBU stream control registers

Added TSN_TBU_STREAM_CTRL_REG_3_TSN0/1/2 to ATF's secure range check
to permit setting the 31st bit from kernel space.

Change-Id: I74bd296c4c050fb61d4df5c1bd5b57449b3a13e3
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(fvp): use global option for setting PLAT_ARM_MAX_BL2_SIZE

Use global option TRUSTED_BOARD_BOOT for setting PLAT_ARM_MAX_BL2_SIZE.

Change-Id: Ia360b36535d2039de8e41da90dd4c8478adb6d54
Signed-off

fix(fvp): use global option for setting PLAT_ARM_MAX_BL2_SIZE

Use global option TRUSTED_BOARD_BOOT for setting PLAT_ARM_MAX_BL2_SIZE.

Change-Id: Ia360b36535d2039de8e41da90dd4c8478adb6d54
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "chore(fvp): bump maximum permitted Trusted SRAM size" into integration

Merge "fix(versal2): align comment about invalid console selection" into integration

chore(fvp): bump maximum permitted Trusted SRAM size

Bump the size of the Trusted SRAM in FVP builds, as we are now exceeding
the 256KB limit in a meaningful number of builds.

Change-Id: Iefd584172

chore(fvp): bump maximum permitted Trusted SRAM size

Bump the size of the Trusted SRAM in FVP builds, as we are now exceeding
the 256KB limit in a meaningful number of builds.

Change-Id: Iefd58417297507eaa9b24e55fc36de67bd16b716
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge changes from topic "gr/cov_fixes" into integration

* changes:
fix(libc): fix coverity overflowed constant
fix(libc): fix coverity overflowed constant
fix(psci): fix coverity issue with o

Merge changes from topic "gr/cov_fixes" into integration

* changes:
fix(libc): fix coverity overflowed constant
fix(libc): fix coverity overflowed constant
fix(psci): fix coverity issue with out-of-bounds read
fix(fvp): fix coverity issue unsigned_compare

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fix(qti): uart platform base address for SC7180

Following merge of [1] , SC7180 platform broke because of mismatched
UART base address. Restore to the proper value.

[1] https://review.trustedfirmwa

fix(qti): uart platform base address for SC7180

Following merge of [1] , SC7180 platform broke because of mismatched
UART base address. Restore to the proper value.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/43574/5/plat/qti/sc7180/inc/platform_def.h

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Change-Id: I4d34db01720ce289a87bccf0338205b4861e11cb

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feat(rdv3): enable numa aware per-cpu for RD-V3-Cfg2

RD-V3-Cfg2 being quad chip can make use of NUMA allocation within the
per-cpu framework. With NUMA allocation, the platform can distribute
per-cp

feat(rdv3): enable numa aware per-cpu for RD-V3-Cfg2

RD-V3-Cfg2 being quad chip can make use of NUMA allocation within the
per-cpu framework. With NUMA allocation, the platform can distribute
per-cpu objects within a memory that is local to a particular node.
RD-V3-Cfg2 in this case has the per-cpu objects distributed across
different SRAMs present on the system.

introduce platform-specific helper functions to enhance the per_cpu
framework. Adds a helper function to zero init per_cpu sections,
ensuring clean initialization of per-cpu data. Introduces a function
to obtain the base address of per_cpu sections, facilitating efficient
access to per-CPU data structures. Enhances the per_cpu framework's
capability to handle platform-specific requirements.

These additions are crucial for maintaining the integrity and
performance of per-cpu operations.

Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I550c6b5c59f80fbe2b746a1261cda857f4fb1990

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fix(versal2): align comment about invalid console selection

Error message should be aligned actual symbol used for console section
which has been changed by commit 2333ab4cd214 ("fix(versal2): renam

fix(versal2): align comment about invalid console selection

Error message should be aligned actual symbol used for console section
which has been changed by commit 2333ab4cd214 ("fix(versal2): rename
console build arg to generic").

Change-Id: I230892875a6343ca8ffc55e0fac251f6586cf3f4
Signed-off-by: Michal Simek <michal.simek@amd.com>

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fix(fvp): skip SP discovery through FFA_PARTITION_INFO_GET_REGS

The initialization function implemented for the dummy LSP of FVP port
invokes FFA_PARTITION_INFO_GET_REGS to obtain partition properti

fix(fvp): skip SP discovery through FFA_PARTITION_INFO_GET_REGS

The initialization function implemented for the dummy LSP of FVP port
invokes FFA_PARTITION_INFO_GET_REGS to obtain partition properties of
Secure Partitions managed by SPMC. This happens even before the normal
world is booted.

Hafnium SPMC mistakes this as a FF-A invocation from NWd. As per FF-A
version negotiation protocol, Hafnium locks the version of NWd to v1.3
whereas the NWd never got an opportunity to register its own framework
version.

This patch performs early exit from the helper utility to give NWd
endpoint/Hypervisor an opportunity to register its FF-A version with
SPM. We intentionally do not remove the helper utility as it will be
used in a different patchset for a new anticipated feature.

Change-Id: I54087bd2ad53355afeb024c0e4df6a5ba7ab125a
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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fix(fvp): fix coverity issue unsigned_compare

Fixes less than zero comparison for unsigned value.

Issue Description:
CID 447712: (#1 of 1): Macro compares unsigned to 0 (NO_EFFECT)
unsigned_compare

fix(fvp): fix coverity issue unsigned_compare

Fixes less than zero comparison for unsigned value.

Issue Description:
CID 447712: (#1 of 1): Macro compares unsigned to 0 (NO_EFFECT)
unsigned_compare: This less-than-zero comparison of an
unsigned value is never true. power_level < 0ULL.

Change-Id: Ia06f8729ac78b05046402e29e30f55c5f0b9e215
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "upstream_integrate_ddr_fw" into integration

* changes:
feat(s32g274ardb): add custom DDR FW UUID entry
fix(fiptool): skip Layerscape makefile for S32 build