1 2 /* 3 * Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved. 4 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 5 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 */ 9 10 #include <assert.h> 11 #include <common/debug.h> 12 #include <common/runtime_svc.h> 13 #include <drivers/delay_timer.h> 14 #include <lib/mmio.h> 15 #include <tools_share/uuid.h> 16 17 #include "lib/utils/alignment_utils.h" 18 #include "socfpga_fcs.h" 19 #include "socfpga_mailbox.h" 20 #include "socfpga_plat_def.h" 21 #include "socfpga_reset_manager.h" 22 #include "socfpga_sip_svc.h" 23 #include "socfpga_system_manager.h" 24 25 /* Total buffer the driver can hold */ 26 #define FPGA_CONFIG_BUFFER_SIZE 4 27 28 static config_type request_type = NO_REQUEST; 29 static int current_block, current_buffer; 30 static int read_block, max_blocks; 31 static uint32_t send_id, rcv_id; 32 static uint32_t bytes_per_block, blocks_submitted; 33 static bool bridge_disable; 34 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 35 static uint32_t g_remapper_bypass; 36 #endif 37 38 /* RSU static variables */ 39 static uint32_t rsu_dcmf_ver[4] = {0}; 40 static uint16_t rsu_dcmf_stat[4] = {0}; 41 static uint32_t rsu_max_retry; 42 43 /* SiP Service UUID */ 44 DEFINE_SVC_UUID2(intl_svc_uid, 45 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 46 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 47 48 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 49 uint64_t x1, 50 uint64_t x2, 51 uint64_t x3, 52 uint64_t x4, 53 void *cookie, 54 void *handle, 55 uint64_t flags) 56 { 57 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 58 SMC_RET1(handle, SMC_UNK); 59 } 60 61 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 62 63 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 64 { 65 uint32_t args[3]; 66 67 while (max_blocks > 0 && buffer->size > buffer->size_written) { 68 args[0] = (1<<8); 69 args[1] = buffer->addr + buffer->size_written; 70 if (buffer->size - buffer->size_written <= bytes_per_block) { 71 args[2] = buffer->size - buffer->size_written; 72 current_buffer++; 73 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 74 } else { 75 args[2] = bytes_per_block; 76 } 77 78 buffer->size_written += args[2]; 79 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 80 3U, CMD_INDIRECT); 81 82 buffer->subblocks_sent++; 83 max_blocks--; 84 } 85 86 return !max_blocks; 87 } 88 89 static int intel_fpga_sdm_write_all(void) 90 { 91 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 92 if (intel_fpga_sdm_write_buffer( 93 &fpga_config_buffers[current_buffer])) { 94 break; 95 } 96 } 97 return 0; 98 } 99 100 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t *err_states) 101 { 102 uint32_t ret; 103 104 if (err_states == NULL) 105 return INTEL_SIP_SMC_STATUS_REJECTED; 106 107 switch (request_type) { 108 case RECONFIGURATION: 109 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 110 true, err_states); 111 break; 112 case BITSTREAM_AUTH: 113 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 114 false, err_states); 115 break; 116 default: 117 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 118 false, err_states); 119 break; 120 } 121 122 if (ret != 0U) { 123 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 124 return INTEL_SIP_SMC_STATUS_BUSY; 125 } else { 126 request_type = NO_REQUEST; 127 return INTEL_SIP_SMC_STATUS_ERROR; 128 } 129 } 130 131 if (bridge_disable != 0U) { 132 socfpga_bridges_enable(~0); /* Enable bridge */ 133 bridge_disable = false; 134 } 135 request_type = NO_REQUEST; 136 137 return INTEL_SIP_SMC_STATUS_OK; 138 } 139 140 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 141 { 142 int i; 143 144 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 145 if (fpga_config_buffers[i].block_number == current_block) { 146 fpga_config_buffers[i].subblocks_sent--; 147 if (fpga_config_buffers[i].subblocks_sent == 0 148 && fpga_config_buffers[i].size <= 149 fpga_config_buffers[i].size_written) { 150 fpga_config_buffers[i].write_requested = 0; 151 current_block++; 152 *buffer_addr_completed = 153 fpga_config_buffers[i].addr; 154 return 0; 155 } 156 } 157 } 158 159 return -1; 160 } 161 162 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 163 uint32_t *count, uint32_t *job_id) 164 { 165 uint32_t resp[5]; 166 unsigned int resp_len = ARRAY_SIZE(resp); 167 int status = INTEL_SIP_SMC_STATUS_OK; 168 int all_completed = 1; 169 *count = 0; 170 171 while (*count < 3) { 172 173 status = mailbox_read_response(job_id, 174 resp, &resp_len); 175 176 if (status < 0) { 177 break; 178 } 179 180 max_blocks++; 181 182 if (mark_last_buffer_xfer_completed( 183 &completed_addr[*count]) == 0) { 184 *count = *count + 1; 185 } else { 186 break; 187 } 188 } 189 190 if (*count <= 0) { 191 if (status != MBOX_NO_RESPONSE && 192 status != MBOX_TIMEOUT && resp_len != 0) { 193 mailbox_clear_response(); 194 request_type = NO_REQUEST; 195 return INTEL_SIP_SMC_STATUS_ERROR; 196 } 197 198 *count = 0; 199 } 200 201 intel_fpga_sdm_write_all(); 202 203 if (*count > 0) { 204 status = INTEL_SIP_SMC_STATUS_OK; 205 } else if (*count == 0) { 206 status = INTEL_SIP_SMC_STATUS_BUSY; 207 } 208 209 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 210 if (fpga_config_buffers[i].write_requested != 0) { 211 all_completed = 0; 212 break; 213 } 214 } 215 216 if (all_completed == 1) { 217 return INTEL_SIP_SMC_STATUS_OK; 218 } 219 220 return status; 221 } 222 223 static int intel_fpga_config_start(uint32_t flag) 224 { 225 uint32_t argument = 0x1; 226 uint32_t response[3]; 227 int status = 0; 228 unsigned int size = 0; 229 unsigned int resp_len = ARRAY_SIZE(response); 230 231 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 232 /* 233 * To trigger isolation 234 * FPGA configuration complete signal should be de-asserted 235 */ 236 INFO("SOCFPGA: Request SDM to trigger isolation\n"); 237 status = mailbox_send_fpga_config_comp(); 238 239 if (status < 0) { 240 INFO("SOCFPGA: Isolation for FPGA configuration complete is not executed\n"); 241 } 242 #endif 243 244 request_type = RECONFIGURATION; 245 246 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 247 bridge_disable = true; 248 } 249 250 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 251 size = 1; 252 bridge_disable = false; 253 request_type = BITSTREAM_AUTH; 254 } 255 256 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 257 intel_smmu_hps_remapper_init(0U); 258 #endif 259 260 mailbox_clear_response(); 261 262 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 263 CMD_CASUAL, NULL, NULL); 264 265 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 266 CMD_CASUAL, response, &resp_len); 267 268 if (status < 0) { 269 bridge_disable = false; 270 request_type = NO_REQUEST; 271 return INTEL_SIP_SMC_STATUS_ERROR; 272 } 273 274 max_blocks = response[0]; 275 bytes_per_block = response[1]; 276 277 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 278 fpga_config_buffers[i].size = 0; 279 fpga_config_buffers[i].size_written = 0; 280 fpga_config_buffers[i].addr = 0; 281 fpga_config_buffers[i].write_requested = 0; 282 fpga_config_buffers[i].block_number = 0; 283 fpga_config_buffers[i].subblocks_sent = 0; 284 } 285 286 blocks_submitted = 0; 287 current_block = 0; 288 read_block = 0; 289 current_buffer = 0; 290 291 /* Disable bridge on full reconfiguration */ 292 if (bridge_disable) { 293 socfpga_bridges_disable(~0); 294 } 295 296 return INTEL_SIP_SMC_STATUS_OK; 297 } 298 299 static bool is_fpga_config_buffer_full(void) 300 { 301 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 302 if (!fpga_config_buffers[i].write_requested) { 303 return false; 304 } 305 } 306 return true; 307 } 308 309 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 310 { 311 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE; 312 uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size; 313 314 if (!addr && !size) { 315 return true; 316 } 317 if (size > (UINT64_MAX - addr)) { 318 return false; 319 } 320 if (addr < BL31_LIMIT) { 321 return false; 322 } 323 if (dram_region_end > dram_max_sz) { 324 return false; 325 } 326 327 return true; 328 } 329 330 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 331 { 332 int i; 333 334 intel_fpga_sdm_write_all(); 335 336 if (!is_address_in_ddr_range(mem, size) || 337 is_fpga_config_buffer_full()) { 338 return INTEL_SIP_SMC_STATUS_REJECTED; 339 } 340 341 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 342 intel_smmu_hps_remapper_init(&mem); 343 #endif 344 345 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 346 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 347 348 if (!fpga_config_buffers[j].write_requested) { 349 fpga_config_buffers[j].addr = mem; 350 fpga_config_buffers[j].size = size; 351 fpga_config_buffers[j].size_written = 0; 352 fpga_config_buffers[j].write_requested = 1; 353 fpga_config_buffers[j].block_number = 354 blocks_submitted++; 355 fpga_config_buffers[j].subblocks_sent = 0; 356 break; 357 } 358 } 359 360 if (is_fpga_config_buffer_full()) { 361 return INTEL_SIP_SMC_STATUS_BUSY; 362 } 363 364 return INTEL_SIP_SMC_STATUS_OK; 365 } 366 367 static int is_out_of_sec_range(uint64_t reg_addr) 368 { 369 #if DEBUG 370 return 0; 371 #endif 372 373 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 374 if (is_agilex5_A5F4() == true) { 375 switch (reg_addr) { 376 /* TSN stream control registers — only accessible on Agilex5 B0 */ 377 case SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN0): 378 case SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN1): 379 case SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN2): 380 return 0; 381 382 default: 383 break; 384 } 385 } 386 #endif 387 388 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 389 switch (reg_addr) { 390 case(0xF8011100): /* ECCCTRL1 */ 391 case(0xF8011104): /* ECCCTRL2 */ 392 case(0xF8011110): /* ERRINTEN */ 393 case(0xF8011114): /* ERRINTENS */ 394 case(0xF8011118): /* ERRINTENR */ 395 case(0xF801111C): /* INTMODE */ 396 case(0xF8011120): /* INTSTAT */ 397 case(0xF8011124): /* DIAGINTTEST */ 398 case(0xF801112C): /* DERRADDRA */ 399 case(0xFA000000): /* SMMU SCR0 */ 400 case(0xFA000004): /* SMMU SCR1 */ 401 case(0xFA000400): /* SMMU NSCR0 */ 402 case(0xFA004000): /* SMMU SSD0_REG */ 403 case(0xFA000820): /* SMMU SMR8 */ 404 case(0xFA000c20): /* SMMU SCR8 */ 405 case(0xFA028000): /* SMMU CB8_SCTRL */ 406 case(0xFA001020): /* SMMU CBAR8 */ 407 case(0xFA028030): /* SMMU TCR_LPAE */ 408 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 409 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 410 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 411 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 412 case(0xFA028010): /* SMMU_CB8)TCR2 */ 413 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 414 case(0xFA001820): /* SMMU_CBA2R8 */ 415 case(0xFA000074): /* SMMU_STLBGSTATUS */ 416 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 417 case(0xFA000060): /* SMMU_STLBIALL */ 418 case(0xFA000070): /* SMMU_STLBGSYNC */ 419 case(0xFA028618): /* CB8_TLBALL */ 420 case(0xFA0287F0): /* CB8_TLBSYNC */ 421 case(0xFFD12028): /* SDMMCGRP_CTRL */ 422 case(0xFFD12044): /* EMAC0 */ 423 case(0xFFD12048): /* EMAC1 */ 424 case(0xFFD1204C): /* EMAC2 */ 425 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 426 case(0xFFD12094): /* ECC_INT_MASK_SET */ 427 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 428 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 429 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 430 case(0xFFD120C0): /* NOC_TIMEOUT */ 431 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 432 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 433 case(0xFFD120D0): /* NOC_IDLEACK */ 434 case(0xFFD120D4): /* NOC_IDLESTATUS */ 435 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 436 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 437 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 438 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 439 return 0; 440 #else 441 switch (reg_addr) { 442 443 case(0xF8011104): /* ECCCTRL2 */ 444 case(0xFFD12028): /* SDMMCGRP_CTRL */ 445 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 446 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 447 case(0xFFD120D0): /* NOC_IDLEACK */ 448 449 450 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */ 451 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */ 452 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */ 453 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */ 454 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */ 455 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */ 456 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */ 457 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */ 458 459 case(SOCFPGA_ECC_QSPI(INITSTAT)): /* ECC_QSPI_INITSTAT */ 460 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */ 461 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */ 462 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */ 463 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */ 464 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */ 465 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */ 466 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */ 467 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */ 468 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */ 469 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */ 470 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */ 471 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */ 472 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */ 473 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */ 474 #endif 475 case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */ 476 case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */ 477 case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */ 478 case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */ 479 case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */ 480 case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */ 481 case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */ 482 case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */ 483 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 484 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 485 return 0; 486 487 default: 488 break; 489 } 490 491 return -1; 492 } 493 494 /* Secure register access */ 495 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 496 { 497 if (is_out_of_sec_range(reg_addr)) { 498 return INTEL_SIP_SMC_STATUS_ERROR; 499 } 500 501 *retval = mmio_read_32(reg_addr); 502 503 return INTEL_SIP_SMC_STATUS_OK; 504 } 505 506 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 507 uint32_t *retval) 508 { 509 if (is_out_of_sec_range(reg_addr)) { 510 return INTEL_SIP_SMC_STATUS_ERROR; 511 } 512 513 switch (reg_addr) { 514 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 515 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 516 mmio_write_16(reg_addr, val); 517 break; 518 default: 519 mmio_write_32(reg_addr, val); 520 break; 521 } 522 523 return intel_secure_reg_read(reg_addr, retval); 524 } 525 526 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 527 uint32_t val, uint32_t *retval) 528 { 529 if (!intel_secure_reg_read(reg_addr, retval)) { 530 *retval &= ~mask; 531 *retval |= val & mask; 532 return intel_secure_reg_write(reg_addr, *retval, retval); 533 } 534 535 return INTEL_SIP_SMC_STATUS_ERROR; 536 } 537 538 /* Intel Remote System Update (RSU) services */ 539 uint64_t intel_rsu_update_address; 540 541 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 542 { 543 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 544 return INTEL_SIP_SMC_RSU_ERROR; 545 } 546 547 return INTEL_SIP_SMC_STATUS_OK; 548 } 549 550 static uint32_t intel_rsu_get_device_info(uint32_t *respbuf, 551 unsigned int respbuf_sz) 552 { 553 if (mailbox_rsu_get_device_info((uint32_t *)respbuf, respbuf_sz) < 0) { 554 return INTEL_SIP_SMC_RSU_ERROR; 555 } 556 557 return INTEL_SIP_SMC_STATUS_OK; 558 } 559 560 uint32_t intel_rsu_update(uint64_t update_address) 561 { 562 if (update_address > SIZE_MAX) { 563 return INTEL_SIP_SMC_STATUS_REJECTED; 564 } 565 566 intel_rsu_update_address = update_address; 567 return INTEL_SIP_SMC_STATUS_OK; 568 } 569 570 static uint32_t intel_rsu_notify(uint32_t execution_stage) 571 { 572 if (mailbox_hps_stage_notify(execution_stage) < 0) { 573 return INTEL_SIP_SMC_RSU_ERROR; 574 } 575 576 return INTEL_SIP_SMC_STATUS_OK; 577 } 578 579 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 580 uint32_t *ret_stat) 581 { 582 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 583 return INTEL_SIP_SMC_RSU_ERROR; 584 } 585 586 *ret_stat = respbuf[8]; 587 return INTEL_SIP_SMC_STATUS_OK; 588 } 589 590 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 591 uint64_t dcmf_ver_3_2) 592 { 593 rsu_dcmf_ver[0] = dcmf_ver_1_0; 594 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 595 rsu_dcmf_ver[2] = dcmf_ver_3_2; 596 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 597 598 return INTEL_SIP_SMC_STATUS_OK; 599 } 600 601 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 602 { 603 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 604 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 605 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 606 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 607 608 return INTEL_SIP_SMC_STATUS_OK; 609 } 610 611 /* Intel HWMON services */ 612 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 613 { 614 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 615 return INTEL_SIP_SMC_STATUS_ERROR; 616 } 617 618 return INTEL_SIP_SMC_STATUS_OK; 619 } 620 621 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 622 { 623 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 624 return INTEL_SIP_SMC_STATUS_ERROR; 625 } 626 627 return INTEL_SIP_SMC_STATUS_OK; 628 } 629 630 /* Mailbox services */ 631 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 632 { 633 int status; 634 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 635 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 636 637 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 638 CMD_CASUAL, resp_data, &resp_len); 639 640 if (status < 0) { 641 return INTEL_SIP_SMC_STATUS_ERROR; 642 } 643 644 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 645 return INTEL_SIP_SMC_STATUS_ERROR; 646 } 647 648 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 649 650 return INTEL_SIP_SMC_STATUS_OK; 651 } 652 653 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 654 unsigned int len, uint32_t urgent, uint64_t response, 655 unsigned int resp_len, int *mbox_status, 656 unsigned int *len_in_resp) 657 { 658 *len_in_resp = 0; 659 *mbox_status = GENERIC_RESPONSE_ERROR; 660 661 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 662 return INTEL_SIP_SMC_STATUS_REJECTED; 663 } 664 665 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 666 (uint32_t *) response, &resp_len); 667 668 if (status < 0) { 669 *mbox_status = -status; 670 return INTEL_SIP_SMC_STATUS_ERROR; 671 } 672 673 *mbox_status = 0; 674 *len_in_resp = resp_len; 675 676 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 677 678 return INTEL_SIP_SMC_STATUS_OK; 679 } 680 681 static int intel_smc_get_usercode(uint32_t *user_code) 682 { 683 int status; 684 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 685 686 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 687 0U, CMD_CASUAL, user_code, &resp_len); 688 689 if (status < 0) { 690 return INTEL_SIP_SMC_STATUS_ERROR; 691 } 692 693 return INTEL_SIP_SMC_STATUS_OK; 694 } 695 696 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 697 uint32_t mode, uint32_t *job_id, 698 uint32_t *ret_size, uint32_t *mbox_error) 699 { 700 int status = 0; 701 uint32_t resp_len = size / MBOX_WORD_BYTE; 702 703 if (resp_len > MBOX_DATA_MAX_LEN) { 704 return INTEL_SIP_SMC_STATUS_REJECTED; 705 } 706 707 if (!is_address_in_ddr_range(addr, size)) { 708 return INTEL_SIP_SMC_STATUS_REJECTED; 709 } 710 711 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 712 status = mailbox_read_response_async(job_id, 713 NULL, (uint32_t *) addr, &resp_len, 0); 714 } else { 715 status = mailbox_read_response(job_id, 716 (uint32_t *) addr, &resp_len); 717 718 if (status == MBOX_NO_RESPONSE) { 719 status = MBOX_BUSY; 720 } 721 } 722 723 if (status == MBOX_NO_RESPONSE) { 724 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 725 } 726 727 if (status == MBOX_BUSY) { 728 return INTEL_SIP_SMC_STATUS_BUSY; 729 } 730 731 *ret_size = resp_len * MBOX_WORD_BYTE; 732 flush_dcache_range(addr, *ret_size); 733 734 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 735 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 736 *mbox_error = -status; 737 } else if (status != MBOX_RET_OK) { 738 *mbox_error = -status; 739 return INTEL_SIP_SMC_STATUS_ERROR; 740 } 741 742 return INTEL_SIP_SMC_STATUS_OK; 743 } 744 745 /* Miscellaneous HPS services */ 746 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 747 { 748 int status = 0; 749 750 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 751 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 752 status = socfpga_bridges_enable((uint32_t)mask); 753 } else { 754 status = socfpga_bridges_enable(~0); 755 } 756 } else { 757 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 758 status = socfpga_bridges_disable((uint32_t)mask); 759 } else { 760 status = socfpga_bridges_disable(~0); 761 } 762 } 763 764 if (status < 0) { 765 return INTEL_SIP_SMC_STATUS_ERROR; 766 } 767 768 return INTEL_SIP_SMC_STATUS_OK; 769 } 770 771 /* SDM SEU Error services */ 772 static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz) 773 { 774 if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) { 775 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 776 } 777 778 return INTEL_SIP_SMC_STATUS_OK; 779 } 780 781 /* SDM SAFE SEU Error inject services */ 782 static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len) 783 { 784 if (mailbox_safe_inject_seu_err(command, len) < 0) { 785 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 786 } 787 788 return INTEL_SIP_SMC_STATUS_OK; 789 } 790 791 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 792 /* SMMU HPS Remapper */ 793 void intel_smmu_hps_remapper_init(uint64_t *mem) 794 { 795 /* Read out Bit 1 value */ 796 uint32_t remap = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_1)) & 0x02); 797 798 if ((remap == 0x00) && (g_remapper_bypass == 0x00)) { 799 /* Update DRAM Base address for SDM SMMU */ 800 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE); 801 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE); 802 *mem = *mem - DRAM_BASE; 803 } else { 804 *mem = *mem - DRAM_BASE; 805 } 806 } 807 808 int intel_smmu_hps_remapper_config(uint32_t remapper_bypass) 809 { 810 /* Read out the JTAG-ID from boot scratch register */ 811 if (is_agilex5_A5C0() || is_agilex5_A5C4()) { 812 if (remapper_bypass == 0x01) { 813 g_remapper_bypass = remapper_bypass; 814 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), 0); 815 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), 0); 816 } 817 } 818 return INTEL_SIP_SMC_STATUS_OK; 819 } 820 821 static void intel_inject_io96b_ecc_err(const uint32_t *syndrome, const uint32_t command) 822 { 823 volatile uint64_t atf_ddr_buffer; 824 volatile uint64_t val; 825 826 mmio_write_32(IOSSM_CMD_PARAM, *syndrome); 827 mmio_write_32(IOSSM_CMD_TRIG_OP, command); 828 udelay(IOSSM_ECC_ERR_INJ_DELAY_USECS); 829 atf_ddr_buffer = 0xCAFEBABEFEEDFACE; /* Write data */ 830 memcpy_s((void *)&val, sizeof(val), 831 (void *)&atf_ddr_buffer, sizeof(atf_ddr_buffer)); 832 833 /* Clear response_ready BIT0 of status_register before sending next command. */ 834 mmio_clrbits_32(IOSSM_CMD_RESP_STATUS, IOSSM_CMD_STATUS_RESP_READY); 835 } 836 #endif 837 838 #if SIP_SVC_V3 839 uint8_t sip_smc_cmd_cb_ret2(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 840 { 841 uint8_t ret_args_len = 0U; 842 sdm_response_t *resp = (sdm_response_t *)resp_desc; 843 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 844 845 (void)cmd; 846 /* Returns 3 SMC arguments for SMC_RET3 */ 847 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 848 ret_args[ret_args_len++] = resp->err_code; 849 850 return ret_args_len; 851 } 852 853 uint8_t sip_smc_cmd_cb_ret3(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 854 { 855 uint8_t ret_args_len = 0U; 856 sdm_response_t *resp = (sdm_response_t *)resp_desc; 857 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 858 859 (void)cmd; 860 /* Returns 3 SMC arguments for SMC_RET3 */ 861 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 862 ret_args[ret_args_len++] = resp->err_code; 863 ret_args[ret_args_len++] = resp->resp_data[0]; 864 865 return ret_args_len; 866 } 867 868 uint8_t sip_smc_ret_nbytes_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 869 { 870 uint8_t ret_args_len = 0U; 871 sdm_response_t *resp = (sdm_response_t *)resp_desc; 872 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 873 874 INFO("MBOX: %s: mailbox_err 0%x, nbytes_ret %d\n", 875 __func__, resp->err_code, resp->rcvd_resp_len * MBOX_WORD_BYTE); 876 877 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 878 ret_args[ret_args_len++] = resp->err_code; 879 ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE; 880 881 /* Flush the response data buffer. */ 882 flush_dcache_range((uintptr_t)cmd->cb_args, resp->rcvd_resp_len * MBOX_WORD_BYTE); 883 884 return ret_args_len; 885 } 886 887 uint8_t sip_smc_get_chipid_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 888 { 889 uint8_t ret_args_len = 0U; 890 sdm_response_t *resp = (sdm_response_t *)resp_desc; 891 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 892 893 (void)cmd; 894 INFO("MBOX: %s: mailbox_err 0%x, data[0] 0x%x, data[1] 0x%x\n", 895 __func__, resp->err_code, resp->resp_data[0], resp->resp_data[1]); 896 897 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 898 ret_args[ret_args_len++] = resp->err_code; 899 ret_args[ret_args_len++] = resp->resp_data[0]; 900 ret_args[ret_args_len++] = resp->resp_data[1]; 901 902 return ret_args_len; 903 } 904 905 uint8_t sip_smc_cmd_cb_rsu_status(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 906 { 907 uint8_t ret_args_len = 0U; 908 uint32_t retry_counter = ~0U; 909 uint32_t failure_source = 0U; 910 sdm_response_t *resp = (sdm_response_t *)resp_desc; 911 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 912 913 (void)cmd; 914 /* Get the failure source and current image retry counter value from the response. */ 915 failure_source = resp->resp_data[5] & RSU_VERSION_ACMF_MASK; 916 retry_counter = resp->resp_data[8]; 917 918 if ((retry_counter != ~0U) && (failure_source == 0U)) 919 resp->resp_data[5] |= RSU_VERSION_ACMF; 920 921 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 922 ret_args[ret_args_len++] = resp->err_code; 923 /* Current CMF */ 924 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[1], resp->resp_data[0]); 925 /* Last Failing CMF Address */ 926 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[3], resp->resp_data[2]); 927 /* Config State */ 928 ret_args[ret_args_len++] = resp->resp_data[4]; 929 /* Version */ 930 ret_args[ret_args_len++] = resp->resp_data[5]; 931 /* Failure Source */ 932 ret_args[ret_args_len++] = ((GENMASK(32, 17) & resp->resp_data[5]) >> 16); 933 /* Error location */ 934 ret_args[ret_args_len++] = resp->resp_data[6]; 935 /* Error details */ 936 ret_args[ret_args_len++] = resp->resp_data[7]; 937 /* Current image retry counter */ 938 ret_args[ret_args_len++] = resp->resp_data[8]; 939 940 return ret_args_len; 941 } 942 943 uint8_t sip_smc_cmd_cb_rsu_spt(void *resp_desc, void *cmd_desc, uint64_t *ret_args) 944 { 945 uint8_t ret_args_len = 0U; 946 sdm_response_t *resp = (sdm_response_t *)resp_desc; 947 sdm_command_t *cmd = (sdm_command_t *)cmd_desc; 948 949 (void)cmd; 950 951 ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK; 952 ret_args[ret_args_len++] = resp->err_code; 953 /* Sub Partition Table (SPT) 0 address */ 954 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[0], resp->resp_data[1]); 955 /* Sub Partition Table (SPT) 1 address */ 956 ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[2], resp->resp_data[3]); 957 958 return ret_args_len; 959 } 960 961 static uintptr_t smc_ret(void *handle, uint64_t *ret_args, uint32_t ret_args_len) 962 { 963 964 switch (ret_args_len) { 965 case SMC_RET_ARGS_ONE: 966 VERBOSE("SVC V3: %s: x0 0x%lx\n", __func__, ret_args[0]); 967 SMC_RET1(handle, ret_args[0]); 968 break; 969 970 case SMC_RET_ARGS_TWO: 971 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx\n", __func__, ret_args[0], ret_args[1]); 972 SMC_RET2(handle, ret_args[0], ret_args[1]); 973 break; 974 975 case SMC_RET_ARGS_THREE: 976 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx\n", 977 __func__, ret_args[0], ret_args[1], ret_args[2]); 978 SMC_RET3(handle, ret_args[0], ret_args[1], ret_args[2]); 979 break; 980 981 case SMC_RET_ARGS_FOUR: 982 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx\n", 983 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3]); 984 SMC_RET4(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3]); 985 break; 986 987 case SMC_RET_ARGS_FIVE: 988 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx\n", 989 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]); 990 SMC_RET5(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]); 991 break; 992 993 case SMC_RET_ARGS_SIX: 994 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx x3 0x%lx, x4 0x%lx x5 0x%lx\n", 995 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 996 ret_args[5]); 997 SMC_RET6(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 998 ret_args[5]); 999 break; 1000 1001 case SMC_RET_ARGS_SEVEN: 1002 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t" 1003 "x6 0x%lx\n", 1004 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1005 ret_args[5], ret_args[6]); 1006 SMC_RET7(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1007 ret_args[5], ret_args[6]); 1008 break; 1009 1010 case SMC_RET_ARGS_EIGHT: 1011 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t" 1012 "x6 0x%lx, x7 0x%lx\n", 1013 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1014 ret_args[5], ret_args[6], ret_args[7]); 1015 SMC_RET8(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1016 ret_args[5], ret_args[6], ret_args[7]); 1017 break; 1018 1019 case SMC_RET_ARGS_NINE: 1020 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t" 1021 "x6 0x%lx, x7 0x%lx, x8 0x%lx\n", 1022 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1023 ret_args[5], ret_args[6], ret_args[7], ret_args[8]); 1024 SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1025 ret_args[5], ret_args[6], ret_args[7], ret_args[8], 1026 0, 0, 0, 0, 0, 0, 0, 0, 0); 1027 break; 1028 1029 case SMC_RET_ARGS_TEN: 1030 VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t" 1031 "x6 0x%lx, x7 0x%lx x8 0x%lx, x9 0x%lx, x10 0x%lx\n", 1032 __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], 1033 ret_args[4], ret_args[5], ret_args[6], ret_args[7], ret_args[8], 1034 ret_args[9], ret_args[10]); 1035 SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4], 1036 ret_args[5], ret_args[6], ret_args[7], ret_args[8], ret_args[9], 1037 0, 0, 0, 0, 0, 0, 0, 0); 1038 break; 1039 1040 default: 1041 VERBOSE("SVC V3: %s ret_args_len is wrong, please check %d\n ", 1042 __func__, ret_args_len); 1043 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 1044 break; 1045 } 1046 } 1047 1048 static inline bool is_gen_mbox_cmd_allowed(uint32_t cmd) 1049 { 1050 /* Check if the command is allowed to be executed in generic mbox format */ 1051 bool is_cmd_allowed = false; 1052 1053 switch (cmd) { 1054 case MBOX_FCS_OPEN_CS_SESSION: 1055 case MBOX_FCS_CLOSE_CS_SESSION: 1056 case MBOX_FCS_IMPORT_CS_KEY: 1057 case MBOX_FCS_EXPORT_CS_KEY: 1058 case MBOX_FCS_REMOVE_CS_KEY: 1059 case MBOX_FCS_GET_CS_KEY_INFO: 1060 case MBOX_FCS_CREATE_CS_KEY: 1061 case MBOX_FCS_GET_DIGEST_REQ: 1062 case MBOX_FCS_MAC_VERIFY_REQ: 1063 case MBOX_FCS_ECDSA_HASH_SIGN_REQ: 1064 case MBOX_FCS_GET_PROVISION: 1065 case MBOX_FCS_CNTR_SET_PREAUTH: 1066 case MBOX_FCS_ENCRYPT_REQ: 1067 case MBOX_FCS_DECRYPT_REQ: 1068 case MBOX_FCS_RANDOM_GEN: 1069 case MBOX_FCS_AES_CRYPT_REQ: 1070 case MBOX_FCS_ECDSA_SHA2_DATA_SIGN_REQ: 1071 case MBOX_FCS_ECDSA_HASH_SIG_VERIFY: 1072 case MBOX_FCS_ECDSA_SHA2_DATA_SIGN_VERIFY: 1073 case MBOX_FCS_ECDSA_GET_PUBKEY: 1074 case MBOX_FCS_ECDH_REQUEST: 1075 case MBOX_FCS_HKDF_REQUEST: 1076 /* These mailbox commands are not supported in the generic mailbox format. */ 1077 break; 1078 1079 default: 1080 is_cmd_allowed = true; 1081 break; 1082 } /* switch */ 1083 1084 return is_cmd_allowed; 1085 } 1086 1087 /* 1088 * This function is responsible for handling all SiP SVC V3 calls from the 1089 * non-secure world. 1090 */ 1091 static uintptr_t sip_smc_handler_v3(uint32_t smc_fid, 1092 u_register_t x1, 1093 u_register_t x2, 1094 u_register_t x3, 1095 u_register_t x4, 1096 void *cookie, 1097 void *handle, 1098 u_register_t flags) 1099 { 1100 int status = 0; 1101 uint32_t mbox_error = 0U; 1102 u_register_t x5, x6, x7, x8, x9, x10, x11; 1103 1104 /* Get all the SMC call arguments */ 1105 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1106 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1107 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1108 x8 = SMC_GET_GP(handle, CTX_GPREG_X8); 1109 x9 = SMC_GET_GP(handle, CTX_GPREG_X9); 1110 x10 = SMC_GET_GP(handle, CTX_GPREG_X10); 1111 x11 = SMC_GET_GP(handle, CTX_GPREG_X11); 1112 1113 INFO("MBOX: SVC_V3: x0 0x%x, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\n", 1114 smc_fid, x1, x2, x3, x4, x5); 1115 INFO("MBOX: SVC_V3: x6 0x%lx, x7 0x%lx, x8 0x%lx, x9 0x%lx, x10 0x%lx x11 0x%lx\n", 1116 x6, x7, x8, x9, x10, x11); 1117 1118 switch (smc_fid) { 1119 case ALTERA_SIP_SMC_ASYNC_RESP_POLL: 1120 { 1121 uint64_t ret_args[16] = {0}; 1122 uint32_t ret_args_len = 0; 1123 1124 status = mailbox_response_poll_v3(GET_CLIENT_ID(x1), 1125 GET_JOB_ID(x1), 1126 ret_args, 1127 &ret_args_len); 1128 /* Always reserve [0] index for command status. */ 1129 ret_args[0] = status; 1130 1131 /* Return SMC call based on the number of return arguments */ 1132 return smc_ret(handle, ret_args, ret_args_len); 1133 } 1134 1135 case ALTERA_SIP_SMC_ASYNC_RESP_POLL_ON_INTR: 1136 { 1137 /* TBD: Here now we don't need these CID and JID?? */ 1138 uint8_t client_id = 0U; 1139 uint8_t job_id = 0U; 1140 uint64_t trans_id_bitmap[4] = {0U}; 1141 1142 status = mailbox_response_poll_on_intr_v3(&client_id, 1143 &job_id, 1144 trans_id_bitmap); 1145 1146 SMC_RET5(handle, status, trans_id_bitmap[0], trans_id_bitmap[1], 1147 trans_id_bitmap[2], trans_id_bitmap[3]); 1148 break; 1149 } 1150 1151 case ALTERA_SIP_SMC_ASYNC_GET_DEVICE_IDENTITY: 1152 { 1153 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1154 GET_JOB_ID(x1), 1155 MBOX_CMD_GET_DEVICEID, 1156 NULL, 1157 0U, 1158 MBOX_CMD_FLAG_CASUAL, 1159 sip_smc_ret_nbytes_cb, 1160 (uint32_t *)x2, 1161 2); 1162 1163 SMC_RET1(handle, status); 1164 } 1165 1166 case ALTERA_SIP_SMC_ASYNC_GET_IDCODE: 1167 { 1168 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1169 GET_JOB_ID(x1), 1170 MBOX_CMD_GET_IDCODE, 1171 NULL, 1172 0U, 1173 MBOX_CMD_FLAG_CASUAL, 1174 sip_smc_cmd_cb_ret3, 1175 NULL, 1176 0); 1177 1178 SMC_RET1(handle, status); 1179 } 1180 1181 case ALTERA_SIP_SMC_ASYNC_QSPI_OPEN: 1182 { 1183 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1184 GET_JOB_ID(x1), 1185 MBOX_CMD_QSPI_OPEN, 1186 NULL, 1187 0U, 1188 MBOX_CMD_FLAG_CASUAL, 1189 sip_smc_cmd_cb_ret2, 1190 NULL, 1191 0U); 1192 1193 SMC_RET1(handle, status); 1194 } 1195 1196 case ALTERA_SIP_SMC_ASYNC_QSPI_CLOSE: 1197 { 1198 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1199 GET_JOB_ID(x1), 1200 MBOX_CMD_QSPI_CLOSE, 1201 NULL, 1202 0U, 1203 MBOX_CMD_FLAG_CASUAL, 1204 sip_smc_cmd_cb_ret2, 1205 NULL, 1206 0U); 1207 1208 SMC_RET1(handle, status); 1209 } 1210 1211 case ALTERA_SIP_SMC_ASYNC_QSPI_SET_CS: 1212 { 1213 uint32_t cmd_data = 0U; 1214 uint32_t chip_sel = (uint32_t)x2; 1215 uint32_t comb_addr_mode = (uint32_t)x3; 1216 uint32_t ext_dec_mode = (uint32_t)x4; 1217 1218 cmd_data = (chip_sel << MBOX_QSPI_SET_CS_OFFSET) | 1219 (comb_addr_mode << MBOX_QSPI_SET_CS_CA_OFFSET) | 1220 (ext_dec_mode << MBOX_QSPI_SET_CS_MODE_OFFSET); 1221 1222 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1223 GET_JOB_ID(x1), 1224 MBOX_CMD_QSPI_SET_CS, 1225 &cmd_data, 1226 1U, 1227 MBOX_CMD_FLAG_CASUAL, 1228 sip_smc_cmd_cb_ret2, 1229 NULL, 1230 0U); 1231 1232 SMC_RET1(handle, status); 1233 } 1234 1235 case ALTERA_SIP_SMC_ASYNC_QSPI_ERASE: 1236 { 1237 uint32_t qspi_addr = (uint32_t)x2; 1238 uint32_t qspi_nwords = (uint32_t)x3; 1239 1240 /* QSPI address offset to start erase, must be 4K aligned */ 1241 if (MBOX_IS_4K_ALIGNED(qspi_addr)) { 1242 ERROR("MBOX: 0x%x: QSPI address not 4K aligned\n", 1243 smc_fid); 1244 status = INTEL_SIP_SMC_STATUS_REJECTED; 1245 SMC_RET1(handle, status); 1246 } 1247 1248 /* Number of words to erase, multiples of 0x400 or 4K */ 1249 if (qspi_nwords % MBOX_QSPI_ERASE_SIZE_GRAN) { 1250 ERROR("MBOX: 0x%x: Given words not in multiples of 4K\n", 1251 smc_fid); 1252 status = INTEL_SIP_SMC_STATUS_REJECTED; 1253 SMC_RET1(handle, status); 1254 } 1255 1256 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords}; 1257 1258 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1259 GET_JOB_ID(x1), 1260 MBOX_CMD_QSPI_ERASE, 1261 cmd_data, 1262 sizeof(cmd_data) / MBOX_WORD_BYTE, 1263 MBOX_CMD_FLAG_CASUAL, 1264 sip_smc_cmd_cb_ret2, 1265 NULL, 1266 0U); 1267 1268 SMC_RET1(handle, status); 1269 } 1270 1271 case ALTERA_SIP_SMC_ASYNC_QSPI_WRITE: 1272 { 1273 uint32_t *qspi_payload = (uint32_t *)x2; 1274 uint32_t qspi_total_nwords = (((uint32_t)x3) / MBOX_WORD_BYTE); 1275 uint32_t qspi_addr = qspi_payload[0]; 1276 uint32_t qspi_nwords = qspi_payload[1]; 1277 1278 if (!MBOX_IS_WORD_ALIGNED(qspi_addr)) { 1279 ERROR("MBOX: 0x%x: Given address is not WORD aligned\n", 1280 smc_fid); 1281 status = INTEL_SIP_SMC_STATUS_REJECTED; 1282 SMC_RET1(handle, status); 1283 } 1284 1285 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) { 1286 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n", 1287 smc_fid); 1288 status = INTEL_SIP_SMC_STATUS_REJECTED; 1289 SMC_RET1(handle, status); 1290 } 1291 1292 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1293 GET_JOB_ID(x1), 1294 MBOX_CMD_QSPI_WRITE, 1295 qspi_payload, 1296 qspi_total_nwords, 1297 MBOX_CMD_FLAG_CASUAL, 1298 sip_smc_cmd_cb_ret2, 1299 NULL, 1300 0U); 1301 1302 SMC_RET1(handle, status); 1303 } 1304 1305 case ALTERA_SIP_SMC_ASYNC_QSPI_READ: 1306 { 1307 uint32_t qspi_addr = (uint32_t)x2; 1308 uint32_t qspi_nwords = (((uint32_t)x4) / MBOX_WORD_BYTE); 1309 1310 if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) { 1311 ERROR("MBOX: 0x%x: Number of words exceeds max limit\n", 1312 smc_fid); 1313 status = INTEL_SIP_SMC_STATUS_REJECTED; 1314 SMC_RET1(handle, status); 1315 } 1316 1317 uint32_t cmd_data[2] = {qspi_addr, qspi_nwords}; 1318 1319 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1320 GET_JOB_ID(x1), 1321 MBOX_CMD_QSPI_READ, 1322 cmd_data, 1323 sizeof(cmd_data) / MBOX_WORD_BYTE, 1324 MBOX_CMD_FLAG_CASUAL, 1325 sip_smc_ret_nbytes_cb, 1326 (uint32_t *)x3, 1327 2); 1328 1329 SMC_RET1(handle, status); 1330 } 1331 1332 case ALTERA_SIP_SMC_ASYNC_QSPI_GET_DEV_INFO: 1333 { 1334 uint32_t *dst_addr = (uint32_t *)x2; 1335 1336 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1337 GET_JOB_ID(x1), 1338 MBOX_CMD_QSPI_GET_DEV_INFO, 1339 NULL, 1340 0U, 1341 MBOX_CMD_FLAG_CASUAL, 1342 sip_smc_ret_nbytes_cb, 1343 (uint32_t *)dst_addr, 1344 2); 1345 1346 SMC_RET1(handle, status); 1347 } 1348 1349 case ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT: 1350 case ALTERA_SIP_SMC_ASYNC_HWMON_READTEMP: 1351 { 1352 uint32_t channel = (uint32_t)x2; 1353 uint32_t mbox_cmd = ((smc_fid == ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT) ? 1354 MBOX_HWMON_READVOLT : MBOX_HWMON_READTEMP); 1355 1356 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1357 GET_JOB_ID(x1), 1358 mbox_cmd, 1359 &channel, 1360 1U, 1361 MBOX_CMD_FLAG_CASUAL, 1362 sip_smc_cmd_cb_ret3, 1363 NULL, 1364 0); 1365 1366 SMC_RET1(handle, status); 1367 } 1368 1369 case ALTERA_SIP_SMC_ASYNC_RSU_GET_SPT: 1370 { 1371 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1372 GET_JOB_ID(x1), 1373 MBOX_GET_SUBPARTITION_TABLE, 1374 NULL, 1375 0, 1376 MBOX_CMD_FLAG_CASUAL, 1377 sip_smc_cmd_cb_rsu_spt, 1378 NULL, 1379 0); 1380 1381 SMC_RET1(handle, status); 1382 } 1383 1384 case ALTERA_SIP_SMC_ASYNC_RSU_GET_STATUS: 1385 { 1386 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1387 GET_JOB_ID(x1), 1388 MBOX_RSU_STATUS, 1389 NULL, 1390 0, 1391 MBOX_CMD_FLAG_CASUAL, 1392 sip_smc_cmd_cb_rsu_status, 1393 NULL, 1394 0); 1395 1396 SMC_RET1(handle, status); 1397 } 1398 1399 case ALTERA_SIP_SMC_ASYNC_RSU_NOTIFY: 1400 { 1401 uint32_t notify_code = (uint32_t)x2; 1402 1403 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1404 GET_JOB_ID(x1), 1405 MBOX_HPS_STAGE_NOTIFY, 1406 ¬ify_code, 1407 1U, 1408 MBOX_CMD_FLAG_CASUAL, 1409 sip_smc_cmd_cb_ret2, 1410 NULL, 1411 0); 1412 1413 SMC_RET1(handle, status); 1414 } 1415 1416 case ALTERA_SIP_SMC_ASYNC_GEN_MBOX_CMD: 1417 { 1418 /* Collect all the args passed in, and send the mailbox command. */ 1419 uint32_t mbox_cmd = (uint32_t)x2; 1420 uint32_t *cmd_payload_addr = NULL; 1421 uint32_t cmd_payload_len = (uint32_t)x4 / MBOX_WORD_BYTE; 1422 uint32_t *resp_payload_addr = NULL; 1423 uint32_t resp_payload_len = (uint32_t)x6 / MBOX_WORD_BYTE; 1424 1425 /* Filter the required commands here. */ 1426 if (!is_gen_mbox_cmd_allowed(mbox_cmd)) { 1427 status = INTEL_SIP_SMC_STATUS_REJECTED; 1428 SMC_RET1(handle, status); 1429 } 1430 1431 if ((cmd_payload_len > MBOX_GEN_CMD_MAX_WORDS) || 1432 (resp_payload_len > MBOX_GEN_CMD_MAX_WORDS)) { 1433 ERROR("MBOX: 0x%x: Command/Response payload length exceeds max limit\n", 1434 smc_fid); 1435 status = INTEL_SIP_SMC_STATUS_REJECTED; 1436 SMC_RET1(handle, status); 1437 } 1438 1439 /* Make sure we have valid command payload length and buffer */ 1440 if (cmd_payload_len != 0U) { 1441 cmd_payload_addr = (uint32_t *)x3; 1442 if (cmd_payload_addr == NULL) { 1443 ERROR("MBOX: 0x%x: Command payload address is NULL\n", 1444 smc_fid); 1445 status = INTEL_SIP_SMC_STATUS_REJECTED; 1446 SMC_RET1(handle, status); 1447 } 1448 } 1449 1450 /* Make sure we have valid response payload length and buffer */ 1451 if (resp_payload_len != 0U) { 1452 resp_payload_addr = (uint32_t *)x5; 1453 if (resp_payload_addr == NULL) { 1454 ERROR("MBOX: 0x%x: Response payload address is NULL\n", 1455 smc_fid); 1456 status = INTEL_SIP_SMC_STATUS_REJECTED; 1457 SMC_RET1(handle, status); 1458 } 1459 } 1460 1461 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1462 GET_JOB_ID(x1), 1463 mbox_cmd, 1464 (uint32_t *)cmd_payload_addr, 1465 cmd_payload_len, 1466 MBOX_CMD_FLAG_CASUAL, 1467 sip_smc_ret_nbytes_cb, 1468 (uint32_t *)resp_payload_addr, 1469 resp_payload_len); 1470 1471 SMC_RET1(handle, status); 1472 } 1473 1474 case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT: 1475 { 1476 uint32_t session_id = (uint32_t)x2; 1477 uint32_t context_id = (uint32_t)x3; 1478 uint64_t ret_random_addr = (uint64_t)x4; 1479 uint32_t random_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1480 uint32_t crypto_header = 0U; 1481 1482 if ((random_len > (FCS_RANDOM_EXT_MAX_WORD_SIZE * MBOX_WORD_BYTE)) || 1483 (random_len == 0U) || 1484 (!is_size_4_bytes_aligned(random_len))) { 1485 ERROR("MBOX: 0x%x is rejected\n", smc_fid); 1486 status = INTEL_SIP_SMC_STATUS_REJECTED; 1487 SMC_RET1(handle, status); 1488 } 1489 1490 crypto_header = ((FCS_CS_FIELD_FLAG_INIT | FCS_CS_FIELD_FLAG_FINALIZE) << 1491 FCS_CS_FIELD_FLAG_OFFSET); 1492 fcs_rng_payload payload = {session_id, context_id, 1493 crypto_header, random_len}; 1494 1495 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1496 GET_JOB_ID(x1), 1497 MBOX_FCS_RANDOM_GEN, 1498 (uint32_t *)&payload, 1499 sizeof(payload) / MBOX_WORD_BYTE, 1500 MBOX_CMD_FLAG_CASUAL, 1501 sip_smc_ret_nbytes_cb, 1502 (uint32_t *)ret_random_addr, 1503 2); 1504 SMC_RET1(handle, status); 1505 } 1506 1507 case ALTERA_SIP_SMC_ASYNC_FCS_GET_PROVISION_DATA: 1508 { 1509 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1510 GET_JOB_ID(x1), 1511 MBOX_FCS_GET_PROVISION, 1512 NULL, 1513 0U, 1514 MBOX_CMD_FLAG_CASUAL, 1515 sip_smc_ret_nbytes_cb, 1516 (uint32_t *)x2, 1517 2); 1518 SMC_RET1(handle, status); 1519 } 1520 1521 case ALTERA_SIP_SMC_ASYNC_FCS_CNTR_SET_PREAUTH: 1522 { 1523 status = intel_fcs_cntr_set_preauth(smc_fid, x1, x2, x3, 1524 x4, &mbox_error); 1525 SMC_RET1(handle, status); 1526 } 1527 1528 case ALTERA_SIP_SMC_ASYNC_FCS_CHIP_ID: 1529 { 1530 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1531 GET_JOB_ID(x1), 1532 MBOX_CMD_GET_CHIPID, 1533 NULL, 1534 0U, 1535 MBOX_CMD_FLAG_CASUAL, 1536 sip_smc_get_chipid_cb, 1537 NULL, 1538 0); 1539 SMC_RET1(handle, status); 1540 } 1541 1542 case ALTERA_SIP_SMC_ASYNC_FCS_GET_ATTESTATION_CERT: 1543 { 1544 status = intel_fcs_get_attestation_cert(smc_fid, x1, x2, x3, 1545 (uint32_t *) &x4, &mbox_error); 1546 SMC_RET1(handle, status); 1547 } 1548 1549 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CERT_ON_RELOAD: 1550 { 1551 status = intel_fcs_create_cert_on_reload(smc_fid, x1, 1552 x2, &mbox_error); 1553 SMC_RET1(handle, status); 1554 } 1555 1556 case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT: 1557 { 1558 if (x4 == FCS_MODE_ENCRYPT) { 1559 status = intel_fcs_encryption_ext(smc_fid, x1, x2, x3, 1560 x5, x6, x7, (uint32_t *) &x8, 1561 &mbox_error, x10, x11); 1562 } else if (x4 == FCS_MODE_DECRYPT) { 1563 status = intel_fcs_decryption_ext(smc_fid, x1, x2, x3, 1564 x5, x6, x7, (uint32_t *) &x8, 1565 &mbox_error, x9, x10, x11); 1566 } else { 1567 ERROR("MBOX: 0x%x: Wrong crypto mode\n", smc_fid); 1568 status = INTEL_SIP_SMC_STATUS_REJECTED; 1569 } 1570 SMC_RET1(handle, status); 1571 } 1572 1573 case ALTERA_SIP_SMC_ASYNC_FCS_SEND_CERTIFICATE: 1574 { 1575 status = intel_fcs_send_cert(smc_fid, x1, x2, x3, &mbox_error); 1576 SMC_RET1(handle, status); 1577 } 1578 1579 case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION: 1580 { 1581 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1582 GET_JOB_ID(x1), 1583 MBOX_FCS_OPEN_CS_SESSION, 1584 NULL, 1585 0U, 1586 MBOX_CMD_FLAG_CASUAL, 1587 sip_smc_cmd_cb_ret3, 1588 NULL, 1589 0); 1590 SMC_RET1(handle, status); 1591 } 1592 1593 case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION: 1594 { 1595 uint32_t session_id = (uint32_t)x2; 1596 1597 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1598 GET_JOB_ID(x1), 1599 MBOX_FCS_CLOSE_CS_SESSION, 1600 &session_id, 1601 1U, 1602 MBOX_CMD_FLAG_CASUAL, 1603 sip_smc_cmd_cb_ret2, 1604 NULL, 1605 0); 1606 SMC_RET1(handle, status); 1607 } 1608 1609 case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY: 1610 { 1611 uint64_t key_addr = x2; 1612 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE; 1613 1614 if ((key_len_words > FCS_CS_KEY_OBJ_MAX_WORD_SIZE) || 1615 (!is_address_in_ddr_range(key_addr, key_len_words * 4))) { 1616 ERROR("MBOX: 0x%x: Addr not in DDR range or key len exceeds\n", 1617 smc_fid); 1618 status = INTEL_SIP_SMC_STATUS_REJECTED; 1619 SMC_RET1(handle, status); 1620 } 1621 1622 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1623 GET_JOB_ID(x1), 1624 MBOX_FCS_IMPORT_CS_KEY, 1625 (uint32_t *)key_addr, 1626 key_len_words, 1627 MBOX_CMD_FLAG_CASUAL, 1628 sip_smc_cmd_cb_ret3, 1629 NULL, 1630 0); 1631 SMC_RET1(handle, status); 1632 } 1633 1634 case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY: 1635 { 1636 uint64_t key_addr = x2; 1637 uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE; 1638 1639 if (!is_address_in_ddr_range(key_addr, key_len_words * 4)) { 1640 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1641 status = INTEL_SIP_SMC_STATUS_REJECTED; 1642 SMC_RET1(handle, status); 1643 } 1644 1645 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1646 GET_JOB_ID(x1), 1647 MBOX_FCS_CREATE_CS_KEY, 1648 (uint32_t *)key_addr, 1649 key_len_words, 1650 MBOX_CMD_FLAG_CASUAL, 1651 sip_smc_cmd_cb_ret3, 1652 NULL, 1653 0); 1654 SMC_RET1(handle, status); 1655 } 1656 1657 case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY: 1658 { 1659 uint32_t session_id = (uint32_t)x2; 1660 uint32_t key_uid = (uint32_t)x3; 1661 uint64_t ret_key_addr = (uint64_t)x4; 1662 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1663 1664 if (!is_address_in_ddr_range(ret_key_addr, key_len)) { 1665 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1666 status = INTEL_SIP_SMC_STATUS_REJECTED; 1667 SMC_RET1(handle, status); 1668 } 1669 1670 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1671 RESERVED_AS_ZERO, key_uid}; 1672 1673 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1674 GET_JOB_ID(x1), 1675 MBOX_FCS_EXPORT_CS_KEY, 1676 (uint32_t *)&payload, 1677 sizeof(payload) / MBOX_WORD_BYTE, 1678 MBOX_CMD_FLAG_CASUAL, 1679 sip_smc_ret_nbytes_cb, 1680 (uint32_t *)ret_key_addr, 1681 2); 1682 SMC_RET1(handle, status); 1683 } 1684 1685 case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY: 1686 { 1687 uint32_t session_id = (uint32_t)x2; 1688 uint32_t key_uid = (uint32_t)x3; 1689 1690 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1691 RESERVED_AS_ZERO, key_uid}; 1692 1693 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1694 GET_JOB_ID(x1), 1695 MBOX_FCS_REMOVE_CS_KEY, 1696 (uint32_t *)&payload, 1697 sizeof(payload) / MBOX_WORD_BYTE, 1698 MBOX_CMD_FLAG_CASUAL, 1699 sip_smc_cmd_cb_ret3, 1700 NULL, 1701 0); 1702 SMC_RET1(handle, status); 1703 } 1704 1705 case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO: 1706 { 1707 uint32_t session_id = (uint32_t)x2; 1708 uint32_t key_uid = (uint32_t)x3; 1709 uint64_t ret_key_addr = (uint64_t)x4; 1710 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); 1711 1712 if (!is_address_in_ddr_range(ret_key_addr, key_len)) { 1713 ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid); 1714 status = INTEL_SIP_SMC_STATUS_REJECTED; 1715 SMC_RET1(handle, status); 1716 } 1717 1718 fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO, 1719 RESERVED_AS_ZERO, key_uid}; 1720 1721 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1722 GET_JOB_ID(x1), 1723 MBOX_FCS_GET_CS_KEY_INFO, 1724 (uint32_t *)&payload, 1725 sizeof(payload) / MBOX_WORD_BYTE, 1726 MBOX_CMD_FLAG_CASUAL, 1727 sip_smc_ret_nbytes_cb, 1728 (uint32_t *)ret_key_addr, 1729 2); 1730 SMC_RET1(handle, status); 1731 } 1732 1733 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_INIT: 1734 { 1735 status = intel_fcs_aes_crypt_init(x2, x3, x4, x5, 1736 x6, &mbox_error); 1737 SMC_RET1(handle, status); 1738 } 1739 1740 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_UPDATE: 1741 case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE: 1742 { 1743 uint32_t job_id = 0U; 1744 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE) ? 1745 true : false; 1746 1747 status = intel_fcs_aes_crypt_update_finalize(smc_fid, x1, x2, 1748 x3, x4, x5, x6, x7, x8, is_final, 1749 &job_id, x9, x10); 1750 SMC_RET1(handle, status); 1751 } 1752 1753 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT: 1754 { 1755 status = intel_fcs_get_digest_init(x2, x3, x4, x5, x6, 1756 &mbox_error); 1757 SMC_RET1(handle, status); 1758 } 1759 1760 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE: 1761 case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE: 1762 { 1763 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE) ? 1764 true : false; 1765 1766 status = intel_fcs_get_digest_update_finalize(smc_fid, x1, x2, 1767 x3, x4, x5, x6, (uint32_t *) &x7, 1768 is_final, &mbox_error, x8); 1769 1770 SMC_RET1(handle, status); 1771 } 1772 1773 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT: 1774 { 1775 status = intel_fcs_mac_verify_init(x2, x3, x4, x5, x6, 1776 &mbox_error); 1777 SMC_RET1(handle, status); 1778 } 1779 1780 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE: 1781 case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE: 1782 { 1783 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE) ? 1784 true : false; 1785 1786 status = intel_fcs_mac_verify_update_finalize(smc_fid, x1, x2, 1787 x3, x4, x5, x6, (uint32_t *) &x7, x8, 1788 is_final, &mbox_error, x9); 1789 SMC_RET1(handle, status); 1790 } 1791 1792 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT: 1793 { 1794 status = intel_fcs_ecdsa_hash_sign_init(x2, x3, x4, x5, x6, 1795 &mbox_error); 1796 SMC_RET1(handle, status); 1797 } 1798 1799 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1800 { 1801 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, x1, x2, x3, 1802 x4, x5, x6, (uint32_t *) &x7, 1803 &mbox_error); 1804 SMC_RET1(handle, status); 1805 } 1806 1807 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1808 { 1809 status = intel_fcs_ecdsa_sha2_data_sign_init(x2, x3, x4, x5, x6, 1810 &mbox_error); 1811 SMC_RET1(handle, status); 1812 } 1813 1814 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1815 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1816 { 1817 bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE) 1818 ? true : false; 1819 1820 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 1821 x1, x2, x3, x4, x5, x6, (uint32_t *) &x7, 1822 is_final, &mbox_error, x8); 1823 SMC_RET1(handle, status); 1824 } 1825 1826 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1827 { 1828 status = intel_fcs_ecdsa_hash_sig_verify_init(x2, x3, x4, x5, 1829 x6, &mbox_error); 1830 SMC_RET1(handle, status); 1831 } 1832 1833 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1834 { 1835 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, x1, 1836 x2, x3, x4, x5, x6, (uint32_t *) &x7, 1837 &mbox_error); 1838 SMC_RET1(handle, status); 1839 } 1840 1841 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1842 { 1843 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x2, x3, x4, 1844 x5, x6, &mbox_error); 1845 SMC_RET1(handle, status); 1846 } 1847 1848 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1849 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1850 { 1851 bool is_final = (smc_fid == 1852 ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE) ? 1853 true : false; 1854 1855 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1856 smc_fid, x1, x2, x3, x4, x5, x6, 1857 (uint32_t *) &x7, x8, is_final, 1858 &mbox_error, x9); 1859 SMC_RET1(handle, status); 1860 } 1861 1862 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT: 1863 { 1864 status = intel_fcs_ecdsa_get_pubkey_init(x2, x3, x4, x5, x6, 1865 &mbox_error); 1866 SMC_RET1(handle, status); 1867 } 1868 1869 case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1870 { 1871 status = intel_fcs_ecdsa_get_pubkey_finalize(smc_fid, x1, x2, x3, 1872 x4, (uint32_t *) &x5, &mbox_error); 1873 SMC_RET1(handle, status); 1874 } 1875 1876 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT: 1877 { 1878 status = intel_fcs_ecdh_request_init(x2, x3, x4, x5, x6, 1879 &mbox_error); 1880 SMC_RET1(handle, status); 1881 } 1882 1883 case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE: 1884 { 1885 uint32_t dest_size = (uint32_t)x7; 1886 1887 NOTICE("MBOX: %s, %d: x7 0x%x, dest_size 0x%x\n", 1888 __func__, __LINE__, (uint32_t)x7, dest_size); 1889 1890 status = intel_fcs_ecdh_request_finalize(smc_fid, x1, x2, x3, 1891 x4, x5, x6, (uint32_t *) &dest_size, 1892 &mbox_error); 1893 SMC_RET1(handle, status); 1894 } 1895 1896 case ALTERA_SIP_SMC_ASYNC_MCTP_MSG: 1897 { 1898 uint32_t *src_addr = (uint32_t *)x2; 1899 uint32_t src_size = (uint32_t)x3; 1900 uint32_t *dst_addr = (uint32_t *)x4; 1901 1902 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1), 1903 GET_JOB_ID(x1), 1904 MBOX_CMD_MCTP_MSG, 1905 src_addr, 1906 src_size / MBOX_WORD_BYTE, 1907 MBOX_CMD_FLAG_CASUAL, 1908 sip_smc_ret_nbytes_cb, 1909 dst_addr, 1910 2); 1911 1912 SMC_RET1(handle, status); 1913 } 1914 1915 case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST: 1916 { 1917 status = intel_fcs_hkdf_request(smc_fid, x1, x2, x3, x4, x5, x6, 1918 x7); 1919 SMC_RET1(handle, status); 1920 } 1921 1922 default: 1923 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1924 cookie, handle, flags); 1925 } /* switch (smc_fid) */ 1926 } 1927 #endif 1928 1929 /* 1930 * This function is responsible for handling all SiP calls from the NS world 1931 */ 1932 1933 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 1934 u_register_t x1, 1935 u_register_t x2, 1936 u_register_t x3, 1937 u_register_t x4, 1938 void *cookie, 1939 void *handle, 1940 u_register_t flags) 1941 { 1942 uint32_t retval = 0, completed_addr[3]; 1943 uint32_t retval2 = 0; 1944 uint32_t mbox_error = 0; 1945 uint32_t err_states = 0; 1946 uint64_t retval64, rsu_respbuf[9]; 1947 uint32_t seu_respbuf[3]; 1948 int status = INTEL_SIP_SMC_STATUS_OK; 1949 int mbox_status; 1950 unsigned int len_in_resp = 0; 1951 u_register_t x5, x6, x7; 1952 1953 switch (smc_fid) { 1954 case SIP_SVC_UID: 1955 /* Return UID to the caller */ 1956 SMC_UUID_RET(handle, intl_svc_uid); 1957 1958 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 1959 status = intel_mailbox_fpga_config_isdone(&err_states); 1960 SMC_RET4(handle, status, err_states, 0, 0); 1961 1962 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 1963 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1964 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 1965 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 1966 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 1967 1968 case INTEL_SIP_SMC_FPGA_CONFIG_START: 1969 status = intel_fpga_config_start(x1); 1970 SMC_RET4(handle, status, 0, 0, 0); 1971 1972 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 1973 status = intel_fpga_config_write(x1, x2); 1974 SMC_RET4(handle, status, 0, 0, 0); 1975 1976 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 1977 status = intel_fpga_config_completed_write(completed_addr, 1978 &retval, &rcv_id); 1979 switch (retval) { 1980 case 1: 1981 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1982 completed_addr[0], 0, 0); 1983 1984 case 2: 1985 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1986 completed_addr[0], 1987 completed_addr[1], 0); 1988 1989 case 3: 1990 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 1991 completed_addr[0], 1992 completed_addr[1], 1993 completed_addr[2]); 1994 1995 case 0: 1996 SMC_RET4(handle, status, 0, 0, 0); 1997 1998 default: 1999 mailbox_clear_response(); 2000 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 2001 } 2002 2003 case INTEL_SIP_SMC_REG_READ: 2004 status = intel_secure_reg_read(x1, &retval); 2005 SMC_RET3(handle, status, retval, x1); 2006 2007 case INTEL_SIP_SMC_REG_WRITE: 2008 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 2009 SMC_RET3(handle, status, retval, x1); 2010 2011 case INTEL_SIP_SMC_REG_UPDATE: 2012 status = intel_secure_reg_update(x1, (uint32_t)x2, 2013 (uint32_t)x3, &retval); 2014 SMC_RET3(handle, status, retval, x1); 2015 2016 case INTEL_SIP_SMC_RSU_STATUS: 2017 status = intel_rsu_status(rsu_respbuf, 2018 ARRAY_SIZE(rsu_respbuf)); 2019 if (status) { 2020 SMC_RET1(handle, status); 2021 } else { 2022 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 2023 rsu_respbuf[2], rsu_respbuf[3]); 2024 } 2025 2026 case INTEL_SIP_SMC_RSU_UPDATE: 2027 status = intel_rsu_update(x1); 2028 SMC_RET1(handle, status); 2029 2030 case INTEL_SIP_SMC_RSU_NOTIFY: 2031 status = intel_rsu_notify(x1); 2032 SMC_RET1(handle, status); 2033 2034 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 2035 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 2036 ARRAY_SIZE(rsu_respbuf), &retval); 2037 if (status) { 2038 SMC_RET1(handle, status); 2039 } else { 2040 SMC_RET2(handle, status, retval); 2041 } 2042 2043 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 2044 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 2045 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 2046 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 2047 2048 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 2049 status = intel_rsu_copy_dcmf_version(x1, x2); 2050 SMC_RET1(handle, status); 2051 2052 case INTEL_SIP_SMC_RSU_GET_DEVICE_INFO: 2053 status = intel_rsu_get_device_info((uint32_t *)rsu_respbuf, 2054 ARRAY_SIZE(rsu_respbuf)); 2055 if (status) { 2056 SMC_RET1(handle, status); 2057 } else { 2058 SMC_RET5(handle, status, rsu_respbuf[0], rsu_respbuf[1], 2059 rsu_respbuf[2], rsu_respbuf[3]); 2060 } 2061 2062 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 2063 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 2064 ((uint64_t)rsu_dcmf_stat[3] << 48) | 2065 ((uint64_t)rsu_dcmf_stat[2] << 32) | 2066 ((uint64_t)rsu_dcmf_stat[1] << 16) | 2067 rsu_dcmf_stat[0]); 2068 2069 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 2070 status = intel_rsu_copy_dcmf_status(x1); 2071 SMC_RET1(handle, status); 2072 2073 case INTEL_SIP_SMC_RSU_MAX_RETRY: 2074 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 2075 2076 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 2077 rsu_max_retry = x1; 2078 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 2079 2080 case INTEL_SIP_SMC_ECC_DBE: 2081 status = intel_ecc_dbe_notification(x1); 2082 SMC_RET1(handle, status); 2083 2084 case INTEL_SIP_SMC_SERVICE_COMPLETED: 2085 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 2086 &len_in_resp, &mbox_error); 2087 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 2088 2089 case INTEL_SIP_SMC_FIRMWARE_VERSION: 2090 status = intel_smc_fw_version(&retval); 2091 SMC_RET2(handle, status, retval); 2092 2093 case INTEL_SIP_SMC_MBOX_SEND_CMD: 2094 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2095 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2096 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 2097 &mbox_status, &len_in_resp); 2098 SMC_RET3(handle, status, mbox_status, len_in_resp); 2099 2100 case INTEL_SIP_SMC_GET_USERCODE: 2101 status = intel_smc_get_usercode(&retval); 2102 SMC_RET2(handle, status, retval); 2103 2104 case INTEL_SIP_SMC_FCS_CRYPTION: 2105 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2106 2107 if (x1 == FCS_MODE_DECRYPT) { 2108 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 2109 } else if (x1 == FCS_MODE_ENCRYPT) { 2110 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 2111 } else { 2112 status = INTEL_SIP_SMC_STATUS_REJECTED; 2113 } 2114 2115 SMC_RET3(handle, status, x4, x5); 2116 2117 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 2118 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2119 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2120 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2121 2122 if (x3 == FCS_MODE_DECRYPT) { 2123 status = intel_fcs_decryption_ext(smc_fid, 0, x1, x2, x4, x5, x6, 2124 (uint32_t *) &x7, &mbox_error, 0, 0, 0); 2125 } else if (x3 == FCS_MODE_ENCRYPT) { 2126 status = intel_fcs_encryption_ext(smc_fid, 0, x1, x2, x4, x5, x6, 2127 (uint32_t *) &x7, &mbox_error, 0, 0); 2128 } else { 2129 status = INTEL_SIP_SMC_STATUS_REJECTED; 2130 } 2131 2132 SMC_RET4(handle, status, mbox_error, x6, x7); 2133 2134 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 2135 status = intel_fcs_random_number_gen(x1, &retval64, 2136 &mbox_error); 2137 SMC_RET4(handle, status, mbox_error, x1, retval64); 2138 2139 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 2140 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 2141 &send_id); 2142 SMC_RET1(handle, status); 2143 2144 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 2145 status = intel_fcs_send_cert(smc_fid, 0, x1, x2, &send_id); 2146 SMC_RET1(handle, status); 2147 2148 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 2149 status = intel_fcs_get_provision_data(&send_id); 2150 SMC_RET1(handle, status); 2151 2152 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 2153 status = intel_fcs_cntr_set_preauth(smc_fid, 0, x1, x2, x3, 2154 &mbox_error); 2155 SMC_RET2(handle, status, mbox_error); 2156 2157 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 2158 status = intel_hps_set_bridges(x1, x2); 2159 SMC_RET1(handle, status); 2160 2161 case INTEL_SIP_SMC_HWMON_READTEMP: 2162 status = intel_hwmon_readtemp(x1, &retval); 2163 SMC_RET2(handle, status, retval); 2164 2165 case INTEL_SIP_SMC_HWMON_READVOLT: 2166 status = intel_hwmon_readvolt(x1, &retval); 2167 SMC_RET2(handle, status, retval); 2168 2169 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 2170 status = intel_fcs_sigma_teardown(x1, &mbox_error); 2171 SMC_RET2(handle, status, mbox_error); 2172 2173 case INTEL_SIP_SMC_FCS_CHIP_ID: 2174 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 2175 SMC_RET4(handle, status, mbox_error, retval, retval2); 2176 2177 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 2178 status = intel_fcs_attestation_subkey(x1, x2, x3, 2179 (uint32_t *) &x4, &mbox_error); 2180 SMC_RET4(handle, status, mbox_error, x3, x4); 2181 2182 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 2183 status = intel_fcs_get_measurement(x1, x2, x3, 2184 (uint32_t *) &x4, &mbox_error); 2185 SMC_RET4(handle, status, mbox_error, x3, x4); 2186 2187 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 2188 status = intel_fcs_get_attestation_cert(smc_fid, 0, x1, x2, 2189 (uint32_t *) &x3, &mbox_error); 2190 SMC_RET4(handle, status, mbox_error, x2, x3); 2191 2192 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 2193 status = intel_fcs_create_cert_on_reload(smc_fid, 0, x1, &mbox_error); 2194 SMC_RET2(handle, status, mbox_error); 2195 2196 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 2197 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 2198 SMC_RET3(handle, status, mbox_error, retval); 2199 2200 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 2201 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 2202 SMC_RET2(handle, status, mbox_error); 2203 2204 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 2205 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 2206 SMC_RET1(handle, status); 2207 2208 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 2209 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 2210 (uint32_t *) &x4, &mbox_error); 2211 SMC_RET4(handle, status, mbox_error, x3, x4); 2212 2213 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 2214 status = intel_fcs_remove_crypto_service_key(x1, x2, 2215 &mbox_error); 2216 SMC_RET2(handle, status, mbox_error); 2217 2218 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 2219 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 2220 (uint32_t *) &x4, &mbox_error); 2221 SMC_RET4(handle, status, mbox_error, x3, x4); 2222 2223 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 2224 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2225 status = intel_fcs_get_digest_init(x1, x2, x3, 2226 x4, x5, &mbox_error); 2227 SMC_RET2(handle, status, mbox_error); 2228 2229 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 2230 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2231 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2232 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2, 2233 x3, x4, x5, (uint32_t *) &x6, false, 2234 &mbox_error, 0); 2235 SMC_RET4(handle, status, mbox_error, x5, x6); 2236 2237 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 2238 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2239 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2240 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2, 2241 x3, x4, x5, (uint32_t *) &x6, true, 2242 &mbox_error, 0); 2243 SMC_RET4(handle, status, mbox_error, x5, x6); 2244 2245 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 2246 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2247 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2248 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 2249 x4, x5, (uint32_t *) &x6, false, 2250 &mbox_error, &send_id); 2251 SMC_RET4(handle, status, mbox_error, x5, x6); 2252 2253 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 2254 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2255 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2256 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 2257 x4, x5, (uint32_t *) &x6, true, 2258 &mbox_error, &send_id); 2259 SMC_RET4(handle, status, mbox_error, x5, x6); 2260 2261 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 2262 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2263 status = intel_fcs_mac_verify_init(x1, x2, x3, 2264 x4, x5, &mbox_error); 2265 SMC_RET2(handle, status, mbox_error); 2266 2267 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 2268 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2269 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2270 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2271 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2, 2272 x3, x4, x5, (uint32_t *) &x6, x7, false, 2273 &mbox_error, 0); 2274 SMC_RET4(handle, status, mbox_error, x5, x6); 2275 2276 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 2277 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2278 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2279 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2280 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2, 2281 x3, x4, x5, (uint32_t *) &x6, x7, true, 2282 &mbox_error, 0); 2283 SMC_RET4(handle, status, mbox_error, x5, x6); 2284 2285 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 2286 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2287 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2288 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2289 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 2290 x4, x5, (uint32_t *) &x6, x7, 2291 false, &mbox_error, &send_id); 2292 SMC_RET4(handle, status, mbox_error, x5, x6); 2293 2294 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 2295 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2296 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2297 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2298 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 2299 x4, x5, (uint32_t *) &x6, x7, 2300 true, &mbox_error, &send_id); 2301 SMC_RET4(handle, status, mbox_error, x5, x6); 2302 2303 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 2304 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2305 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 2306 x4, x5, &mbox_error); 2307 SMC_RET2(handle, status, mbox_error); 2308 2309 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 2310 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2311 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2312 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 2313 0, x1, x2, x3, x4, x5, (uint32_t *) &x6, 2314 false, &mbox_error, 0); 2315 SMC_RET4(handle, status, mbox_error, x5, x6); 2316 2317 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 2318 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2319 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2320 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid, 2321 0, x1, x2, x3, x4, x5, (uint32_t *) &x6, 2322 true, &mbox_error, 0); 2323 SMC_RET4(handle, status, mbox_error, x5, x6); 2324 2325 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 2326 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2327 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2328 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 2329 x2, x3, x4, x5, (uint32_t *) &x6, false, 2330 &mbox_error, &send_id); 2331 SMC_RET4(handle, status, mbox_error, x5, x6); 2332 2333 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 2334 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2335 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2336 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 2337 x2, x3, x4, x5, (uint32_t *) &x6, true, 2338 &mbox_error, &send_id); 2339 SMC_RET4(handle, status, mbox_error, x5, x6); 2340 2341 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 2342 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2343 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 2344 x4, x5, &mbox_error); 2345 SMC_RET2(handle, status, mbox_error); 2346 2347 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 2348 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2349 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2350 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, 0, x1, x2, 2351 x3, x4, x5, (uint32_t *) &x6, 2352 &mbox_error); 2353 SMC_RET4(handle, status, mbox_error, x5, x6); 2354 2355 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 2356 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2357 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 2358 x4, x5, &mbox_error); 2359 SMC_RET2(handle, status, mbox_error); 2360 2361 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 2362 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2363 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2364 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, 0, x1, 2365 x2, x3, x4, x5, (uint32_t *) &x6, 2366 &mbox_error); 2367 SMC_RET4(handle, status, mbox_error, x5, x6); 2368 2369 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 2370 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2371 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 2372 x4, x5, &mbox_error); 2373 SMC_RET2(handle, status, mbox_error); 2374 2375 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 2376 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2377 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2378 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2379 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 2380 smc_fid, 0, x1, x2, x3, x4, x5, 2381 (uint32_t *) &x6, x7, false, 2382 &mbox_error, 0); 2383 SMC_RET4(handle, status, mbox_error, x5, x6); 2384 2385 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 2386 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2387 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2388 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2389 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 2390 x1, x2, x3, x4, x5, (uint32_t *) &x6, 2391 x7, false, &mbox_error, &send_id); 2392 SMC_RET4(handle, status, mbox_error, x5, x6); 2393 2394 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 2395 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2396 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2397 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2398 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 2399 x1, x2, x3, x4, x5, (uint32_t *) &x6, 2400 x7, true, &mbox_error, &send_id); 2401 SMC_RET4(handle, status, mbox_error, x5, x6); 2402 2403 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 2404 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2405 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2406 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 2407 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 2408 smc_fid, 0, x1, x2, x3, x4, x5, 2409 (uint32_t *) &x6, x7, true, 2410 &mbox_error, 0); 2411 SMC_RET4(handle, status, mbox_error, x5, x6); 2412 2413 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 2414 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2415 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 2416 x4, x5, &mbox_error); 2417 SMC_RET2(handle, status, mbox_error); 2418 2419 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 2420 status = intel_fcs_ecdsa_get_pubkey_finalize( 2421 INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE, 0, 2422 x1, x2, x3, (uint32_t *) &x4, &mbox_error); 2423 SMC_RET4(handle, status, mbox_error, x3, x4); 2424 2425 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 2426 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2427 status = intel_fcs_ecdh_request_init(x1, x2, x3, 2428 x4, x5, &mbox_error); 2429 SMC_RET2(handle, status, mbox_error); 2430 2431 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 2432 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2433 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2434 status = intel_fcs_ecdh_request_finalize(smc_fid, 0, x1, x2, x3, 2435 x4, x5, (uint32_t *) &x6, &mbox_error); 2436 SMC_RET4(handle, status, mbox_error, x5, x6); 2437 2438 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 2439 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2440 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 2441 &mbox_error); 2442 SMC_RET2(handle, status, mbox_error); 2443 2444 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 2445 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2446 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2447 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2, 2448 x3, x4, x5, x6, 0, false, &send_id, 0, 0); 2449 SMC_RET1(handle, status); 2450 2451 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 2452 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 2453 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 2454 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2, 2455 x3, x4, x5, x6, 0, true, &send_id, 0, 0); 2456 SMC_RET1(handle, status); 2457 2458 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 2459 case INTEL_SIP_SMC_FCS_SDM_REMAPPER_CONFIG: 2460 status = intel_smmu_hps_remapper_config(x1); 2461 SMC_RET1(handle, status); 2462 #endif 2463 2464 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 2465 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 2466 &mbox_error); 2467 SMC_RET4(handle, status, mbox_error, x1, retval64); 2468 2469 case INTEL_SIP_SMC_SVC_VERSION: 2470 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 2471 SIP_SVC_VERSION_MAJOR, 2472 SIP_SVC_VERSION_MINOR); 2473 2474 case INTEL_SIP_SMC_SEU_ERR_STATUS: 2475 status = intel_sdm_seu_err_read(seu_respbuf, 2476 ARRAY_SIZE(seu_respbuf)); 2477 if (status) { 2478 SMC_RET1(handle, status); 2479 } else { 2480 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); 2481 } 2482 2483 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR: 2484 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2); 2485 SMC_RET1(handle, status); 2486 2487 case INTEL_SIP_SMC_ATF_BUILD_VER: 2488 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, VERSION_MAJOR, 2489 VERSION_MINOR, VERSION_PATCH); 2490 2491 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 2492 case INTEL_SIP_SMC_INJECT_IO96B_ECC_ERR: 2493 intel_inject_io96b_ecc_err((uint32_t *)&x1, (uint32_t)x2); 2494 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 2495 #endif 2496 2497 default: 2498 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 2499 cookie, handle, flags); 2500 } 2501 } 2502 2503 uintptr_t sip_smc_handler(uint32_t smc_fid, 2504 u_register_t x1, 2505 u_register_t x2, 2506 u_register_t x3, 2507 u_register_t x4, 2508 void *cookie, 2509 void *handle, 2510 u_register_t flags) 2511 { 2512 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 2513 2514 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 2515 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 2516 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 2517 cookie, handle, flags); 2518 } 2519 #if SIP_SVC_V3 2520 else if ((cmd >= INTEL_SIP_SMC_CMD_V3_RANGE_BEGIN) && 2521 (cmd <= INTEL_SIP_SMC_CMD_V3_RANGE_END)) { 2522 uintptr_t ret = sip_smc_handler_v3(smc_fid, x1, x2, x3, x4, 2523 cookie, handle, flags); 2524 return ret; 2525 } 2526 #endif 2527 else { 2528 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 2529 cookie, handle, flags); 2530 } 2531 } 2532 2533 DECLARE_RT_SVC( 2534 socfpga_sip_svc, 2535 OEN_SIP_START, 2536 OEN_SIP_END, 2537 SMC_TYPE_FAST, 2538 NULL, 2539 sip_smc_handler 2540 ); 2541 2542 DECLARE_RT_SVC( 2543 socfpga_sip_svc_std, 2544 OEN_SIP_START, 2545 OEN_SIP_END, 2546 SMC_TYPE_YIELD, 2547 NULL, 2548 sip_smc_handler 2549 ); 2550