Merge changes from topic "mcn" into integration

* changes:
feat(tc): add MCN PMU nodes in dts for TC4
feat(tc): add 'kaslr-seed' node in device tree for TC3
feat(tc): enable MCN non-secure acc

Merge changes from topic "mcn" into integration

* changes:
feat(tc): add MCN PMU nodes in dts for TC4
feat(tc): add 'kaslr-seed' node in device tree for TC3
feat(tc): enable MCN non-secure access to pmu counters on TC4
feat(tc): define MCN related macros for TC4

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fix(rdv3): add console name to checksum calculation on RD-V3

The name field of console_info structure was missed in
checksum calculation. This is corrected by adding a new
helper checksum_calc() whi

fix(rdv3): add console name to checksum calculation on RD-V3

The name field of console_info structure was missed in
checksum calculation. This is corrected by adding a new
helper checksum_calc() which computes the checksum in a
field agnostic manner.

Change-Id: I98d35d53e1faccf1221e8eddb122558ae359a2d5
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>

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Merge "fix(css): turn the redistributor off on PSCI CPU_OFF" into integration

feat(tc): enable MCN non-secure access to pmu counters on TC4

MCN PMU counters are by default non-accesible from non-secure world,
so enable the non-secure access to those PMU counters so that linux

feat(tc): enable MCN non-secure access to pmu counters on TC4

MCN PMU counters are by default non-accesible from non-secure world,
so enable the non-secure access to those PMU counters so that linux
perf driver can read them.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I1cf1f88f97e9062592fd5603a78fd36f15a15f89

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feat(tc): define MCN related macros for TC4

Define MCN related macros for TC4 to add TC4 specific MCN PMU
nodes in dts and to enable MCN PMU NS access in further commits.

Signed-off-by: Jagdish Ged

feat(tc): define MCN related macros for TC4

Define MCN related macros for TC4 to add TC4 specific MCN PMU
nodes in dts and to enable MCN PMU NS access in further commits.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ifc02fcd833888a9953fac404585468316aa0168c

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feat(mt8196): enable APU on mt8196

Enable APU on MT8196

Change-Id: Ic746571ba3ecf9db512e26ee2f89683f2d656239
Signed-off-by: Karl Li <karl.li@mediatek.com>

feat(mt8196): add APU SMMU hardware semaphore operations

Add APU SMMU hardware semaphore operations to make APU SMMU
able to sync the power status.

Change-Id: I1926cab990fba54a2ea694ac6d9e87135dfb1

feat(mt8196): add APU SMMU hardware semaphore operations

Add APU SMMU hardware semaphore operations to make APU SMMU
able to sync the power status.

Change-Id: I1926cab990fba54a2ea694ac6d9e87135dfb19cf
Signed-off-by: Karl Li <karl.li@mediatek.com>

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feat(mt8196): add smpu protection for APU secure memory

1. Add smpu protection for APU secure memory.
2. Move emi mpu protection for mt8188 to platform folder

Since the smpu driver has not upstream

feat(mt8196): add smpu protection for APU secure memory

1. Add smpu protection for APU secure memory.
2. Move emi mpu protection for mt8188 to platform folder

Since the smpu driver has not upstream, we currently leave the interface
and do nothing until smpu driver is ready.

Change-Id: Id70162e90a7deb64befe90f09a841a0903535482
Signed-off-by: Karl Li <karl.li@mediatek.com>

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feat(mt8196): add APU RCX DevAPC setting

APU RCX is a sub-domain in apusys, connecting several APU components.
The APU RCX DevAPC control lives in APU and can only be set after
APU is powered on.
Th

feat(mt8196): add APU RCX DevAPC setting

APU RCX is a sub-domain in apusys, connecting several APU components.
The APU RCX DevAPC control lives in APU and can only be set after
APU is powered on.
The APUSYS kernel driver will trigger RCX DevAPC init by smc call.

Change-Id: I3a9b014ea1be7ee80fd6861ad088f1dec5410872
Signed-off-by: Karl Li <karl.li@mediatek.com>

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feat(mt8196): add APU kernel control operations

Add APU kernel control operations to provide the bootup init functions.

1. Add software workaround for certain operations on mt8196.
2. Add APU logge

feat(mt8196): add APU kernel control operations

Add APU kernel control operations to provide the bootup init functions.

1. Add software workaround for certain operations on mt8196.
2. Add APU logger operations.
3. Add function to clear mbox spare register, which is used in APU
booting process.
4. Add function to setup CE binary to make sure the CE binary version
is align with the APU firmware.

Change-Id: Ic99adba1409c020c72179ea135e0d4291fc3f384
Signed-off-by: Karl Li <karl.li@mediatek.com>

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feat(mt8196): add APU power on/off functions

1. Add APU power on/off functions
2. Refine the APU power on/off interface for mt8188
3. Add dcm setup function to support mt8196

Change-Id: Ie1caca40f8

feat(mt8196): add APU power on/off functions

1. Add APU power on/off functions
2. Refine the APU power on/off interface for mt8188
3. Add dcm setup function to support mt8196

Change-Id: Ie1caca40f89de71caac037fabe7e7455ff2a1872
Signed-off-by: Karl Li <karl.li@mediatek.com>

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feat(mt8196): add APUMMU setting

APUMMU is the MMU in APU, which is responsible for inner address
mapping. The APU kernel driver will setup the APUMMU by SMC call.

Change-Id: Iad7532883e42c288aeb0d

feat(mt8196): add APUMMU setting

APUMMU is the MMU in APU, which is responsible for inner address
mapping. The APU kernel driver will setup the APUMMU by SMC call.

Change-Id: Iad7532883e42c288aeb0d23ab419f4dc6d8630f2
Signed-off-by: Karl Li <karl.li@mediatek.com>

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feat(mt8196): enable apusys mailbox mpu protection

Enable mt8196 apusys mailbox mpu protection and
move the mt8188 setting to platform folder

Change-Id: I76b68318bb88e56b12cdacd9e2b998699ca6b48e
Si

feat(mt8196): enable apusys mailbox mpu protection

Enable mt8196 apusys mailbox mpu protection and
move the mt8188 setting to platform folder

Change-Id: I76b68318bb88e56b12cdacd9e2b998699ca6b48e
Signed-off-by: Karl Li <karl.li@mediatek.com>

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feat(mt8196): enable apusys security control

Remap the request from domain 5, 7, 14 to domain 6 and setup security
sideband

Change-Id: I06d377f4bcc542bf22e0a04ffb45cf52b7528a75
Signed-off-by: Karl

feat(mt8196): enable apusys security control

Remap the request from domain 5, 7, 14 to domain 6 and setup security
sideband

Change-Id: I06d377f4bcc542bf22e0a04ffb45cf52b7528a75
Signed-off-by: Karl Li <karl.li@mediatek.com>

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feat(mt8196): add APUSYS AO DevAPC setting

Apusys AO DevAPC is a set of control registers inside APU, controlling
the access permission of APU AO (Always On) domain.

This patch add the mt8196 APU A

feat(mt8196): add APUSYS AO DevAPC setting

Apusys AO DevAPC is a set of control registers inside APU, controlling
the access permission of APU AO (Always On) domain.

This patch add the mt8196 APU AO DevAPC setting to setup the protection.

Change-Id: I975a92795031cd1813442302890e29b671ef16f1
Signed-off-by: Karl Li <karl.li@mediatek.com>

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feat(mt8196): add APU power-on init flow

Add the APU (AI processing unit) power init flow to prepare the hardware
setting before using APU power functions.

Change-Id: I595b1d5100a4f083263de6527f920

feat(mt8196): add APU power-on init flow

Add the APU (AI processing unit) power init flow to prepare the hardware
setting before using APU power functions.

Change-Id: I595b1d5100a4f083263de6527f920e5168700b7a
Signed-off-by: Karl Li <karl.li@mediatek.com>

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Merge changes from topic "hm/heap-info" into integration

* changes:
fix(handoff): remove XFERLIST_TB_FW_CONFIG
feat(arm): migrate heap info to fw handoff
feat(mbedtls): introduce crypto lib he

Merge changes from topic "hm/heap-info" into integration

* changes:
fix(handoff): remove XFERLIST_TB_FW_CONFIG
feat(arm): migrate heap info to fw handoff
feat(mbedtls): introduce crypto lib heap info struct
feat(handoff): add Mbed-TLS heap info entry tag
refactor(arm): refactor secure TL initialization
fix(handoff): fix message formatting of hex values
feat(handoff): add func to check and init a tl
fix(arm): resolve dangling comments around macros

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feat(arm): migrate heap info to fw handoff

Mbed-TLS requires platforms to allocate it a heap for it's own internal
usage. This heap is typically between shared by BL1 and BL2 to conserve
memory.The

feat(arm): migrate heap info to fw handoff

Mbed-TLS requires platforms to allocate it a heap for it's own internal
usage. This heap is typically between shared by BL1 and BL2 to conserve
memory.The base address and size of the heap are conveyed from BL1 to
BL2 through the config TB_FW_CONFIG.

This slightly awkward approach necessitates declaring a placeholder node
in the DTS. At runtime, this node is populated with the actual values of
the heap information. Instead, since this is dynamic information, and
simple to represent through C structures, transmit it to later stages
using the firmware handoff framework.

With this migration, remove references to TB_FW_CONFIG when firmware
handoff is enabled, as it is no longer needed. The setup code now relies
solely on TL structures to configure the TB firmware

Change-Id: Iff00dc742924a055b8bd304f15eec03ce3c6d1ef
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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refactor(arm): refactor secure TL initialization

The initialization logic for the secure transfer list is currently
scattered and duplicated across platform setup code. This not only leads
to ineffi

refactor(arm): refactor secure TL initialization

The initialization logic for the secure transfer list is currently
scattered and duplicated across platform setup code. This not only leads
to inefficiency but also complicates access to transfer lists from other
parts of the code without invoking setup functions. For instance,
arm_bl2_setup_next_ep_info acts as a thin wrapper in arm_bl2_setup.c to
provide access to the secure transfer list.

To streamline the interface, all setup code has been consolidated into a
central location.

Change-Id: I99d2a567ff39df88baa57e7e08607fccb8af189c
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(arm): resolve dangling comments around macros

Fix dangling comments around define guards, addressing leftovers from
fe94a21a6 ("fix(arm): move HW_CONFIG relocation into BL31") which
implicitly r

fix(arm): resolve dangling comments around macros

Fix dangling comments around define guards, addressing leftovers from
fe94a21a6 ("fix(arm): move HW_CONFIG relocation into BL31") which
implicitly removed constraints on using HW_CONFIG with RESET_TO_BL2.

Change-Id: I19d61812fed6fa4b668875e5bf4eafd1a8a660f6
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(tc): define status to fix SPM tests

The failure was caused by missing a variable definition, `status`
in the RSE initialisation patch.

Change-Id: I937a39e20fae39f3a6d14fe66af578c166545301
Signe

fix(tc): define status to fix SPM tests

The failure was caused by missing a variable definition, `status`
in the RSE initialisation patch.

Change-Id: I937a39e20fae39f3a6d14fe66af578c166545301
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(css): turn the redistributor off on PSCI CPU_OFF

When GICR_WAKER.ProcessorSleep == 1 (i.e. after gicv3_cpuif_disable())
the GIC will assert the WakeRequest signal to try and wake the core up
ins

fix(css): turn the redistributor off on PSCI CPU_OFF

When GICR_WAKER.ProcessorSleep == 1 (i.e. after gicv3_cpuif_disable())
the GIC will assert the WakeRequest signal to try and wake the core up
instead of delivering an interrupt. This is useful when a core is in
some kind of suspend state.

However, when the core is properly off (CPU_OFF), it shouldn't get woken
up in any way other than a CPU_ON call. In the general case interrupts
would be routed away so this doesn't matter. But in case they aren't, we
want the core to stay off.

So turn the redistributor off on CPU_OFF calls. This will prevent the
WakeRequest from being sent.

Change-Id: I7f20591d1c83a4a9639281ef86caa79d6669b536
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(psa): increase psa-mbedtls heap size for rsa" into integration

Merge changes from topic "gerrit-master-v3" into integration

* changes:
feat(qemu-sbsa): add support for RME on SBSA machine
feat(qemu-sbsa): configure RMM manifest based on system RAM
feat(qe

Merge changes from topic "gerrit-master-v3" into integration

* changes:
feat(qemu-sbsa): add support for RME on SBSA machine
feat(qemu-sbsa): configure RMM manifest based on system RAM
feat(qemu-sbsa): configure GPT based on system RAM
feat(qemu-sbsa): adjust DT memory start address when supporting RME
feat(qemu-sbsa): relocate DT after the RMM when RME is enabled
feat(qemu-sbsa): dissociate QEMU NS start address and NS_DRAM0_BASE
feat(qemu-sbsa): increase maximum FIP size
refactor(qemu-sbsa): move all DT related functions to sbsa_platform.c
refactor(qemu-sbsa): create accessor functions for platform info
refactor(qemu-sbsa): rename function sip_svc_init() to something more meaningful
refactor(qemu-sbsa): move DT related structures to their own header
refactor(qemu-sbsa): rename struct dynamic_platform_info
refactor(qemu): make L0GPT size configurable
refactor(qemu): move GPT setup to BL31
fix(qemu-sbsa): fix compilation error when accessing DT functions

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Merge "feat(mt8196): enable DP and eDP for mt8196" into integration