1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch.h> 11 #include <arch_features.h> 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/delay_timer.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/extensions/spe.h> 19 #include <lib/pmf/pmf.h> 20 #include <lib/runtime_instr.h> 21 #include <lib/utils.h> 22 #include <plat/common/platform.h> 23 24 #include "psci_private.h" 25 26 /* 27 * SPD power management operations, expected to be supplied by the registered 28 * SPD on successful SP initialization 29 */ 30 const spd_pm_ops_t *psci_spd_pm; 31 32 /* 33 * PSCI requested local power state map. This array is used to store the local 34 * power states requested by a CPU for power levels from level 1 to 35 * PLAT_MAX_PWR_LVL. It does not store the requested local power state for power 36 * level 0 (PSCI_CPU_PWR_LVL) as the requested and the target power state for a 37 * CPU are the same. 38 * 39 * During state coordination, the platform is passed an array containing the 40 * local states requested for a particular non cpu power domain by each cpu 41 * within the domain. 42 * 43 * TODO: Dense packing of the requested states will cause cache thrashing 44 * when multiple power domains write to it. If we allocate the requested 45 * states at each power level in a cache-line aligned per-domain memory, 46 * the cache thrashing can be avoided. 47 */ 48 static plat_local_state_t 49 psci_req_local_pwr_states[PLAT_MAX_PWR_LVL][PLATFORM_CORE_COUNT]; 50 51 unsigned int psci_plat_core_count; 52 53 /******************************************************************************* 54 * Arrays that hold the platform's power domain tree information for state 55 * management of power domains. 56 * Each node in the array 'psci_non_cpu_pd_nodes' corresponds to a power domain 57 * which is an ancestor of a CPU power domain. 58 * Each node in the array 'psci_cpu_pd_nodes' corresponds to a cpu power domain 59 ******************************************************************************/ 60 non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS] 61 #if USE_COHERENT_MEM 62 __section(".tzfw_coherent_mem") 63 #endif 64 ; 65 66 /* Lock for PSCI state coordination */ 67 DEFINE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); 68 69 cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; 70 71 /******************************************************************************* 72 * Pointer to functions exported by the platform to complete power mgmt. ops 73 ******************************************************************************/ 74 const plat_psci_ops_t *psci_plat_pm_ops; 75 76 /****************************************************************************** 77 * Check that the maximum power level supported by the platform makes sense 78 *****************************************************************************/ 79 CASSERT((PLAT_MAX_PWR_LVL <= PSCI_MAX_PWR_LVL) && 80 (PLAT_MAX_PWR_LVL >= PSCI_CPU_PWR_LVL), 81 assert_platform_max_pwrlvl_check); 82 83 #if PSCI_OS_INIT_MODE 84 /******************************************************************************* 85 * The power state coordination mode used in CPU_SUSPEND. 86 * Defaults to platform-coordinated mode. 87 ******************************************************************************/ 88 suspend_mode_t psci_suspend_mode = PLAT_COORD; 89 #endif 90 91 /* 92 * The plat_local_state used by the platform is one of these types: RUN, 93 * RETENTION and OFF. The platform can define further sub-states for each type 94 * apart from RUN. This categorization is done to verify the sanity of the 95 * psci_power_state passed by the platform and to print debug information. The 96 * categorization is done on the basis of the following conditions: 97 * 98 * 1. If (plat_local_state == 0) then the category is STATE_TYPE_RUN. 99 * 100 * 2. If (0 < plat_local_state <= PLAT_MAX_RET_STATE), then the category is 101 * STATE_TYPE_RETN. 102 * 103 * 3. If (plat_local_state > PLAT_MAX_RET_STATE), then the category is 104 * STATE_TYPE_OFF. 105 */ 106 typedef enum plat_local_state_type { 107 STATE_TYPE_RUN = 0, 108 STATE_TYPE_RETN, 109 STATE_TYPE_OFF 110 } plat_local_state_type_t; 111 112 /* Function used to categorize plat_local_state. */ 113 static plat_local_state_type_t find_local_state_type(plat_local_state_t state) 114 { 115 if (state != 0U) { 116 if (state > PLAT_MAX_RET_STATE) { 117 return STATE_TYPE_OFF; 118 } else { 119 return STATE_TYPE_RETN; 120 } 121 } else { 122 return STATE_TYPE_RUN; 123 } 124 } 125 126 /****************************************************************************** 127 * Check that the maximum retention level supported by the platform is less 128 * than the maximum off level. 129 *****************************************************************************/ 130 CASSERT(PLAT_MAX_RET_STATE < PLAT_MAX_OFF_STATE, 131 assert_platform_max_off_and_retn_state_check); 132 133 /****************************************************************************** 134 * This function ensures that the power state parameter in a CPU_SUSPEND request 135 * is valid. If so, it returns the requested states for each power level. 136 *****************************************************************************/ 137 int psci_validate_power_state(unsigned int power_state, 138 psci_power_state_t *state_info) 139 { 140 /* Check SBZ bits in power state are zero */ 141 if (psci_check_power_state(power_state) != 0U) 142 return PSCI_E_INVALID_PARAMS; 143 144 assert(psci_plat_pm_ops->validate_power_state != NULL); 145 146 /* Validate the power_state using platform pm_ops */ 147 return psci_plat_pm_ops->validate_power_state(power_state, state_info); 148 } 149 150 /****************************************************************************** 151 * This function retrieves the `psci_power_state_t` for system suspend from 152 * the platform. 153 *****************************************************************************/ 154 void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info) 155 { 156 /* 157 * Assert that the required pm_ops hook is implemented to ensure that 158 * the capability detected during psci_setup() is valid. 159 */ 160 assert(psci_plat_pm_ops->get_sys_suspend_power_state != NULL); 161 162 /* 163 * Query the platform for the power_state required for system suspend 164 */ 165 psci_plat_pm_ops->get_sys_suspend_power_state(state_info); 166 } 167 168 #if PSCI_OS_INIT_MODE 169 /******************************************************************************* 170 * This function verifies that all the other cores at the 'end_pwrlvl' have been 171 * idled and the current CPU is the last running CPU at the 'end_pwrlvl'. 172 * Returns 1 (true) if the current CPU is the last ON CPU or 0 (false) 173 * otherwise. 174 ******************************************************************************/ 175 static bool psci_is_last_cpu_to_idle_at_pwrlvl(unsigned int my_idx, unsigned int end_pwrlvl) 176 { 177 unsigned int lvl; 178 unsigned int parent_idx = 0; 179 unsigned int cpu_start_idx, ncpus, cpu_idx; 180 plat_local_state_t local_state; 181 182 if (end_pwrlvl == PSCI_CPU_PWR_LVL) { 183 return true; 184 } 185 186 parent_idx = psci_cpu_pd_nodes[my_idx].parent_node; 187 for (lvl = PSCI_CPU_PWR_LVL + U(1); lvl < end_pwrlvl; lvl++) { 188 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 189 } 190 191 cpu_start_idx = psci_non_cpu_pd_nodes[parent_idx].cpu_start_idx; 192 ncpus = psci_non_cpu_pd_nodes[parent_idx].ncpus; 193 194 for (cpu_idx = cpu_start_idx; cpu_idx < cpu_start_idx + ncpus; 195 cpu_idx++) { 196 local_state = psci_get_cpu_local_state_by_idx(cpu_idx); 197 if (cpu_idx == my_idx) { 198 assert(is_local_state_run(local_state) != 0); 199 continue; 200 } 201 202 if (is_local_state_run(local_state) != 0) { 203 return false; 204 } 205 } 206 207 return true; 208 } 209 #endif 210 211 /******************************************************************************* 212 * This function verifies that all the other cores in the system have been 213 * turned OFF and the current CPU is the last running CPU in the system. 214 * Returns true, if the current CPU is the last ON CPU or false otherwise. 215 ******************************************************************************/ 216 bool psci_is_last_on_cpu(unsigned int my_idx) 217 { 218 for (unsigned int cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) { 219 if (cpu_idx == my_idx) { 220 assert(psci_get_aff_info_state() == AFF_STATE_ON); 221 continue; 222 } 223 224 if (psci_get_aff_info_state_by_idx(cpu_idx) != AFF_STATE_OFF) { 225 VERBOSE("core=%u other than current core=%u %s\n", 226 cpu_idx, my_idx, "running in the system"); 227 return false; 228 } 229 } 230 231 return true; 232 } 233 234 /******************************************************************************* 235 * This function verifies that all cores in the system have been turned ON. 236 * Returns true, if all CPUs are ON or false otherwise. 237 ******************************************************************************/ 238 static bool psci_are_all_cpus_on(void) 239 { 240 unsigned int cpu_idx; 241 242 for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) { 243 if (psci_get_aff_info_state_by_idx(cpu_idx) == AFF_STATE_OFF) { 244 return false; 245 } 246 } 247 248 return true; 249 } 250 251 /******************************************************************************* 252 * Routine to return the maximum power level to traverse to after a cpu has 253 * been physically powered up. It is expected to be called immediately after 254 * reset from assembler code. 255 ******************************************************************************/ 256 static unsigned int get_power_on_target_pwrlvl(void) 257 { 258 unsigned int pwrlvl; 259 260 /* 261 * Assume that this cpu was suspended and retrieve its target power 262 * level. If it wasn't, the cpu is off so this will be PLAT_MAX_PWR_LVL. 263 */ 264 pwrlvl = psci_get_suspend_pwrlvl(); 265 assert(pwrlvl < PSCI_INVALID_PWR_LVL); 266 return pwrlvl; 267 } 268 269 /****************************************************************************** 270 * Helper function to update the requested local power state array. This array 271 * does not store the requested state for the CPU power level. Hence an 272 * assertion is added to prevent us from accessing the CPU power level. 273 *****************************************************************************/ 274 static void psci_set_req_local_pwr_state(unsigned int pwrlvl, 275 unsigned int cpu_idx, 276 plat_local_state_t req_pwr_state) 277 { 278 assert(pwrlvl > PSCI_CPU_PWR_LVL); 279 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && 280 (cpu_idx < psci_plat_core_count)) { 281 psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx] = req_pwr_state; 282 } 283 } 284 285 /****************************************************************************** 286 * This function initializes the psci_req_local_pwr_states. 287 *****************************************************************************/ 288 void __init psci_init_req_local_pwr_states(void) 289 { 290 /* Initialize the requested state of all non CPU power domains as OFF */ 291 unsigned int pwrlvl; 292 unsigned int core; 293 294 for (pwrlvl = 0U; pwrlvl < PLAT_MAX_PWR_LVL; pwrlvl++) { 295 for (core = 0; core < psci_plat_core_count; core++) { 296 psci_req_local_pwr_states[pwrlvl][core] = 297 PLAT_MAX_OFF_STATE; 298 } 299 } 300 } 301 302 /****************************************************************************** 303 * Helper function to return a reference to an array containing the local power 304 * states requested by each cpu for a power domain at 'pwrlvl'. The size of the 305 * array will be the number of cpu power domains of which this power domain is 306 * an ancestor. These requested states will be used to determine a suitable 307 * target state for this power domain during psci state coordination. An 308 * assertion is added to prevent us from accessing the CPU power level. 309 *****************************************************************************/ 310 static plat_local_state_t *psci_get_req_local_pwr_states(unsigned int pwrlvl, 311 unsigned int cpu_idx) 312 { 313 assert(pwrlvl > PSCI_CPU_PWR_LVL); 314 315 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && 316 (cpu_idx < psci_plat_core_count)) { 317 return &psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx]; 318 } else 319 return NULL; 320 } 321 322 #if PSCI_OS_INIT_MODE 323 /****************************************************************************** 324 * Helper function to save a copy of the psci_req_local_pwr_states (prev) for a 325 * CPU (cpu_idx), and update psci_req_local_pwr_states with the new requested 326 * local power states (state_info). 327 *****************************************************************************/ 328 void psci_update_req_local_pwr_states(unsigned int end_pwrlvl, 329 unsigned int cpu_idx, 330 psci_power_state_t *state_info, 331 plat_local_state_t *prev) 332 { 333 unsigned int lvl; 334 #ifdef PLAT_MAX_CPU_SUSPEND_PWR_LVL 335 unsigned int max_pwrlvl = PLAT_MAX_CPU_SUSPEND_PWR_LVL; 336 #else 337 unsigned int max_pwrlvl = PLAT_MAX_PWR_LVL; 338 #endif 339 plat_local_state_t req_state; 340 341 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= max_pwrlvl; lvl++) { 342 /* Save the previous requested local power state */ 343 prev[lvl - 1U] = *psci_get_req_local_pwr_states(lvl, cpu_idx); 344 345 /* Update the new requested local power state */ 346 if (lvl <= end_pwrlvl) { 347 req_state = state_info->pwr_domain_state[lvl]; 348 } else { 349 req_state = state_info->pwr_domain_state[end_pwrlvl]; 350 } 351 psci_set_req_local_pwr_state(lvl, cpu_idx, req_state); 352 } 353 } 354 355 /****************************************************************************** 356 * Helper function to restore the previously saved requested local power states 357 * (prev) for a CPU (cpu_idx) to psci_req_local_pwr_states. 358 *****************************************************************************/ 359 void psci_restore_req_local_pwr_states(unsigned int cpu_idx, 360 plat_local_state_t *prev) 361 { 362 unsigned int lvl; 363 #ifdef PLAT_MAX_CPU_SUSPEND_PWR_LVL 364 unsigned int max_pwrlvl = PLAT_MAX_CPU_SUSPEND_PWR_LVL; 365 #else 366 unsigned int max_pwrlvl = PLAT_MAX_PWR_LVL; 367 #endif 368 369 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= max_pwrlvl; lvl++) { 370 /* Restore the previous requested local power state */ 371 psci_set_req_local_pwr_state(lvl, cpu_idx, prev[lvl - 1U]); 372 } 373 } 374 #endif 375 376 /* 377 * psci_non_cpu_pd_nodes can be placed either in normal memory or coherent 378 * memory. 379 * 380 * With !USE_COHERENT_MEM, psci_non_cpu_pd_nodes is placed in normal memory, 381 * it's accessed by both cached and non-cached participants. To serve the common 382 * minimum, perform a cache flush before read and after write so that non-cached 383 * participants operate on latest data in main memory. 384 * 385 * When USE_COHERENT_MEM is used, psci_non_cpu_pd_nodes is placed in coherent 386 * memory. With HW_ASSISTED_COHERENCY, all PSCI participants are cache-coherent. 387 * In both cases, no cache operations are required. 388 */ 389 390 /* 391 * Retrieve local state of non-CPU power domain node from a non-cached CPU, 392 * after any required cache maintenance operation. 393 */ 394 static plat_local_state_t get_non_cpu_pd_node_local_state( 395 unsigned int parent_idx) 396 { 397 #if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 398 flush_dcache_range( 399 (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx], 400 sizeof(psci_non_cpu_pd_nodes[parent_idx])); 401 #endif 402 return psci_non_cpu_pd_nodes[parent_idx].local_state; 403 } 404 405 /* 406 * Update local state of non-CPU power domain node from a cached CPU; perform 407 * any required cache maintenance operation afterwards. 408 */ 409 static void set_non_cpu_pd_node_local_state(unsigned int parent_idx, 410 plat_local_state_t state) 411 { 412 psci_non_cpu_pd_nodes[parent_idx].local_state = state; 413 #if !(USE_COHERENT_MEM || HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 414 flush_dcache_range( 415 (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx], 416 sizeof(psci_non_cpu_pd_nodes[parent_idx])); 417 #endif 418 } 419 420 /****************************************************************************** 421 * Helper function to return the current local power state of each power domain 422 * from the current cpu power domain to its ancestor at the 'end_pwrlvl'. This 423 * function will be called after a cpu is powered on to find the local state 424 * each power domain has emerged from. 425 *****************************************************************************/ 426 void psci_get_target_local_pwr_states(unsigned int cpu_idx, unsigned int end_pwrlvl, 427 psci_power_state_t *target_state) 428 { 429 unsigned int parent_idx, lvl; 430 plat_local_state_t *pd_state = target_state->pwr_domain_state; 431 432 pd_state[PSCI_CPU_PWR_LVL] = psci_get_cpu_local_state(); 433 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; 434 435 /* Copy the local power state from node to state_info */ 436 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { 437 pd_state[lvl] = get_non_cpu_pd_node_local_state(parent_idx); 438 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 439 } 440 441 /* Set the the higher levels to RUN */ 442 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) 443 target_state->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN; 444 } 445 446 /****************************************************************************** 447 * Helper function to set the target local power state that each power domain 448 * from the current cpu power domain to its ancestor at the 'end_pwrlvl' will 449 * enter. This function will be called after coordination of requested power 450 * states has been done for each power level. 451 *****************************************************************************/ 452 void psci_set_target_local_pwr_states(unsigned int cpu_idx, unsigned int end_pwrlvl, 453 const psci_power_state_t *target_state) 454 { 455 unsigned int parent_idx, lvl; 456 const plat_local_state_t *pd_state = target_state->pwr_domain_state; 457 458 psci_set_cpu_local_state(pd_state[PSCI_CPU_PWR_LVL]); 459 460 /* 461 * Need to flush as local_state might be accessed with Data Cache 462 * disabled during power on 463 */ 464 psci_flush_cpu_data(psci_svc_cpu_data.local_state); 465 466 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; 467 468 /* Copy the local_state from state_info */ 469 for (lvl = 1U; lvl <= end_pwrlvl; lvl++) { 470 set_non_cpu_pd_node_local_state(parent_idx, pd_state[lvl]); 471 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 472 } 473 } 474 475 /******************************************************************************* 476 * PSCI helper function to get the parent nodes corresponding to a cpu_index. 477 ******************************************************************************/ 478 void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx, 479 unsigned int end_lvl, 480 unsigned int *node_index) 481 { 482 unsigned int parent_node = psci_cpu_pd_nodes[cpu_idx].parent_node; 483 unsigned int i; 484 unsigned int *node = node_index; 485 486 for (i = PSCI_CPU_PWR_LVL + 1U; i <= end_lvl; i++) { 487 *node = parent_node; 488 node++; 489 parent_node = psci_non_cpu_pd_nodes[parent_node].parent_node; 490 } 491 } 492 493 /****************************************************************************** 494 * This function is invoked post CPU power up and initialization. It sets the 495 * affinity info state, target power state and requested power state for the 496 * current CPU and all its ancestor power domains to RUN. 497 *****************************************************************************/ 498 void psci_set_pwr_domains_to_run(unsigned int cpu_idx, unsigned int end_pwrlvl) 499 { 500 unsigned int parent_idx, lvl; 501 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; 502 503 /* Reset the local_state to RUN for the non cpu power domains. */ 504 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { 505 set_non_cpu_pd_node_local_state(parent_idx, 506 PSCI_LOCAL_STATE_RUN); 507 psci_set_req_local_pwr_state(lvl, 508 cpu_idx, 509 PSCI_LOCAL_STATE_RUN); 510 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 511 } 512 513 /* Set the affinity info state to ON */ 514 psci_set_aff_info_state(AFF_STATE_ON); 515 516 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN); 517 psci_flush_cpu_data(psci_svc_cpu_data); 518 } 519 520 /****************************************************************************** 521 * This function is used in platform-coordinated mode. 522 * 523 * This function is passed the local power states requested for each power 524 * domain (state_info) between the current CPU domain and its ancestors until 525 * the target power level (end_pwrlvl). It updates the array of requested power 526 * states with this information. 527 * 528 * Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it 529 * retrieves the states requested by all the cpus of which the power domain at 530 * that level is an ancestor. It passes this information to the platform to 531 * coordinate and return the target power state. If the target state for a level 532 * is RUN then subsequent levels are not considered. At the CPU level, state 533 * coordination is not required. Hence, the requested and the target states are 534 * the same. 535 * 536 * The 'state_info' is updated with the target state for each level between the 537 * CPU and the 'end_pwrlvl' and returned to the caller. 538 * 539 * This function will only be invoked with data cache enabled and while 540 * powering down a core. 541 *****************************************************************************/ 542 void psci_do_state_coordination(unsigned int cpu_idx, unsigned int end_pwrlvl, 543 psci_power_state_t *state_info) 544 { 545 unsigned int lvl, parent_idx; 546 unsigned int start_idx; 547 unsigned int ncpus; 548 plat_local_state_t target_state, *req_states; 549 550 assert(end_pwrlvl <= PLAT_MAX_PWR_LVL); 551 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; 552 553 /* For level 0, the requested state will be equivalent 554 to target state */ 555 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { 556 557 /* First update the requested power state */ 558 psci_set_req_local_pwr_state(lvl, cpu_idx, 559 state_info->pwr_domain_state[lvl]); 560 561 /* Get the requested power states for this power level */ 562 start_idx = psci_non_cpu_pd_nodes[parent_idx].cpu_start_idx; 563 req_states = psci_get_req_local_pwr_states(lvl, start_idx); 564 565 /* 566 * Let the platform coordinate amongst the requested states at 567 * this power level and return the target local power state. 568 */ 569 ncpus = psci_non_cpu_pd_nodes[parent_idx].ncpus; 570 target_state = plat_get_target_pwr_state(lvl, 571 req_states, 572 ncpus); 573 574 state_info->pwr_domain_state[lvl] = target_state; 575 576 /* Break early if the negotiated target power state is RUN */ 577 if (is_local_state_run(state_info->pwr_domain_state[lvl]) != 0) 578 break; 579 580 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 581 } 582 583 /* 584 * This is for cases when we break out of the above loop early because 585 * the target power state is RUN at a power level < end_pwlvl. 586 * We update the requested power state from state_info and then 587 * set the target state as RUN. 588 */ 589 for (lvl = lvl + 1U; lvl <= end_pwrlvl; lvl++) { 590 psci_set_req_local_pwr_state(lvl, cpu_idx, 591 state_info->pwr_domain_state[lvl]); 592 state_info->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN; 593 594 } 595 } 596 597 #if PSCI_OS_INIT_MODE 598 /****************************************************************************** 599 * This function is used in OS-initiated mode. 600 * 601 * This function is passed the local power states requested for each power 602 * domain (state_info) between the current CPU domain and its ancestors until 603 * the target power level (end_pwrlvl), and ensures the requested power states 604 * are valid. It updates the array of requested power states with this 605 * information. 606 * 607 * Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it 608 * retrieves the states requested by all the cpus of which the power domain at 609 * that level is an ancestor. It passes this information to the platform to 610 * coordinate and return the target power state. If the requested state does 611 * not match the target state, the request is denied. 612 * 613 * The 'state_info' is not modified. 614 * 615 * This function will only be invoked with data cache enabled and while 616 * powering down a core. 617 *****************************************************************************/ 618 int psci_validate_state_coordination(unsigned int cpu_idx, unsigned int end_pwrlvl, 619 psci_power_state_t *state_info) 620 { 621 int rc = PSCI_E_SUCCESS; 622 unsigned int lvl, parent_idx; 623 unsigned int start_idx; 624 unsigned int ncpus; 625 plat_local_state_t target_state, *req_states; 626 plat_local_state_t prev[PLAT_MAX_PWR_LVL]; 627 628 assert(end_pwrlvl <= PLAT_MAX_PWR_LVL); 629 parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; 630 631 /* 632 * Save a copy of the previous requested local power states and update 633 * the new requested local power states. 634 */ 635 psci_update_req_local_pwr_states(end_pwrlvl, cpu_idx, state_info, prev); 636 637 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { 638 /* Get the requested power states for this power level */ 639 start_idx = psci_non_cpu_pd_nodes[parent_idx].cpu_start_idx; 640 req_states = psci_get_req_local_pwr_states(lvl, start_idx); 641 642 /* 643 * Let the platform coordinate amongst the requested states at 644 * this power level and return the target local power state. 645 */ 646 ncpus = psci_non_cpu_pd_nodes[parent_idx].ncpus; 647 target_state = plat_get_target_pwr_state(lvl, 648 req_states, 649 ncpus); 650 651 /* 652 * Verify that the requested power state matches the target 653 * local power state. 654 */ 655 if (state_info->pwr_domain_state[lvl] != target_state) { 656 if (target_state == PSCI_LOCAL_STATE_RUN) { 657 rc = PSCI_E_DENIED; 658 } else { 659 rc = PSCI_E_INVALID_PARAMS; 660 } 661 goto exit; 662 } 663 664 parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; 665 } 666 667 /* 668 * Verify that the current core is the last running core at the 669 * specified power level. 670 */ 671 lvl = state_info->last_at_pwrlvl; 672 if (!psci_is_last_cpu_to_idle_at_pwrlvl(cpu_idx, lvl)) { 673 rc = PSCI_E_DENIED; 674 } 675 676 exit: 677 if (rc != PSCI_E_SUCCESS) { 678 /* Restore the previous requested local power states. */ 679 psci_restore_req_local_pwr_states(cpu_idx, prev); 680 return rc; 681 } 682 683 return rc; 684 } 685 #endif 686 687 /****************************************************************************** 688 * This function validates a suspend request by making sure that if a standby 689 * state is requested then no power level is turned off and the highest power 690 * level is placed in a standby/retention state. 691 * 692 * It also ensures that the state level X will enter is not shallower than the 693 * state level X + 1 will enter. 694 * 695 * This validation will be enabled only for DEBUG builds as the platform is 696 * expected to perform these validations as well. 697 *****************************************************************************/ 698 int psci_validate_suspend_req(const psci_power_state_t *state_info, 699 unsigned int is_power_down_state) 700 { 701 unsigned int max_off_lvl, target_lvl, max_retn_lvl; 702 plat_local_state_t state; 703 plat_local_state_type_t req_state_type, deepest_state_type; 704 int i; 705 706 /* Find the target suspend power level */ 707 target_lvl = psci_find_target_suspend_lvl(state_info); 708 if (target_lvl == PSCI_INVALID_PWR_LVL) 709 return PSCI_E_INVALID_PARAMS; 710 711 /* All power domain levels are in a RUN state to begin with */ 712 deepest_state_type = STATE_TYPE_RUN; 713 714 for (i = (int) target_lvl; i >= (int) PSCI_CPU_PWR_LVL; i--) { 715 state = state_info->pwr_domain_state[i]; 716 req_state_type = find_local_state_type(state); 717 718 /* 719 * While traversing from the highest power level to the lowest, 720 * the state requested for lower levels has to be the same or 721 * deeper i.e. equal to or greater than the state at the higher 722 * levels. If this condition is true, then the requested state 723 * becomes the deepest state encountered so far. 724 */ 725 if (req_state_type < deepest_state_type) 726 return PSCI_E_INVALID_PARAMS; 727 deepest_state_type = req_state_type; 728 } 729 730 /* Find the highest off power level */ 731 max_off_lvl = psci_find_max_off_lvl(state_info); 732 733 /* The target_lvl is either equal to the max_off_lvl or max_retn_lvl */ 734 max_retn_lvl = PSCI_INVALID_PWR_LVL; 735 if (target_lvl != max_off_lvl) 736 max_retn_lvl = target_lvl; 737 738 /* 739 * If this is not a request for a power down state then max off level 740 * has to be invalid and max retention level has to be a valid power 741 * level. 742 */ 743 if ((is_power_down_state == 0U) && 744 ((max_off_lvl != PSCI_INVALID_PWR_LVL) || 745 (max_retn_lvl == PSCI_INVALID_PWR_LVL))) 746 return PSCI_E_INVALID_PARAMS; 747 748 return PSCI_E_SUCCESS; 749 } 750 751 /****************************************************************************** 752 * This function finds the highest power level which will be powered down 753 * amongst all the power levels specified in the 'state_info' structure 754 *****************************************************************************/ 755 unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info) 756 { 757 int i; 758 759 for (i = (int) PLAT_MAX_PWR_LVL; i >= (int) PSCI_CPU_PWR_LVL; i--) { 760 if (is_local_state_off(state_info->pwr_domain_state[i]) != 0) 761 return (unsigned int) i; 762 } 763 764 return PSCI_INVALID_PWR_LVL; 765 } 766 767 /****************************************************************************** 768 * This functions finds the level of the highest power domain which will be 769 * placed in a low power state during a suspend operation. 770 *****************************************************************************/ 771 unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info) 772 { 773 int i; 774 775 for (i = (int) PLAT_MAX_PWR_LVL; i >= (int) PSCI_CPU_PWR_LVL; i--) { 776 if (is_local_state_run(state_info->pwr_domain_state[i]) == 0) 777 return (unsigned int) i; 778 } 779 780 return PSCI_INVALID_PWR_LVL; 781 } 782 783 /******************************************************************************* 784 * This function is passed the highest level in the topology tree that the 785 * operation should be applied to and a list of node indexes. It picks up locks 786 * from the node index list in order of increasing power domain level in the 787 * range specified. 788 ******************************************************************************/ 789 void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, 790 const unsigned int *parent_nodes) 791 { 792 unsigned int parent_idx; 793 unsigned int level; 794 795 /* No locking required for level 0. Hence start locking from level 1 */ 796 for (level = PSCI_CPU_PWR_LVL + 1U; level <= end_pwrlvl; level++) { 797 parent_idx = parent_nodes[level - 1U]; 798 psci_lock_get(&psci_non_cpu_pd_nodes[parent_idx]); 799 } 800 } 801 802 /******************************************************************************* 803 * This function is passed the highest level in the topology tree that the 804 * operation should be applied to and a list of node indexes. It releases the 805 * locks in order of decreasing power domain level in the range specified. 806 ******************************************************************************/ 807 void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, 808 const unsigned int *parent_nodes) 809 { 810 unsigned int parent_idx; 811 unsigned int level; 812 813 /* Unlock top down. No unlocking required for level 0. */ 814 for (level = end_pwrlvl; level >= (PSCI_CPU_PWR_LVL + 1U); level--) { 815 parent_idx = parent_nodes[level - 1U]; 816 psci_lock_release(&psci_non_cpu_pd_nodes[parent_idx]); 817 } 818 } 819 820 /******************************************************************************* 821 * This function determines the full entrypoint information for the requested 822 * PSCI entrypoint on power on/resume and returns it. 823 ******************************************************************************/ 824 #ifdef __aarch64__ 825 static int psci_get_ns_ep_info(entry_point_info_t *ep, 826 uintptr_t entrypoint, 827 u_register_t context_id) 828 { 829 u_register_t ep_attr, sctlr; 830 unsigned int daif, ee, mode; 831 u_register_t ns_scr_el3 = read_scr_el3(); 832 u_register_t ns_sctlr_el1 = read_sctlr_el1(); 833 834 sctlr = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ? 835 read_sctlr_el2() : ns_sctlr_el1; 836 ee = 0; 837 838 ep_attr = NON_SECURE | EP_ST_DISABLE; 839 if ((sctlr & SCTLR_EE_BIT) != 0U) { 840 ep_attr |= EP_EE_BIG; 841 ee = 1; 842 } 843 SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr); 844 845 ep->pc = entrypoint; 846 zeromem(&ep->args, sizeof(ep->args)); 847 ep->args.arg0 = context_id; 848 849 /* 850 * Figure out whether the cpu enters the non-secure address space 851 * in aarch32 or aarch64 852 */ 853 if ((ns_scr_el3 & SCR_RW_BIT) != 0U) { 854 855 /* 856 * Check whether a Thumb entry point has been provided for an 857 * aarch64 EL 858 */ 859 if ((entrypoint & 0x1UL) != 0UL) 860 return PSCI_E_INVALID_ADDRESS; 861 862 mode = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ? MODE_EL2 : MODE_EL1; 863 864 ep->spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, 865 DISABLE_ALL_EXCEPTIONS); 866 } else { 867 868 mode = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ? 869 MODE32_hyp : MODE32_svc; 870 871 /* 872 * TODO: Choose async. exception bits if HYP mode is not 873 * implemented according to the values of SCR.{AW, FW} bits 874 */ 875 daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT; 876 877 ep->spsr = SPSR_MODE32((uint64_t)mode, entrypoint & 0x1, ee, 878 daif); 879 } 880 881 return PSCI_E_SUCCESS; 882 } 883 #else /* !__aarch64__ */ 884 static int psci_get_ns_ep_info(entry_point_info_t *ep, 885 uintptr_t entrypoint, 886 u_register_t context_id) 887 { 888 u_register_t ep_attr; 889 unsigned int aif, ee, mode; 890 u_register_t scr = read_scr(); 891 u_register_t ns_sctlr, sctlr; 892 893 /* Switch to non secure state */ 894 write_scr(scr | SCR_NS_BIT); 895 isb(); 896 ns_sctlr = read_sctlr(); 897 898 sctlr = scr & SCR_HCE_BIT ? read_hsctlr() : ns_sctlr; 899 900 /* Return to original state */ 901 write_scr(scr); 902 isb(); 903 ee = 0; 904 905 ep_attr = NON_SECURE | EP_ST_DISABLE; 906 if (sctlr & SCTLR_EE_BIT) { 907 ep_attr |= EP_EE_BIG; 908 ee = 1; 909 } 910 SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr); 911 912 ep->pc = entrypoint; 913 zeromem(&ep->args, sizeof(ep->args)); 914 ep->args.arg0 = context_id; 915 916 mode = scr & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc; 917 918 /* 919 * TODO: Choose async. exception bits if HYP mode is not 920 * implemented according to the values of SCR.{AW, FW} bits 921 */ 922 aif = SPSR_ABT_BIT | SPSR_IRQ_BIT | SPSR_FIQ_BIT; 923 924 ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, aif); 925 926 return PSCI_E_SUCCESS; 927 } 928 929 #endif /* __aarch64__ */ 930 931 /******************************************************************************* 932 * This function validates the entrypoint with the platform layer if the 933 * appropriate pm_ops hook is exported by the platform and returns the 934 * 'entry_point_info'. 935 ******************************************************************************/ 936 int psci_validate_entry_point(entry_point_info_t *ep, 937 uintptr_t entrypoint, 938 u_register_t context_id) 939 { 940 int rc; 941 942 /* Validate the entrypoint using platform psci_ops */ 943 if (psci_plat_pm_ops->validate_ns_entrypoint != NULL) { 944 rc = psci_plat_pm_ops->validate_ns_entrypoint(entrypoint); 945 if (rc != PSCI_E_SUCCESS) 946 return PSCI_E_INVALID_ADDRESS; 947 } 948 949 /* 950 * Verify and derive the re-entry information for 951 * the non-secure world from the non-secure state from 952 * where this call originated. 953 */ 954 rc = psci_get_ns_ep_info(ep, entrypoint, context_id); 955 return rc; 956 } 957 958 /******************************************************************************* 959 * Generic handler which is called when a cpu is physically powered on. It 960 * traverses the node information and finds the highest power level powered 961 * off and performs generic, architectural, platform setup and state management 962 * to power on that power level and power levels below it. 963 * e.g. For a cpu that's been powered on, it will call the platform specific 964 * code to enable the gic cpu interface and for a cluster it will enable 965 * coherency at the interconnect level in addition to gic cpu interface. 966 ******************************************************************************/ 967 void psci_warmboot_entrypoint(void) 968 { 969 unsigned int end_pwrlvl; 970 unsigned int cpu_idx = plat_my_core_pos(); 971 unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; 972 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; 973 974 /* Init registers that never change for the lifetime of TF-A */ 975 cm_manage_extensions_el3(); 976 977 /* 978 * Verify that we have been explicitly turned ON or resumed from 979 * suspend. 980 */ 981 if (psci_get_aff_info_state() == AFF_STATE_OFF) { 982 ERROR("Unexpected affinity info state.\n"); 983 panic(); 984 } 985 986 /* 987 * Get the maximum power domain level to traverse to after this cpu 988 * has been physically powered up. 989 */ 990 end_pwrlvl = get_power_on_target_pwrlvl(); 991 992 /* Get the parent nodes */ 993 psci_get_parent_pwr_domain_nodes(cpu_idx, end_pwrlvl, parent_nodes); 994 995 /* 996 * This function acquires the lock corresponding to each power level so 997 * that by the time all locks are taken, the system topology is snapshot 998 * and state management can be done safely. 999 */ 1000 psci_acquire_pwr_domain_locks(end_pwrlvl, parent_nodes); 1001 1002 psci_get_target_local_pwr_states(cpu_idx, end_pwrlvl, &state_info); 1003 1004 #if ENABLE_PSCI_STAT 1005 plat_psci_stat_accounting_stop(&state_info); 1006 #endif 1007 1008 /* 1009 * This CPU could be resuming from suspend or it could have just been 1010 * turned on. To distinguish between these 2 cases, we examine the 1011 * affinity state of the CPU: 1012 * - If the affinity state is ON_PENDING then it has just been 1013 * turned on. 1014 * - Else it is resuming from suspend. 1015 * 1016 * Depending on the type of warm reset identified, choose the right set 1017 * of power management handler and perform the generic, architecture 1018 * and platform specific handling. 1019 */ 1020 if (psci_get_aff_info_state() == AFF_STATE_ON_PENDING) 1021 psci_cpu_on_finish(cpu_idx, &state_info); 1022 else 1023 psci_cpu_suspend_to_powerdown_finish(cpu_idx, &state_info); 1024 1025 /* 1026 * Generic management: Now we just need to retrieve the 1027 * information that we had stashed away during the cpu_on 1028 * call to set this cpu on its way. 1029 */ 1030 cm_prepare_el3_exit_ns(); 1031 1032 /* 1033 * Set the requested and target state of this CPU and all the higher 1034 * power domains which are ancestors of this CPU to run. 1035 */ 1036 psci_set_pwr_domains_to_run(cpu_idx, end_pwrlvl); 1037 1038 #if ENABLE_PSCI_STAT 1039 psci_stats_update_pwr_up(cpu_idx, end_pwrlvl, &state_info); 1040 #endif 1041 1042 /* 1043 * This loop releases the lock corresponding to each power level 1044 * in the reverse order to which they were acquired. 1045 */ 1046 psci_release_pwr_domain_locks(end_pwrlvl, parent_nodes); 1047 } 1048 1049 /******************************************************************************* 1050 * This function initializes the set of hooks that PSCI invokes as part of power 1051 * management operation. The power management hooks are expected to be provided 1052 * by the SPD, after it finishes all its initialization 1053 ******************************************************************************/ 1054 void psci_register_spd_pm_hook(const spd_pm_ops_t *pm) 1055 { 1056 assert(pm != NULL); 1057 psci_spd_pm = pm; 1058 1059 if (pm->svc_migrate != NULL) 1060 psci_caps |= define_psci_cap(PSCI_MIG_AARCH64); 1061 1062 if (pm->svc_migrate_info != NULL) 1063 psci_caps |= define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64) 1064 | define_psci_cap(PSCI_MIG_INFO_TYPE); 1065 } 1066 1067 /******************************************************************************* 1068 * This function invokes the migrate info hook in the spd_pm_ops. It performs 1069 * the necessary return value validation. If the Secure Payload is UP and 1070 * migrate capable, it returns the mpidr of the CPU on which the Secure payload 1071 * is resident through the mpidr parameter. Else the value of the parameter on 1072 * return is undefined. 1073 ******************************************************************************/ 1074 int psci_spd_migrate_info(u_register_t *mpidr) 1075 { 1076 int rc; 1077 1078 if ((psci_spd_pm == NULL) || (psci_spd_pm->svc_migrate_info == NULL)) 1079 return PSCI_E_NOT_SUPPORTED; 1080 1081 rc = psci_spd_pm->svc_migrate_info(mpidr); 1082 1083 assert((rc == PSCI_TOS_UP_MIG_CAP) || (rc == PSCI_TOS_NOT_UP_MIG_CAP) || 1084 (rc == PSCI_TOS_NOT_PRESENT_MP) || (rc == PSCI_E_NOT_SUPPORTED)); 1085 1086 return rc; 1087 } 1088 1089 1090 /******************************************************************************* 1091 * This function prints the state of all power domains present in the 1092 * system 1093 ******************************************************************************/ 1094 void psci_print_power_domain_map(void) 1095 { 1096 #if LOG_LEVEL >= LOG_LEVEL_INFO 1097 unsigned int idx; 1098 plat_local_state_t state; 1099 plat_local_state_type_t state_type; 1100 1101 /* This array maps to the PSCI_STATE_X definitions in psci.h */ 1102 static const char * const psci_state_type_str[] = { 1103 "ON", 1104 "RETENTION", 1105 "OFF", 1106 }; 1107 1108 INFO("PSCI Power Domain Map:\n"); 1109 for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - psci_plat_core_count); 1110 idx++) { 1111 state_type = find_local_state_type( 1112 psci_non_cpu_pd_nodes[idx].local_state); 1113 INFO(" Domain Node : Level %u, parent_node %u," 1114 " State %s (0x%x)\n", 1115 psci_non_cpu_pd_nodes[idx].level, 1116 psci_non_cpu_pd_nodes[idx].parent_node, 1117 psci_state_type_str[state_type], 1118 psci_non_cpu_pd_nodes[idx].local_state); 1119 } 1120 1121 for (idx = 0; idx < psci_plat_core_count; idx++) { 1122 state = psci_get_cpu_local_state_by_idx(idx); 1123 state_type = find_local_state_type(state); 1124 INFO(" CPU Node : MPID 0x%llx, parent_node %u," 1125 " State %s (0x%x)\n", 1126 (unsigned long long)psci_cpu_pd_nodes[idx].mpidr, 1127 psci_cpu_pd_nodes[idx].parent_node, 1128 psci_state_type_str[state_type], 1129 psci_get_cpu_local_state_by_idx(idx)); 1130 } 1131 #endif 1132 } 1133 1134 /****************************************************************************** 1135 * Return whether any secondaries were powered up with CPU_ON call. A CPU that 1136 * have ever been powered up would have set its MPDIR value to something other 1137 * than PSCI_INVALID_MPIDR. Note that MPDIR isn't reset back to 1138 * PSCI_INVALID_MPIDR when a CPU is powered down later, so the return value is 1139 * meaningful only when called on the primary CPU during early boot. 1140 *****************************************************************************/ 1141 int psci_secondaries_brought_up(void) 1142 { 1143 unsigned int idx, n_valid = 0U; 1144 1145 for (idx = 0U; idx < ARRAY_SIZE(psci_cpu_pd_nodes); idx++) { 1146 if (psci_cpu_pd_nodes[idx].mpidr != PSCI_INVALID_MPIDR) 1147 n_valid++; 1148 } 1149 1150 assert(n_valid > 0U); 1151 1152 return (n_valid > 1U) ? 1 : 0; 1153 } 1154 1155 /******************************************************************************* 1156 * Initiate power down sequence, by calling power down operations registered for 1157 * this CPU. 1158 ******************************************************************************/ 1159 void psci_pwrdown_cpu(unsigned int power_level) 1160 { 1161 #if ENABLE_RUNTIME_INSTRUMENTATION 1162 1163 /* 1164 * Flush cache line so that even if CPU power down happens 1165 * the timestamp update is reflected in memory. 1166 */ 1167 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 1168 RT_INSTR_ENTER_CFLUSH, 1169 PMF_CACHE_MAINT); 1170 #endif 1171 1172 #if HW_ASSISTED_COHERENCY 1173 /* 1174 * With hardware-assisted coherency, the CPU drivers only initiate the 1175 * power down sequence, without performing cache-maintenance operations 1176 * in software. Data caches enabled both before and after this call. 1177 */ 1178 prepare_cpu_pwr_dwn(power_level); 1179 #else 1180 /* 1181 * Without hardware-assisted coherency, the CPU drivers disable data 1182 * caches, then perform cache-maintenance operations in software. 1183 * 1184 * This also calls prepare_cpu_pwr_dwn() to initiate power down 1185 * sequence, but that function will return with data caches disabled. 1186 * We must ensure that the stack memory is flushed out to memory before 1187 * we start popping from it again. 1188 */ 1189 psci_do_pwrdown_cache_maintenance(power_level); 1190 #endif 1191 1192 #if ENABLE_RUNTIME_INSTRUMENTATION 1193 PMF_CAPTURE_TIMESTAMP(rt_instr_svc, 1194 RT_INSTR_EXIT_CFLUSH, 1195 PMF_NO_CACHE_MAINT); 1196 #endif 1197 } 1198 1199 /******************************************************************************* 1200 * This function invokes the callback 'stop_func()' with the 'mpidr' of each 1201 * online PE. Caller can pass suitable method to stop a remote core. 1202 * 1203 * 'wait_ms' is the timeout value in milliseconds for the other cores to 1204 * transition to power down state. Passing '0' makes it non-blocking. 1205 * 1206 * The function returns 'PSCI_E_DENIED' if some cores failed to stop within the 1207 * given timeout. 1208 ******************************************************************************/ 1209 int psci_stop_other_cores(unsigned int this_cpu_idx, unsigned int wait_ms, 1210 void (*stop_func)(u_register_t mpidr)) 1211 { 1212 /* Invoke stop_func for each core */ 1213 for (unsigned int idx = 0U; idx < psci_plat_core_count; idx++) { 1214 /* skip current CPU */ 1215 if (idx == this_cpu_idx) { 1216 continue; 1217 } 1218 1219 /* Check if the CPU is ON */ 1220 if (psci_get_aff_info_state_by_idx(idx) == AFF_STATE_ON) { 1221 (*stop_func)(psci_cpu_pd_nodes[idx].mpidr); 1222 } 1223 } 1224 1225 /* Need to wait for other cores to shutdown */ 1226 if (wait_ms != 0U) { 1227 while ((wait_ms-- != 0U) && (!psci_is_last_on_cpu(this_cpu_idx))) { 1228 mdelay(1U); 1229 } 1230 1231 if (!psci_is_last_on_cpu(this_cpu_idx)) { 1232 WARN("Failed to stop all cores!\n"); 1233 psci_print_power_domain_map(); 1234 return PSCI_E_DENIED; 1235 } 1236 } 1237 1238 return PSCI_E_SUCCESS; 1239 } 1240 1241 /******************************************************************************* 1242 * This function verifies that all the other cores in the system have been 1243 * turned OFF and the current CPU is the last running CPU in the system. 1244 * Returns true if the current CPU is the last ON CPU or false otherwise. 1245 * 1246 * This API has following differences with psci_is_last_on_cpu 1247 * 1. PSCI states are locked 1248 ******************************************************************************/ 1249 bool psci_is_last_on_cpu_safe(unsigned int this_core) 1250 { 1251 unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; 1252 1253 psci_get_parent_pwr_domain_nodes(this_core, PLAT_MAX_PWR_LVL, parent_nodes); 1254 1255 psci_acquire_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes); 1256 1257 if (!psci_is_last_on_cpu(this_core)) { 1258 psci_release_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes); 1259 return false; 1260 } 1261 1262 psci_release_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes); 1263 1264 return true; 1265 } 1266 1267 /******************************************************************************* 1268 * This function verifies that all cores in the system have been turned ON. 1269 * Returns true, if all CPUs are ON or false otherwise. 1270 * 1271 * This API has following differences with psci_are_all_cpus_on 1272 * 1. PSCI states are locked 1273 ******************************************************************************/ 1274 bool psci_are_all_cpus_on_safe(unsigned int this_core) 1275 { 1276 unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; 1277 1278 psci_get_parent_pwr_domain_nodes(this_core, PLAT_MAX_PWR_LVL, parent_nodes); 1279 1280 psci_acquire_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes); 1281 1282 if (!psci_are_all_cpus_on()) { 1283 psci_release_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes); 1284 return false; 1285 } 1286 1287 psci_release_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes); 1288 1289 return true; 1290 } 1291