1 /* 2 * Copyright (c) 2024, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <plat/common/common_def.h> 12 13 #include <arch_def.h> 14 15 #define PLAT_PRIMARY_CPU (0x0) 16 17 #define MT_GIC_BASE (0x0C400000) 18 #define MCUCFG_BASE (0x0C000000) 19 #define MCUCFG_REG_SIZE (0x50000) 20 #define IO_PHYS (0x10000000) 21 22 /* Aggregate of all devices for MMU mapping */ 23 #define MTK_DEV_RNG1_BASE (IO_PHYS) 24 #define MTK_DEV_RNG1_SIZE (0x10000000) 25 26 #define TOPCKGEN_BASE (IO_PHYS) 27 28 /******************************************************************************* 29 * AUDIO related constants 30 ******************************************************************************/ 31 #define AUDIO_BASE (IO_PHYS + 0x0a110000) 32 33 /******************************************************************************* 34 * APUSYS related constants 35 ******************************************************************************/ 36 #define APUSYS_BASE (IO_PHYS + 0x09000000) 37 #define APU_MD32_SYSCTRL (IO_PHYS + 0x09001000) 38 #define APU_MD32_WDT (IO_PHYS + 0x09002000) 39 #define APU_LOGTOP (IO_PHYS + 0x09024000) 40 #define APUSYS_CTRL_DAPC_RCX_BASE (IO_PHYS + 0x09030000) 41 #define APU_REVISER (IO_PHYS + 0x0903C000) 42 #define APU_RCX_UPRV_TCU (IO_PHYS + 0x09060000) 43 #define APU_RCX_EXTM_TCU (IO_PHYS + 0x09061000) 44 #define APU_CMU_TOP (IO_PHYS + 0x09067000) 45 #define APUSYS_CE_BASE (IO_PHYS + 0x090B0000) 46 #define APU_ARE_REG_BASE (IO_PHYS + 0x090B0000) 47 #define APU_RCX_VCORE_CONFIG (IO_PHYS + 0x090E0000) 48 #define APU_AO_CTRL (IO_PHYS + 0x090F2000) 49 #define APU_SEC_CON (IO_PHYS + 0x090F5000) 50 #define APUSYS_CTRL_DAPC_AO_BASE (IO_PHYS + 0x090FC000) 51 52 #define APU_MBOX0 (0x4C200000) 53 #define APU_MD32_TCM (0x4D000000) 54 55 #define APU_MD32_TCM_SZ (0x50000) 56 #define APU_MBOX0_SZ (0x100000) 57 #define APU_INFRA_BASE (0x1002C000) 58 #define APU_INFRA_SZ (0x1000) 59 60 #define APU_RESERVE_MEMORY (0x95000000) 61 #define APU_SEC_INFO_OFFSET (0x100000) 62 #define APU_RESERVE_SIZE (0x1400000) 63 64 /******************************************************************************* 65 * SPM related constants 66 ******************************************************************************/ 67 #define SPM_BASE (IO_PHYS + 0x0C004000) 68 69 /******************************************************************************* 70 * GPIO related constants 71 ******************************************************************************/ 72 #define GPIO_BASE (IO_PHYS + 0x0002D000) 73 #define RGU_BASE (IO_PHYS + 0x0C00B000) 74 #define DRM_BASE (IO_PHYS + 0x0000D000) 75 #define IOCFG_RT_BASE (IO_PHYS + 0x02000000) 76 #define IOCFG_RM1_BASE (IO_PHYS + 0x02020000) 77 #define IOCFG_RM2_BASE (IO_PHYS + 0x02040000) 78 #define IOCFG_RB_BASE (IO_PHYS + 0x02060000) 79 #define IOCFG_BM1_BASE (IO_PHYS + 0x02820000) 80 #define IOCFG_BM2_BASE (IO_PHYS + 0x02840000) 81 #define IOCFG_BM3_BASE (IO_PHYS + 0x02860000) 82 #define IOCFG_LT_BASE (IO_PHYS + 0x03000000) 83 #define IOCFG_LM1_BASE (IO_PHYS + 0x03020000) 84 #define IOCFG_LM2_BASE (IO_PHYS + 0x03040000) 85 #define IOCFG_LB1_BASE (IO_PHYS + 0x030f0000) 86 #define IOCFG_LB2_BASE (IO_PHYS + 0x03110000) 87 #define IOCFG_TM1_BASE (IO_PHYS + 0x03800000) 88 #define IOCFG_TM2_BASE (IO_PHYS + 0x03820000) 89 #define IOCFG_TM3_BASE (IO_PHYS + 0x03860000) 90 91 /******************************************************************************* 92 * UART related constants 93 ******************************************************************************/ 94 #define UART0_BASE (IO_PHYS + 0x06000000) 95 #define UART_BAUDRATE (115200) 96 97 /******************************************************************************* 98 * Infra IOMMU related constants 99 ******************************************************************************/ 100 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) 101 #define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00404000) 102 #define PERICFG_AO_BASE (IO_PHYS + 0x06630000) 103 #define PERICFG_AO_REG_SIZE (0x1000) 104 105 /******************************************************************************* 106 * GIC-600 & interrupt handling related constants 107 ******************************************************************************/ 108 /* Base MTK_platform compatible GIC memory map */ 109 #define BASE_GICD_BASE (MT_GIC_BASE) 110 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 111 #define MTK_GIC_REG_SIZE 0x400000 112 #define SGI_MASK 0xffff 113 #define DEV_IRQ_ID 982 114 115 #define PLATFORM_G1S_PROPS(grp) \ 116 INTR_PROP_DESC(DEV_IRQ_ID, GIC_HIGHEST_SEC_PRIORITY, grp, \ 117 GIC_INTR_CFG_LEVEL) 118 119 /******************************************************************************* 120 * MM IOMMU & SMI related constants 121 ******************************************************************************/ 122 #define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000) 123 #define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000) 124 #define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000) 125 #define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000) 126 #define SMI_LARB_4_BASE (IO_PHYS + 0x04013000) 127 #define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000) 128 #define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000) 129 #define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000) 130 #define SMI_LARB_9_BASE (IO_PHYS + 0x05001000) 131 #define SMI_LARB_10_BASE (IO_PHYS + 0x05120000) 132 #define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000) 133 #define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000) 134 #define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000) 135 #define SMI_LARB_12_BASE (IO_PHYS + 0x05340000) 136 #define SMI_LARB_13_BASE (IO_PHYS + 0x06001000) 137 #define SMI_LARB_14_BASE (IO_PHYS + 0x06002000) 138 #define SMI_LARB_15_BASE (IO_PHYS + 0x05140000) 139 #define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000) 140 #define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000) 141 #define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000) 142 #define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000) 143 #define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000) 144 #define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000) 145 #define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000) 146 #define SMI_LARB_27_BASE (IO_PHYS + 0x07201000) 147 #define SMI_LARB_28_BASE (IO_PHYS + 0x00000000) 148 #define SMI_LARB_REG_RNG_SIZE (0x1000) 149 150 /******************************************************************************* 151 * APMIXEDSYS related constants 152 ******************************************************************************/ 153 #define APMIXEDSYS (IO_PHYS + 0x0000C000) 154 155 /******************************************************************************* 156 * VPPSYS related constants 157 ******************************************************************************/ 158 #define VPPSYS0_BASE (IO_PHYS + 0x04000000) 159 #define VPPSYS1_BASE (IO_PHYS + 0x04f00000) 160 161 /******************************************************************************* 162 * VDOSYS related constants 163 ******************************************************************************/ 164 #define VDOSYS0_BASE (IO_PHYS + 0x0C01D000) 165 #define VDOSYS1_BASE (IO_PHYS + 0x0C100000) 166 167 /******************************************************************************* 168 * DP related constants 169 ******************************************************************************/ 170 #define EDP_SEC_BASE (IO_PHYS + 0x2EC50000) 171 #define DP_SEC_BASE (IO_PHYS + 0x2EC10000) 172 #define EDP_SEC_SIZE (0x1000) 173 #define DP_SEC_SIZE (0x1000) 174 175 /******************************************************************************* 176 * EMI MPU related constants 177 *******************************************************************************/ 178 #define EMI_MPU_BASE (IO_PHYS + 0x00428000) 179 #define SUB_EMI_MPU_BASE (IO_PHYS + 0x00528000) 180 #define EMI_SLB_BASE (IO_PHYS + 0x0042e000) 181 #define SUB_EMI_SLB_BASE (IO_PHYS + 0x0052e000) 182 #define CHN0_EMI_APB_BASE (IO_PHYS + 0x00201000) 183 #define CHN1_EMI_APB_BASE (IO_PHYS + 0x00205000) 184 #define CHN2_EMI_APB_BASE (IO_PHYS + 0x00209000) 185 #define CHN3_EMI_APB_BASE (IO_PHYS + 0x0020D000) 186 #define EMI_APB_BASE (IO_PHYS + 0x00429000) 187 #define INFRA_EMI_DEBUG_CFG_BASE (IO_PHYS + 0x00425000) 188 #define NEMI_SMPU_BASE (IO_PHYS + 0x0042f000) 189 #define SEMI_SMPU_BASE (IO_PHYS + 0x0052f000) 190 #define SUB_EMI_APB_BASE (IO_PHYS + 0x00529000) 191 #define SUB_INFRA_EMI_DEBUG_CFG_BASE (IO_PHYS + 0x00525000) 192 #define SUB_INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00504000) 193 194 /******************************************************************************* 195 * System counter frequency related constants 196 ******************************************************************************/ 197 #define SYS_COUNTER_FREQ_IN_HZ (13000000) 198 #define SYS_COUNTER_FREQ_IN_MHZ (13) 199 200 /******************************************************************************* 201 * Generic platform constants 202 ******************************************************************************/ 203 #define PLATFORM_STACK_SIZE (0x800) 204 #define SOC_CHIP_ID U(0x8196) 205 206 /******************************************************************************* 207 * Platform memory map related constants 208 ******************************************************************************/ 209 #define TZRAM_BASE (0x94600000) 210 #define TZRAM_SIZE (0x00200000) 211 212 /******************************************************************************* 213 * BL31 specific defines. 214 ******************************************************************************/ 215 /* 216 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 217 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 218 * little space for growth. 219 */ 220 #define BL31_BASE (TZRAM_BASE + 0x1000) 221 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 222 223 /******************************************************************************* 224 * Platform specific page table and MMU setup constants 225 ******************************************************************************/ 226 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) 227 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) 228 #define MAX_XLAT_TABLES (128) 229 #define MAX_MMAP_REGIONS (512) 230 231 /******************************************************************************* 232 * CPU PM definitions 233 *******************************************************************************/ 234 #define PLAT_CPU_PM_B_BUCK_ISO_ID (6) 235 #define PLAT_CPU_PM_ILDO_ID (6) 236 #define CPU_IDLE_SRAM_BASE (0x11B000) 237 #define CPU_IDLE_SRAM_SIZE (0x1000) 238 239 /******************************************************************************* 240 * SYSTIMER related definitions 241 ******************************************************************************/ 242 #define SYSTIMER_BASE (0x1C400000) 243 244 #endif /* PLATFORM_DEF_H */ 245